1082 skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock)  in skl_edp_set_pll_config()  argument
1086 	pipe_config->ddi_pll_sel = SKL_DPLL0;  in skl_edp_set_pll_config()
1087 	pipe_config->dpll_hw_state.cfgcr1 = 0;  in skl_edp_set_pll_config()
1088 	pipe_config->dpll_hw_state.cfgcr2 = 0;  in skl_edp_set_pll_config()
1121 	pipe_config->dpll_hw_state.ctrl1 = ctrl1;  in skl_edp_set_pll_config()
1125 hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config, int link_bw)  in hsw_dp_set_ddi_pll_sel()  argument
1129 		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;  in hsw_dp_set_ddi_pll_sel()
1132 		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;  in hsw_dp_set_ddi_pll_sel()
1135 		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;  in hsw_dp_set_ddi_pll_sel()
1188 		   struct intel_crtc_state *pipe_config, int link_bw)  in intel_dp_set_clock()  argument
1211 				pipe_config->dpll = divisor[i].dpll;  in intel_dp_set_clock()
1212 				pipe_config->clock_set = true;  in intel_dp_set_clock()
1328 			struct intel_crtc_state *pipe_config)  in intel_dp_compute_config()  argument
1332 	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;  in intel_dp_compute_config()
1335 	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);  in intel_dp_compute_config()
1356 		pipe_config->has_pch_encoder = true;  in intel_dp_compute_config()
1358 	pipe_config->has_dp_encoder = true;  in intel_dp_compute_config()
1359 	pipe_config->has_drrs = false;  in intel_dp_compute_config()
1360 	pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;  in intel_dp_compute_config()
1366 			intel_gmch_panel_fitting(intel_crtc, pipe_config,  in intel_dp_compute_config()
1369 			intel_pch_panel_fitting(intel_crtc, pipe_config,  in intel_dp_compute_config()
1383 	bpp = pipe_config->pipe_bpp;  in intel_dp_compute_config()
1438 		pipe_config->limited_color_range = true;  in intel_dp_compute_config()
1452 	pipe_config->pipe_bpp = bpp;  in intel_dp_compute_config()
1453 	pipe_config->port_clock = common_rates[clock];  in intel_dp_compute_config()
1457 		      pipe_config->port_clock, bpp);  in intel_dp_compute_config()
1463 			       pipe_config->port_clock,  in intel_dp_compute_config()
1464 			       &pipe_config->dp_m_n);  in intel_dp_compute_config()
1468 			pipe_config->has_drrs = true;  in intel_dp_compute_config()
1471 				pipe_config->port_clock,  in intel_dp_compute_config()
1472 				&pipe_config->dp_m2_n2);  in intel_dp_compute_config()
1476 		skl_edp_set_pll_config(pipe_config, common_rates[clock]);  in intel_dp_compute_config()
1478 		hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);  in intel_dp_compute_config()
1480 		intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);  in intel_dp_compute_config()
2212 				struct intel_crtc_state *pipe_config)  in intel_dp_get_config()  argument
2224 	pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;  in intel_dp_get_config()
2249 	pipe_config->base.adjusted_mode.flags |= flags;  in intel_dp_get_config()
2253 		pipe_config->limited_color_range = true;  in intel_dp_get_config()
2255 	pipe_config->has_dp_encoder = true;  in intel_dp_get_config()
2257 	intel_dp_get_m_n(crtc, pipe_config);  in intel_dp_get_config()
2261 			pipe_config->port_clock = 162000;  in intel_dp_get_config()
2263 			pipe_config->port_clock = 270000;  in intel_dp_get_config()
2266 	dotclock = intel_dotclock_calculate(pipe_config->port_clock,  in intel_dp_get_config()
2267 					    &pipe_config->dp_m_n);  in intel_dp_get_config()
2270 		ironlake_check_encoder_dotclock(pipe_config, dotclock);  in intel_dp_get_config()
2272 	pipe_config->base.adjusted_mode.crtc_clock = dotclock;  in intel_dp_get_config()
2275 	    pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {  in intel_dp_get_config()
2290 			      pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);  in intel_dp_get_config()
2291 		dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;  in intel_dp_get_config()