773 				struct intel_crtc_state *pipe_config)  in skl_ddi_clock_get()  argument
779 	dpll = pipe_config->ddi_pll_sel;  in skl_ddi_clock_get()
815 	pipe_config->port_clock = link_clock;  in skl_ddi_clock_get()
817 	if (pipe_config->has_dp_encoder)  in skl_ddi_clock_get()
818 		pipe_config->base.adjusted_mode.crtc_clock =  in skl_ddi_clock_get()
819 			intel_dotclock_calculate(pipe_config->port_clock,  in skl_ddi_clock_get()
820 						 &pipe_config->dp_m_n);  in skl_ddi_clock_get()
822 		pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;  in skl_ddi_clock_get()
826 			      struct intel_crtc_state *pipe_config)  in hsw_ddi_clock_get()  argument
832 	val = pipe_config->ddi_pll_sel;  in hsw_ddi_clock_get()
867 	pipe_config->port_clock = link_clock * 2;  in hsw_ddi_clock_get()
869 	if (pipe_config->has_pch_encoder)  in hsw_ddi_clock_get()
870 		pipe_config->base.adjusted_mode.crtc_clock =  in hsw_ddi_clock_get()
871 			intel_dotclock_calculate(pipe_config->port_clock,  in hsw_ddi_clock_get()
872 						 &pipe_config->fdi_m_n);  in hsw_ddi_clock_get()
873 	else if (pipe_config->has_dp_encoder)  in hsw_ddi_clock_get()
874 		pipe_config->base.adjusted_mode.crtc_clock =  in hsw_ddi_clock_get()
875 			intel_dotclock_calculate(pipe_config->port_clock,  in hsw_ddi_clock_get()
876 						 &pipe_config->dp_m_n);  in hsw_ddi_clock_get()
878 		pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;  in hsw_ddi_clock_get()
882 			 struct intel_crtc_state *pipe_config)  in intel_ddi_clock_get()  argument
887 		hsw_ddi_clock_get(encoder, pipe_config);  in intel_ddi_clock_get()
889 		skl_ddi_clock_get(encoder, pipe_config);  in intel_ddi_clock_get()
2084 			  struct intel_crtc_state *pipe_config)  in intel_ddi_get_config()  argument
2088 	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;  in intel_ddi_get_config()
2102 	pipe_config->base.adjusted_mode.flags |= flags;  in intel_ddi_get_config()
2106 		pipe_config->pipe_bpp = 18;  in intel_ddi_get_config()
2109 		pipe_config->pipe_bpp = 24;  in intel_ddi_get_config()
2112 		pipe_config->pipe_bpp = 30;  in intel_ddi_get_config()
2115 		pipe_config->pipe_bpp = 36;  in intel_ddi_get_config()
2123 		pipe_config->has_hdmi_sink = true;  in intel_ddi_get_config()
2127 			pipe_config->has_infoframe = true;  in intel_ddi_get_config()
2134 		pipe_config->has_dp_encoder = true;  in intel_ddi_get_config()
2135 		intel_dp_get_m_n(intel_crtc, pipe_config);  in intel_ddi_get_config()
2144 			pipe_config->has_audio = true;  in intel_ddi_get_config()
2148 	    pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {  in intel_ddi_get_config()
2163 			      pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);  in intel_ddi_get_config()
2164 		dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;  in intel_ddi_get_config()
2167 	intel_ddi_clock_get(encoder, pipe_config);  in intel_ddi_get_config()
2171 				     struct intel_crtc_state *pipe_config)  in intel_ddi_compute_config()  argument
2179 		pipe_config->cpu_transcoder = TRANSCODER_EDP;  in intel_ddi_compute_config()
2182 		return intel_hdmi_compute_config(encoder, pipe_config);  in intel_ddi_compute_config()
2184 		return intel_dp_compute_config(encoder, pipe_config);  in intel_ddi_compute_config()