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Searched refs:page_directory (Results 1 – 5 of 5) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/radeon/
Dradeon_vm.c141 list[0].robj = vm->page_directory; in radeon_vm_get_bos()
144 list[0].tv.bo = &vm->page_directory->tbo; in radeon_vm_get_bos()
240 uint64_t pd_addr = radeon_bo_gpu_offset(vm->page_directory); in radeon_vm_flush()
645 struct radeon_bo *pd = vm->page_directory; in radeon_vm_update_page_directory()
1203 NULL, &vm->page_directory); in radeon_vm_init()
1207 r = radeon_vm_clear_bo(rdev, vm->page_directory); in radeon_vm_init()
1209 radeon_bo_unref(&vm->page_directory); in radeon_vm_init()
1210 vm->page_directory = NULL; in radeon_vm_init()
1254 radeon_bo_unref(&vm->page_directory); in radeon_vm_fini()
Dradeon.h946 struct radeon_bo *page_directory; member
/linux-4.1.27/drivers/gpu/drm/i915/
Di915_gem_gtt.c473 dma_addr_t addr = ppgtt->pdp.page_directory[i]->daddr; in gen8_mm_switch()
504 if (WARN_ON(!ppgtt->pdp.page_directory[pdpe])) in gen8_ppgtt_clear_range()
507 pd = ppgtt->pdp.page_directory[pdpe]; in gen8_ppgtt_clear_range()
562 struct i915_page_directory_entry *pd = ppgtt->pdp.page_directory[pdpe]; in gen8_ppgtt_insert_entries()
612 if (WARN_ON(!ppgtt->pdp.page_directory[i])) in gen8_ppgtt_free()
615 gen8_free_page_tables(ppgtt->pdp.page_directory[i], ppgtt->base.dev); in gen8_ppgtt_free()
616 unmap_and_free_pd(ppgtt->pdp.page_directory[i]); in gen8_ppgtt_free()
628 if (!ppgtt->pdp.page_directory[i]->daddr) in gen8_ppgtt_unmap_pages()
631 pci_unmap_page(hwdev, ppgtt->pdp.page_directory[i]->daddr, PAGE_SIZE, in gen8_ppgtt_unmap_pages()
635 struct i915_page_directory_entry *pd = ppgtt->pdp.page_directory[i]; in gen8_ppgtt_unmap_pages()
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Dintel_lrc.c1818 reg_state[CTX_PDP3_UDW+1] = upper_32_bits(ppgtt->pdp.page_directory[3]->daddr); in populate_lr_context()
1819 reg_state[CTX_PDP3_LDW+1] = lower_32_bits(ppgtt->pdp.page_directory[3]->daddr); in populate_lr_context()
1820 reg_state[CTX_PDP2_UDW+1] = upper_32_bits(ppgtt->pdp.page_directory[2]->daddr); in populate_lr_context()
1821 reg_state[CTX_PDP2_LDW+1] = lower_32_bits(ppgtt->pdp.page_directory[2]->daddr); in populate_lr_context()
1822 reg_state[CTX_PDP1_UDW+1] = upper_32_bits(ppgtt->pdp.page_directory[1]->daddr); in populate_lr_context()
1823 reg_state[CTX_PDP1_LDW+1] = lower_32_bits(ppgtt->pdp.page_directory[1]->daddr); in populate_lr_context()
1824 reg_state[CTX_PDP0_UDW+1] = upper_32_bits(ppgtt->pdp.page_directory[0]->daddr); in populate_lr_context()
1825 reg_state[CTX_PDP0_LDW+1] = lower_32_bits(ppgtt->pdp.page_directory[0]->daddr); in populate_lr_context()
Di915_gem_gtt.h228 struct i915_page_directory_entry *page_directory[GEN8_LEGACY_PDPES]; member