| /linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/bios/ |
| D | vmap.c | 91 info->min = nv_ro32(bios, vmap + 0x00); in nvbios_vmap_entry_parse()
92 info->max = nv_ro32(bios, vmap + 0x04); in nvbios_vmap_entry_parse()
93 info->arg[0] = nv_ro32(bios, vmap + 0x08); in nvbios_vmap_entry_parse()
94 info->arg[1] = nv_ro32(bios, vmap + 0x0c); in nvbios_vmap_entry_parse()
95 info->arg[2] = nv_ro32(bios, vmap + 0x10); in nvbios_vmap_entry_parse()
100 info->min = nv_ro32(bios, vmap + 0x02); in nvbios_vmap_entry_parse()
101 info->max = nv_ro32(bios, vmap + 0x06); in nvbios_vmap_entry_parse()
102 info->arg[0] = nv_ro32(bios, vmap + 0x0a); in nvbios_vmap_entry_parse()
103 info->arg[1] = nv_ro32(bios, vmap + 0x0e); in nvbios_vmap_entry_parse()
104 info->arg[2] = nv_ro32(bios, vmap + 0x12); in nvbios_vmap_entry_parse()
[all …]
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| D | pmu.c | 52 data = nv_ro32(bios, bit_p.offset + 0x00); in nvbios_pmuTe()
99 info->data = nv_ro32(bios, data + 0x02); in nvbios_pmuEp()
115 info->init_addr_pmu = nv_ro32(bios, data + 0x08); in nvbios_pmuRm()
116 info->args_addr_pmu = nv_ro32(bios, data + 0x0c); in nvbios_pmuRm()
118 info->boot_addr_pmu = nv_ro32(bios, data + 0x10) + in nvbios_pmuRm()
119 nv_ro32(bios, data + 0x18); in nvbios_pmuRm()
120 info->boot_size = nv_ro32(bios, data + 0x1c) - in nvbios_pmuRm()
121 nv_ro32(bios, data + 0x18); in nvbios_pmuRm()
125 info->code_size = nv_ro32(bios, data + 0x20); in nvbios_pmuRm()
127 nv_ro32(bios, data + 0x24); in nvbios_pmuRm()
[all …]
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| D | timing.c | 133 p->timing[0] = nv_ro32(bios, data + 0x00); in nvbios_timingEp()
134 p->timing[1] = nv_ro32(bios, data + 0x04); in nvbios_timingEp()
135 p->timing[2] = nv_ro32(bios, data + 0x08); in nvbios_timingEp()
136 p->timing[3] = nv_ro32(bios, data + 0x0c); in nvbios_timingEp()
137 p->timing[4] = nv_ro32(bios, data + 0x10); in nvbios_timingEp()
138 p->timing[5] = nv_ro32(bios, data + 0x14); in nvbios_timingEp()
139 p->timing[6] = nv_ro32(bios, data + 0x18); in nvbios_timingEp()
140 p->timing[7] = nv_ro32(bios, data + 0x1c); in nvbios_timingEp()
141 p->timing[8] = nv_ro32(bios, data + 0x20); in nvbios_timingEp()
142 p->timing[9] = nv_ro32(bios, data + 0x24); in nvbios_timingEp()
[all …]
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| D | pll.c | 149 if (nv_ro32(bios, data + 3) == reg) { in pll_map_reg()
164 if (nv_ro32(bios, data) == map->reg) in pll_map_reg()
192 *reg = nv_ro32(bios, data + 3); in pll_map_type()
206 if (nv_ro32(bios, data) == map->reg) in pll_map_type()
248 info->vco1.min_freq = nv_ro32(bios, data + 0); in nvbios_pll_parse()
249 info->vco1.max_freq = nv_ro32(bios, data + 4); in nvbios_pll_parse()
250 info->vco2.min_freq = nv_ro32(bios, data + 8); in nvbios_pll_parse()
251 info->vco2.max_freq = nv_ro32(bios, data + 12); in nvbios_pll_parse()
252 info->vco1.min_inputfreq = nv_ro32(bios, data + 16); in nvbios_pll_parse()
253 info->vco2.min_inputfreq = nv_ro32(bios, data + 20); in nvbios_pll_parse()
[all …]
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| D | init.c | 475 u32 reg = nv_ro32(bios, table + (cond * 12) + 0); in init_condition_met()
476 u32 msk = nv_ro32(bios, table + (cond * 12) + 4); in init_condition_met()
477 u32 val = nv_ro32(bios, table + (cond * 12) + 8); in init_condition_met()
619 u32 reg = nv_ro32(bios, init->offset + 7); in init_io_restrict_prog()
629 u32 data = nv_ro32(bios, init->offset); in init_io_restrict_prog()
683 u32 reg = nv_ro32(bios, init->offset + 8); in init_io_restrict_pll()
733 u32 reg = nv_ro32(bios, init->offset + 1); in init_copy()
875 u32 reg = nv_ro32(bios, init->offset + 1); in init_andn_reg()
876 u32 mask = nv_ro32(bios, init->offset + 5); in init_andn_reg()
892 u32 reg = nv_ro32(bios, init->offset + 1); in init_or_reg()
[all …]
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| D | dcb.c | 49 if (nv_ro32(bios, dcb + 6) == 0x4edcbdcb) { in dcb_table()
57 if (nv_ro32(bios, dcb + 4) == 0x4edcbdcb) { in dcb_table()
129 u32 conn = nv_ro32(bios, dcb + 0x00); in dcb_outp_parse()
143 u32 conf = nv_ro32(bios, dcb + 0x04); in dcb_outp_parse()
218 if (nv_ro32(bios, outp) == 0x00000000) in dcb_outp_foreach()
220 if (nv_ro32(bios, outp) == 0xffffffff) in dcb_outp_foreach()
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| D | volt.c | 85 info->base = nv_ro32(bios, volt + 0x04); in nvbios_volt_parse()
94 info->min = nv_ro32(bios, volt + 0x0a); in nvbios_volt_parse()
95 info->max = nv_ro32(bios, volt + 0x0e); in nvbios_volt_parse()
96 info->base = nv_ro32(bios, volt + 0x12) & 0x00ffffff; in nvbios_volt_parse()
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| D | P0260.c | 37 data = nv_ro32(bios, bit_P.offset + 0x60); in nvbios_P0260Te()
75 info->data = nv_ro32(bios, data); in nvbios_P0260Ep()
101 info->data = nv_ro32(bios, data); in nvbios_P0260Xp()
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| D | npde.c | 35 switch (nv_ro32(bios, data + 0x00)) { in nvbios_npdeTe()
40 data, nv_ro32(bios, data + 0x00)); in nvbios_npdeTe()
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| D | gpio.c | 94 u32 info = nv_ro32(bios, data); in dcb_gpio_parse()
103 u32 info = nv_ro32(bios, data + 0); in dcb_gpio_parse()
104 u8 info1 = nv_ro32(bios, data + 4); in dcb_gpio_parse()
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| D | pcir.c | 33 switch (nv_ro32(bios, data + 0x00)) { in nvbios_pcirTe()
42 data, nv_ro32(bios, data + 0x00)); in nvbios_pcirTe()
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| D | M0209.c | 37 data = nv_ro32(bios, bit_M.offset + 0x09); in nvbios_M0209Te()
125 info->data[i] = nv_ro32(bios, data + off); in nvbios_M0209Sp()
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| D | perf.c | 106 info->core = nv_ro32(bios, perf + 0x01) * 10; in nvbios_perfEp()
107 info->memory = nv_ro32(bios, perf + 0x05) * 20; in nvbios_perfEp()
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| D | fan.c | 89 fan->pwm_freq = nv_ro32(bios, data + 0x0b) & 0xffffff; in nvbios_fan_parse()
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| D | M0205.c | 37 data = nv_ro32(bios, bit_M.offset + 0x05); in nvbios_M0205Te()
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| D | i2c.c | 77 u32 ent_value = nv_ro32(bios, ent); in dcb_i2c_parse()
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| D | disp.c | 102 info->mask = nv_ro32(bios, data + 0x02); in nvbios_outp_parse()
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| D | rammap.c | 96 temp = nv_ro32(bios, data + 0x09); in nvbios_rammapEp()
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| /linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/ce/ |
| D | gt215.c | 84 u32 dispatch = nv_ro32(falcon, 0x01c); in gt215_ce_intr()
85 u32 stat = nv_ro32(falcon, 0x008) & dispatch & ~(dispatch >> 16); in gt215_ce_intr()
86 u64 inst = nv_ro32(falcon, 0x050) & 0x3fffffff; in gt215_ce_intr()
87 u32 ssta = nv_ro32(falcon, 0x040) & 0x0000ffff; in gt215_ce_intr()
88 u32 addr = nv_ro32(falcon, 0x040) >> 16; in gt215_ce_intr()
91 u32 data = nv_ro32(falcon, 0x044); in gt215_ce_intr()
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| /linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/ |
| D | xtensa.c | 59 u32 unk104 = nv_ro32(xtensa, 0xd04); in _nvkm_xtensa_intr()
60 u32 intr = nv_ro32(xtensa, 0xc20); in _nvkm_xtensa_intr()
61 u32 chan = nv_ro32(xtensa, 0xc28); in _nvkm_xtensa_intr()
62 u32 unk10c = nv_ro32(xtensa, 0xd0c); in _nvkm_xtensa_intr()
67 intr = nv_ro32(xtensa, 0xc20); in _nvkm_xtensa_intr()
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| D | falcon.c | 31 u32 dispatch = nv_ro32(falcon, 0x01c); in nvkm_falcon_intr()
32 u32 intr = nv_ro32(falcon, 0x008) & dispatch & ~(dispatch >> 16); in nvkm_falcon_intr()
90 caps = nv_ro32(falcon, 0x12c); in _nvkm_falcon_init()
95 caps = nv_ro32(falcon, 0x108); in _nvkm_falcon_init()
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| /linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/ |
| D | nv40.c | 38 u32 dma0 = nv_ro32(imem, inst + 0); in nv40_mpeg_mthd_dma()
39 u32 dma1 = nv_ro32(imem, inst + 4); in nv40_mpeg_mthd_dma()
40 u32 dma2 = nv_ro32(imem, inst + 8); in nv40_mpeg_mthd_dma()
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| D | nv31.c | 65 u32 dma0 = nv_ro32(imem, inst + 0); in nv31_mpeg_mthd_dma()
66 u32 dma1 = nv_ro32(imem, inst + 4); in nv31_mpeg_mthd_dma()
67 u32 dma2 = nv_ro32(imem, inst + 8); in nv31_mpeg_mthd_dma()
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| /linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ |
| D | nv44.c | 45 tmp[0] = nv_ro32(pgt, base + 0x0); in nv44_vm_fill()
46 tmp[1] = nv_ro32(pgt, base + 0x4); in nv44_vm_fill()
47 tmp[2] = nv_ro32(pgt, base + 0x8); in nv44_vm_fill()
48 tmp[3] = nv_ro32(pgt, base + 0xc); in nv44_vm_fill()
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| /linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/timer/ |
| D | base.c | 38 if ((nv_ro32(obj, addr) & mask) == data) in nvkm_timer_wait_eq()
58 if ((nv_ro32(obj, addr) & mask) != data) in nvkm_timer_wait_ne()
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| /linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ |
| D | gm204.c | 40 nv_wr32(priv, 0x10a184, nv_ro32(bios, img + i)); in pmu_code()
57 nv_wr32(priv, 0x10a1c4, nv_ro32(bios, img + i)); in pmu_data()
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| D | nv05.c | 82 u32 scramble = nv_ro32(bios, data); in nv05_devinit_meminit()
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| /linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/therm/ |
| D | g84.c | 38 if (nv_ro32(fuse, 0x1a8) == 1) in g84_temp_get()
50 if (nv_ro32(fuse, 0x1a8) == 1) { in g84_sensor_setup()
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| /linux-4.1.27/drivers/gpu/drm/nouveau/include/nvkm/core/ |
| D | object.h | 154 nv_ro32(void *obj, u64 addr) in nv_ro32() function
185 u32 temp = nv_ro32(obj, addr); in nv_mo32()
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| /linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/gr/ |
| D | nv04.c | 453 tmp = nv_ro32(object, 0x00); in nv04_gr_set_ctx1()
468 ctx1 = nv_ro32(object, 0x00); in nv04_gr_set_ctx_val()
472 tmp = nv_ro32(object, 0x0c); in nv04_gr_set_ctx_val()
514 u32 class = nv_ro32(object, 0) & 0xff; in nv04_gr_mthd_set_operation()
574 return nv_ro32(imem, inst); in nv04_gr_mthd_bind_class()
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| D | ctxgf100.c | 1353 priv->data[i / 4] = nv_ro32(chan, 0x80000 + i); in gf100_grctx_generate()
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| /linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/ |
| D | gf110.c | 35 u32 data = nv_ro32(bios, entry); in gf110_gpio_reset()
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| D | nv50.c | 36 u32 data = nv_ro32(bios, entry); in nv50_gpio_reset()
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| /linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/core/ |
| D | ramht.c | 50 if (!nv_ro32(ramht, co + 4)) { in nvkm_ramht_insert()
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| D | ioctl.c | 252 args->v0.data = nv_ro32(object, args->v0.addr); in nvkm_ioctl_rd()
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| /linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/ |
| D | base.c | 96 iobj->suspend[i / 4] = nv_ro32(iobj, i); in _nvkm_instmem_fini()
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| D | nv04.c | 37 return nv_ro32(priv, node->mem->offset + addr); in nv04_instobj_rd32()
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| /linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/ |
| D | nv04.c | 67 offset = nv_ro32(pgt, 8 + (offset >> 10)); in nv04_dmaobj_bind()
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| /linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/fifo/ |
| D | nv04.c | 219 u32 cv = (nv_ro32(fctx, c->ctxp + data) & ~cm); in nv04_fifo_chan_fini()
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| /linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| D | ramgk104.c | 1338 data = nv_ro32(bios, data + 0x10); /* guess u32... */ in gk104_ram_init()
1346 .offset = nv_ro32(bios, data), in gk104_ram_init()
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