Searched refs:mrc (Results 1 - 149 of 149) sorted by relevance

/linux-4.1.27/arch/arm/mach-shmobile/
H A Dsetup-rcar-gen2.c69 " mrc p15, 0, r1, c1, c1, 0\n" rcar_gen2_timer_init()
147 struct memory_reserve_config *mrc = data; rcar_gen2_scan_mem() local
173 if (size < mrc->reserved) rcar_gen2_scan_mem()
176 if (base < mrc->base) rcar_gen2_scan_mem()
180 mrc->base = base + size - mrc->reserved; rcar_gen2_scan_mem()
181 mrc->size = mrc->reserved; rcar_gen2_scan_mem()
191 struct memory_reserve_config mrc; rcar_gen2_reserve() local
194 memset(&mrc, 0, sizeof(mrc)); rcar_gen2_reserve()
195 mrc.reserved = SZ_256M; rcar_gen2_reserve()
197 of_scan_flat_dt(rcar_gen2_scan_mem, &mrc); rcar_gen2_reserve()
199 if (mrc.size && memblock_is_region_memory(mrc.base, mrc.size)) rcar_gen2_reserve()
200 dma_contiguous_reserve_area(mrc.size, mrc.base, 0, rcar_gen2_reserve()
H A Dplatsmp-apmu.c149 " mrc p15, 0, %0, c1, c0, 0\n" cpu_enter_lowpower_a15()
162 " mrc p15, 0, %0, c1, c0, 1\n" cpu_enter_lowpower_a15()
187 asm volatile("mrc p15, 0, %0, c1, c0, 0\n" cpu_leave_lowpower()
190 " mrc p15, 0, %0, c1, c0, 1\n" cpu_leave_lowpower()
H A Dheadsmp-scu.S30 mrc p15, 0, r1, c0, c0, 5 @ read MIPDR
H A Dheadsmp.S50 mrc p15, 0, r1, c0, c0, 5 @ r1 = MPIDR
/linux-4.1.27/arch/arm/include/asm/
H A Darch_timer.h54 asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val)); arch_timer_reg_read_cp15()
57 asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val)); arch_timer_reg_read_cp15()
63 asm volatile("mrc p15, 0, %0, c14, c3, 1" : "=r" (val)); arch_timer_reg_read_cp15()
66 asm volatile("mrc p15, 0, %0, c14, c3, 0" : "=r" (val)); arch_timer_reg_read_cp15()
77 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val)); arch_timer_get_cntfrq()
102 asm volatile("mrc p15, 0, %0, c14, c1, 0" : "=r" (cntkctl)); arch_timer_get_cntkctl()
H A Ddcc.h18 asm volatile("mrc p14, 0, %0, c0, c1, 0 @ read comms ctrl reg" __dcc_getstatus()
28 asm volatile("mrc p14, 0, %0, c0, c5, 0 @ read comms data reg" __dcc_getchar()
H A Dsmp_scu.h21 asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (pa)); scu_a9_get_base()
H A Dcp15.h57 asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc"); get_cr()
71 asm("mrc p15, 0, %0, c1, c0, 1 @ get AUXCR" : "=r" (val)); get_auxcr()
89 asm("mrc p15, 0, %0, c1, c0, 2 @ get copro access" get_copro_access()
H A Dtls.h13 mrc p15, 0, \tmp2, c13, c0, 2 @ get the user r/w register
104 __asm__("mrc p15, 0, %0, c13, c0, 2" : "=r" (reg)); get_tpuser()
H A Dpercpu.h39 asm("mrc p15, 0, %0, c13, c0, 4" : "=r" (off) __my_cpu_offset()
H A Dhw_breakpoint.h106 asm volatile("mrc p14, 0, %0, " #N "," #M ", " #OP2 : "=r" (VAL));\
H A Dcputype.h90 asm("mrc p15, 0, %0, c0, c0, " __stringify(reg) \
98 * The memory clobber prevents gcc 4.5 from reordering the mrc before
105 asm("mrc p15, 0, %0, c0, " ext_reg \
H A Dproc-fns.h145 __asm__("mrc p15, 0, %0, c2, c0, 0" \
H A Dcacheflush.h471 "mrc p15, 0, r0, c1, c0, 0 @ get SCTLR \n\t" \
476 "mrc p15, 0, r0, c1, c0, 1 @ get ACTLR \n\t" \
/linux-4.1.27/arch/arm/mach-spear/
H A Dhotplug.c29 " mrc p15, 0, %0, c1, c0, 1\n" cpu_enter_lowpower()
32 " mrc p15, 0, %0, c1, c0, 0\n" cpu_enter_lowpower()
44 asm volatile("mrc p15, 0, %0, c1, c0, 0\n" cpu_leave_lowpower()
47 " mrc p15, 0, %0, c1, c0, 1\n" cpu_leave_lowpower()
H A Dheadsmp.S24 mrc p15, 0, r0, c0, c0, 5
35 mrc p15, 0, r0, c1, c0, 1
/linux-4.1.27/arch/arm/mach-realview/
H A Dhotplug.c28 " mrc p15, 0, %0, c1, c0, 1\n" cpu_enter_lowpower()
31 " mrc p15, 0, %0, c1, c0, 0\n" cpu_enter_lowpower()
43 asm volatile( "mrc p15, 0, %0, c1, c0, 0\n" cpu_leave_lowpower()
46 " mrc p15, 0, %0, c1, c0, 1\n" cpu_leave_lowpower()
/linux-4.1.27/arch/arm/mach-vexpress/
H A Dhotplug.c28 " mrc p15, 0, %0, c1, c0, 1\n" cpu_enter_lowpower()
31 " mrc p15, 0, %0, c1, c0, 0\n" cpu_enter_lowpower()
44 "mrc p15, 0, %0, c1, c0, 0\n" cpu_leave_lowpower()
47 " mrc p15, 0, %0, c1, c0, 1\n" cpu_leave_lowpower()
/linux-4.1.27/arch/arm/mm/
H A Dproc-v7.S33 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
55 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
99 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
100 mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID
103 mrc p15, 0, r6, c3, c0, 0 @ Domain ID
107 mrc p15, 0, r7, c2, c0, 1 @ TTB 1
109 mrc p15, 0, r11, c2, c0, 2 @ TTB control register
111 mrc p15, 0, r8, c1, c0, 0 @ Control register
112 mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register
113 mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control
144 mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register
185 mrc p15, 0, r4, c15, c0, 1 @ Diagnostic register
186 mrc p15, 0, r5, c15, c0, 0 @ Power register
194 mrc p15, 0, r10, c15, c0, 1 @ Read Diagnostic register
197 mrc p15, 0, r10, c15, c0, 0 @ Read Power register
224 mrc p15, 1, r6, c15, c1, 0 @ save CP15 - extra features
225 mrc p15, 1, r7, c15, c2, 0 @ save CP15 - Aux Func Modes Ctrl 0
226 mrc p15, 1, r8, c15, c1, 2 @ save CP15 - Aux Debug Modes Ctrl 2
227 mrc p15, 1, r9, c15, c1, 1 @ save CP15 - Aux Debug Modes Ctrl 1
228 mrc p15, 0, r10, c9, c14, 0 @ save CP15 - PMC
276 ALT_SMP(mrc p15, 0, r0, c1, c0, 1)
311 mrc p15, 1, r0, c15, c1, 1
318 mrc p15, 1, r0, c15, c1, 2
324 mrc p15, 1, r0, c15, c2, 0
333 mrc p15, 1, r0, c15, c1, 0
346 mrc p15, 0, r0, c0, c0, 0 @ read main ID register
440 mrc p15, 0, r0, c0, c1, 0 @ read ID_PFR0 for ThumbEE
446 mrc p14, 6, r0, c0, c0, 0 @ load TEECR
458 mrc p15, 0, r0, c1, c0, 0 @ read control register
H A Dproc-v6.S42 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
60 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
109 mrc p15, 0, r2, c13, c0, 1 @ read current context ID
142 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
144 mrc p15, 0, r5, c3, c0, 0 @ Domain ID
145 mrc p15, 0, r6, c2, c0, 1 @ Translation table base 1
147 mrc p15, 0, r7, c1, c0, 1 @ auxiliary control register
148 mrc p15, 0, r8, c1, c0, 2 @ co-processor access control
149 mrc p15, 0, r9, c1, c0, 0 @ control register
200 ALT_SMP(mrc p15, 0, r0, c1, c0, 1) @ Enable SMP/nAMP mode
225 mrc p15, 0, r0, c1, c0, 0 @ read control register
237 mrc p15, 0, r5, c0, c0, 0 @ get processor id
H A Dproc-sa1100.S57 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
81 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
178 mrc p15, 0, r4, c3, c0, 0 @ domain ID
179 mrc p15, 0, r5, c13, c0, 0 @ PID
180 mrc p15, 0, r6, c1, c0, 0 @ control reg
211 mrc p15, 0, r0, c1, c0 @ get control register v4
H A Dproc-arm926.S64 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
88 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
104 mrc p15, 0, r1, c1, c0, 0 @ Read control register
148 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
375 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
408 mrc p15, 0, r4, c13, c0, 0 @ PID
409 mrc p15, 0, r5, c3, c0, 0 @ Domain ID
410 mrc p15, 0, r6, c1, c0, 0 @ Control register
445 mrc p15, 0, r0, c1, c0 @ get control register v4
H A Dproc-mohawk.S54 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
78 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
356 mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode
357 mrc p15, 0, r5, c15, c1, 0 @ CP access reg
358 mrc p15, 0, r6, c13, c0, 0 @ PID
359 mrc p15, 0, r7, c3, c0, 0 @ domain ID
360 mrc p15, 0, r8, c1, c0, 1 @ auxiliary control reg
361 mrc p15, 0, r9, c1, c0, 0 @ control reg
400 mrc p15, 0, r0, c1, c0 @ get control register
H A Dcache-tauros2.c119 "mrc p15, 0, %0, c1, c0, 0\n\t" tauros2_disable()
129 "mrc p15, 0, %0, c1, c0, 0\n\t" tauros2_resume()
140 __asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (u)); read_extra_features()
159 __asm__("mrc p15, 0, %0, c0, c1, 7\n" : "=r" (mmfr3)); read_mmfr3()
168 __asm__("mrc p15, 0, %0, c1, c0, 1\n" : "=r" (actlr)); read_actlr()
H A Dcache-xsc3l2.c38 __asm__("mrc p15, 1, %0, c0, c0, 1" : "=r" (l2ctype)); xsc3_l2_present()
58 __asm__("mrc p15, 1, %0, c0, c0, 1" : "=r" (l2ctype)); xsc3_l2_inv_all()
168 __asm__("mrc p15, 1, %0, c0, c0, 1" : "=r" (l2ctype)); xsc3_l2_flush_all()
H A Dproc-arm740.S41 mrc p15, 0, r0, c1, c0, 0
56 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
113 mrc p15, 0, r0, c1, c0 @ get control register
H A Dproc-sa110.S49 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
73 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
173 mrc p15, 0, r0, c1, c0 @ get control register v4
H A Dproc-xsc3.S59 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
92 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
112 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
419 mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode
420 mrc p15, 0, r5, c15, c1, 0 @ CP access reg
421 mrc p15, 0, r6, c13, c0, 0 @ PID
422 mrc p15, 0, r7, c3, c0, 0 @ domain ID
423 mrc p15, 0, r8, c1, c0, 1 @ auxiliary control reg
424 mrc p15, 0, r9, c1, c0, 0 @ control reg
463 mrc p15, 0, r0, c1, c0, 1 @ get auxiliary control reg
472 mrc p15, 1, r0, c0, c0, 1 @ get L2 present information
477 mrc p15, 0, r0, c1, c0, 0 @ get control register
H A Dproc-xscale.S72 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
78 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
118 mrc p15, 0, r1, c1, c0, 1
127 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
151 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
534 mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode
535 mrc p15, 0, r5, c15, c1, 0 @ CP access reg
536 mrc p15, 0, r6, c13, c0, 0 @ PID
537 mrc p15, 0, r7, c3, c0, 0 @ domain ID
538 mrc p15, 0, r8, c1, c0, 1 @ auxiliary control reg
539 mrc p15, 0, r9, c1, c0, 0 @ control reg
572 mrc p15, 0, r0, c1, c0, 0 @ get control register
H A Dproc-arm720.S57 mrc p15, 0, r0, c1, c0, 0
111 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
126 mrc p15, 0, r0, c1, c0 @ get control register
156 mrc p15, 0, r0, c1, c0 @ get control register
H A Dproc-arm1026.S71 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
95 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
146 1: mrc p15, 0, r15, c7, c14, 3 @ test, clean, invalidate
371 1: mrc p15, 0, r15, c7, c14, 3 @ test, clean, invalidate
414 mrc p15, 0, r0, c1, c0 @ get control register v4
H A Dproc-arm920.S72 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
96 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
393 mrc p15, 0, r4, c13, c0, 0 @ PID
394 mrc p15, 0, r5, c3, c0, 0 @ Domain ID
395 mrc p15, 0, r6, c1, c0, 0 @ Control register
423 mrc p15, 0, r0, c1, c0 @ get control register v4
H A Dproc-fa526.S41 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
68 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
160 mrc p15, 0, r0, c1, c0 @ get control register v4
H A Dcache-v7.S37 mrc p15, 1, r0, c0, c0, 0
92 mrc p15, 1, r0, c0, c0, 1 @ read clidr, r0 = clidr
98 ALT_SMP(mrc p15, 0, r2, c0, c0, 0) @ read main ID register
120 mrc p15, 1, r0, c0, c0, 1 @ read clidr
137 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
H A Dproc-feroceon.S60 mrc p15, 0, r0, c0, c0, 1 @ read cache type register
85 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
109 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
523 mrc p15, 0, r4, c13, c0, 0 @ PID
524 mrc p15, 0, r5, c3, c0, 0 @ Domain ID
525 mrc p15, 0, r6, c1, c0, 0 @ Control register
554 mrc p15, 0, r0, c1, c0 @ get control register v4
H A Dproc-arm1022.S71 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
95 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
420 mrc p15, 0, r0, c1, c0 @ get control register v4
H A Dproc-arm940.S40 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
57 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
326 mrc p15, 0, r0, c1, c0 @ get control register
H A Dproc-arm946.S47 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
64 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
379 mrc p15, 0, r0, c1, c0 @ get control register
H A Dproc-arm925.S95 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
128 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
142 mrc p15, 0, r1, c1, c0, 0 @ Read control register
463 mrc p15, 0, r0, c1, c0 @ get control register v4
H A Dabort-lv4t.S20 mrc p15, 0, r1, c5, c0, 0 @ get FSR
21 mrc p15, 0, r0, c6, c0, 0 @ get FAR
H A Dcontext.c97 " mrc p15, 0, %0, c2, c0, 1 @ read TTBR1\n" cpu_set_reserved_ttbr0()
117 " mrc p15, 0, %0, c13, c0, 1\n" contextidr_notifier()
H A Dproc-arm1020.S80 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
104 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
455 mrc p15, 0, r0, c1, c0 @ get control register v4
H A Dproc-arm1020e.S80 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
104 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
436 mrc p15, 0, r0, c1, c0 @ get control register v4
H A Dproc-arm922.S74 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
98 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
401 mrc p15, 0, r0, c1, c0 @ get control register v4
H A Dproc-v7-2level.S53 mrc p15, 0, r2, c13, c0, 1 @ read current context ID
H A Dproc-v7-3level.S133 mrc p15, 0, \tmp, c2, c0, 2 @ TTB control register
H A Dnommu.c57 asm("mrc p15, 0, %0, c6, c1, 0" : "=r" (v)); drbar_read()
83 asm("mrc p15, 0, %0, c6, c1, 1" : "=r" (v)); irbar_read()
H A Dcache-feroceon-l2.c296 __asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (u)); read_extra_features()
H A Dcache-l2x0.c1374 asm volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (u)); aurora_enable_no_outer()
/linux-4.1.27/arch/arm/kvm/
H A Dinit.S79 mrc p15, 4, r0, c2, c0, 2 @ HTCR
82 mrc p15, 0, r1, c2, c0, 2 @ TTBCR
87 mrc p15, 4, r1, c2, c1, 2 @ VTCR
97 mrc p15, 0, r0, c10, c2, 0
99 mrc p15, 0, r0, c10, c2, 1
115 mrc p15, 4, r0, c1, c0, 0 @ HSCR
118 mrc p15, 0, r1, c1, c0, 0 @ SCTLR
H A Dinterrupts_head.S251 mrc p15, 0, r2, c1, c0, 0 @ SCTLR
252 mrc p15, 0, r3, c1, c0, 2 @ CPACR
253 mrc p15, 0, r4, c2, c0, 2 @ TTBCR
254 mrc p15, 0, r5, c3, c0, 0 @ DACR
257 mrc p15, 0, r10, c10, c2, 0 @ PRRR
258 mrc p15, 0, r11, c10, c2, 1 @ NMRR
259 mrc p15, 2, r12, c0, c0, 0 @ CSSELR
277 mrc p15, 0, r2, c13, c0, 1 @ CID
278 mrc p15, 0, r3, c13, c0, 2 @ TID_URW
279 mrc p15, 0, r4, c13, c0, 3 @ TID_URO
280 mrc p15, 0, r5, c13, c0, 4 @ TID_PRIV
281 mrc p15, 0, r6, c5, c0, 0 @ DFSR
282 mrc p15, 0, r7, c5, c0, 1 @ IFSR
283 mrc p15, 0, r8, c5, c1, 0 @ ADFSR
284 mrc p15, 0, r9, c5, c1, 1 @ AIFSR
285 mrc p15, 0, r10, c6, c0, 0 @ DFAR
286 mrc p15, 0, r11, c6, c0, 2 @ IFAR
287 mrc p15, 0, r12, c12, c0, 0 @ VBAR
305 mrc p15, 0, r2, c14, c1, 0 @ CNTKCTL
307 mrc p15, 0, r6, c10, c3, 0 @ AMAIR0
308 mrc p15, 0, r7, c10, c3, 1 @ AMAIR1
519 mrc p15, 0, r2, c14, c3, 1 @ CNTV_CTL
538 mrc p15, 4, r2, c14, c1, 0 @ CNTHCTL
553 mrc p15, 4, r2, c14, c1, 0 @ CNTHCTL
585 mrc p15, 4, r2, c1, c1, 3
603 mrc p15, 4, r2, c1, c1, 2
627 mrc p15, 4, r2, c1, c1, 1
650 mrc p15, 4, vcpu, c13, c0, 2 @ HTPIDR
H A Dinterrupts.S195 mrc p15, 0, r2, c0, c0, 0
199 mrc p15, 0, r2, c0, c0, 5
289 mrc p15, 4, r2, c5, c2, 0 @ HSR
290 mrc p15, 4, r1, c6, c0, 0 @ HDFAR
295 mrc p15, 4, r2, c5, c2, 0 @ HSR
296 mrc p15, 4, r1, c6, c0, 2 @ HIFAR
362 mrc p15, 4, r1, c5, c2, 0 @ HSR
417 mrc p15, 4, r2, c6, c0, 0 @ HDFAR
435 mrc p15, 4, r1, c5, c2, 0 @ HSR
H A Dcoproc.c150 asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr)); reset_l2ctlr()
167 asm volatile("mrc p15, 0, %0, c1, c0, 1\n" : "=r" (actlr)); reset_actlr()
501 * kvm_handle_cp15_32 -- handles a mrc/mcr trap on a guest CP15 access
604 /* Unfortunately, there's no register-argument for mrc, so generate. */
611 asm volatile("mrc p15, " __stringify(op1) \
784 asm volatile("mrc p15, 1, %0, c0, c0, 0" : "=r" (ccsidr)); get_ccsidr()
1230 asm volatile("mrc p15, 1, %0, c0, c0, 1" : "=r" (cache_levels)); kvm_coproc_table_init()
H A Dtrace.h157 (__entry->is_write) ? "mcr" : "mrc",
/linux-4.1.27/arch/arm/kernel/
H A Dpj4-cp0.c58 "mrc p15, 0, %0, c1, c0, 2\n\t" pj4_cp_access_read()
69 "mrc p15, 0, %0, c1, c0, 2\n\t" pj4_cp_access_write()
89 __asm__ __volatile__ ("mrc p1, 0, %0, c0, c0, 0\n" : "=r" (wcid)); pj4_get_iwmmxt_version()
H A Diwmmxt.S76 XSC(mrc p15, 0, r2, c15, c1, 0)
77 PJ4(mrc p15, 0, r2, c1, c0, 2)
96 mrc p15, 0, r2, c2, c0, 0
213 XSC(mrc p15, 0, r4, c15, c1, 0)
216 PJ4(mrc p15, 0, r4, c1, c0, 2)
222 mrc p15, 0, r2, c2, c0, 0
232 mrc p15, 0, r2, c2, c0, 0
325 XSC(mrc p15, 0, r1, c15, c1, 0)
326 PJ4(mrc p15, 0, r1, c1, c0, 2)
344 mrc p15, 0, r1, c2, c0, 0
H A Dperf_event_xscale.c100 asm volatile("mrc p14, 0, %0, c0, c0, 0" : "=r" (val)); xscale1pmu_read_pmnc()
319 asm volatile("mrc p14, 0, %0, c1, c0, 0" : "=r" (val)); xscale1pmu_read_counter()
322 asm volatile("mrc p14, 0, %0, c2, c0, 0" : "=r" (val)); xscale1pmu_read_counter()
325 asm volatile("mrc p14, 0, %0, c3, c0, 0" : "=r" (val)); xscale1pmu_read_counter()
398 asm volatile("mrc p14, 0, %0, c0, c1, 0" : "=r" (val)); xscale2pmu_read_pmnc()
415 asm volatile("mrc p14, 0, %0, c5, c1, 0" : "=r" (val)); xscale2pmu_read_overflow_flags()
429 asm volatile("mrc p14, 0, %0, c8, c1, 0" : "=r" (val)); xscale2pmu_read_event_select()
443 asm volatile("mrc p14, 0, %0, c4, c1, 0" : "=r" (val)); xscale2pmu_read_int_enable()
683 asm volatile("mrc p14, 0, %0, c1, c1, 0" : "=r" (val)); xscale2pmu_read_counter()
686 asm volatile("mrc p14, 0, %0, c0, c2, 0" : "=r" (val)); xscale2pmu_read_counter()
689 asm volatile("mrc p14, 0, %0, c1, c2, 0" : "=r" (val)); xscale2pmu_read_counter()
692 asm volatile("mrc p14, 0, %0, c2, c2, 0" : "=r" (val)); xscale2pmu_read_counter()
695 asm volatile("mrc p14, 0, %0, c3, c2, 0" : "=r" (val)); xscale2pmu_read_counter()
H A Dhead-nommu.S58 mrc p15, 0, r9, c0, c0 @ get processor id
103 mrc p15, 0, r9, c0, c0 @ get processor id
200 mrc p15, 0, r0, c0, c1, 4 @ Read ID_MMFR0
207 mrc p15, 0, r0, c0, c0, 4 @ MPUIR
252 mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR
H A Dxscale-cp0.c95 "mrc p15, 0, %0, c15, c1, 0\n\t" xscale_cp_access_read()
107 "mrc p15, 0, %0, c15, c1, 0\n\t" xscale_cp_access_write()
H A Dhyp-stub.S140 mrc p15, 4, r7, c1, c1, 1 @ HDCR
146 mrc p15, 0, r7, c0, c1, 1 @ ID_PFR1
151 mrc p15, 4, r7, c14, c1, 0 @ CNTHCTL
158 mrc p15, 0, r7, c14, c3, 1 @ CNTV_CTL
H A Dthumbee.c33 asm("mrc p14, 6, %0, c1, c0, 0\n" : "=r" (v)); teehbr_read()
H A Dperf_event_v7.c600 asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(val)); armv7_pmnc_read()
645 asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (value)); armv7pmu_read_counter()
648 asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (value)); armv7pmu_read_counter()
711 asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val)); armv7_pmnc_getreset_flags()
728 asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val)); armv7_pmnc_dump_regs()
731 asm volatile("mrc p15, 0, %0, c9, c12, 1" : "=r" (val)); armv7_pmnc_dump_regs()
734 asm volatile("mrc p15, 0, %0, c9, c14, 1" : "=r" (val)); armv7_pmnc_dump_regs()
737 asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val)); armv7_pmnc_dump_regs()
740 asm volatile("mrc p15, 0, %0, c9, c12, 5" : "=r" (val)); armv7_pmnc_dump_regs()
743 asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (val)); armv7_pmnc_dump_regs()
749 asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (val)); armv7_pmnc_dump_regs()
752 asm volatile("mrc p15, 0, %0, c9, c13, 1" : "=r" (val)); armv7_pmnc_dump_regs()
1184 asm volatile("mrc p15, 1, %0, c9, c15, 0" : "=r" (val)); krait_read_pmresrn()
1187 asm volatile("mrc p15, 1, %0, c9, c15, 1" : "=r" (val)); krait_read_pmresrn()
1190 asm volatile("mrc p15, 1, %0, c9, c15, 2" : "=r" (val)); krait_read_pmresrn()
1219 asm volatile("mrc p10, 7, %0, c11, c0, 0" : "=r" (val)); venum_read_pmresr()
1563 asm volatile("mrc p15, 0, %0, c15, c0, 0" : "=r" (val)); scorpion_read_pmresrn()
1566 asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r" (val)); scorpion_read_pmresrn()
1569 asm volatile("mrc p15, 2, %0, c15, c0, 0" : "=r" (val)); scorpion_read_pmresrn()
1572 asm volatile("mrc p15, 3, %0, c15, c2, 0" : "=r" (val)); scorpion_read_pmresrn()
H A Ddebug.S30 mrc p15, 0, \rx, c1, c0
H A Dhead.S94 mrc p15, 0, r9, c0, c0 @ get processor id
101 mrc p15, 0, r3, c0, c1, 4 @ read ID_MMFR0
371 mrc p15, 0, r9, c0, c0 @ get processor id
474 mrc p15, 0, r3, c0, c0, 0 @ read id reg
499 mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
515 mrc p15, 4, r0, c15, c0 @ get SCU base address
H A Dprocess.c150 asm("mrc p15, 0, %0, c2, c0\n\t" __show_regs()
151 "mrc p15, 0, %1, c3, c0\n" __show_regs()
157 asm("mrc p15, 0, %0, c1, c0\n" : "=r" (ctrl)); __show_regs()
H A Dperf_event_v6.c174 asm volatile("mrc p15, 0, %0, c15, c12, 0" : "=r"(val)); armv6_pmcr_read()
234 asm volatile("mrc p15, 0, %0, c15, c12, 1" : "=r"(value)); armv6pmu_read_counter()
236 asm volatile("mrc p15, 0, %0, c15, c12, 2" : "=r"(value)); armv6pmu_read_counter()
238 asm volatile("mrc p15, 0, %0, c15, c12, 3" : "=r"(value)); armv6pmu_read_counter()
H A Dsleep.S106 mrc p15, 0, r0, c0, c0, 0 @ read id reg
128 ALT_SMP(mrc p15, 0, r0, c0, c0, 5)
H A Dtcm.c127 asm("mrc p15, 0, %0, c9, c1, 0" setup_tcm_bank()
130 asm("mrc p15, 0, %0, c9, c1, 1" setup_tcm_bank()
H A Dentry-header.S48 mrc p15, 0, \rtmp2, c1, c0, 0
H A Dentry-armv.S376 ATRAP( mrc p15, 0, r7, c1, c0, 0)
1007 mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code
H A Dsetup.c290 asm("mrc p15, 1, %0, c0, c0, 0 @ read CCSIDR" cpu_has_aliasing_icache()
/linux-4.1.27/arch/arm/mach-iop13xx/include/mach/
H A Dtime.h74 asm volatile("mrc p6, 0, %0, c0, c9, 0" : "=r" (val)); read_tmr0()
91 asm volatile("mrc p6, 0, %0, c2, c9, 0" : "=r" (val)); read_tcr0()
103 asm volatile("mrc p6, 0, %0, c3, c9, 0" : "=r" (val)); read_tcr1()
H A Dirqs.h12 asm volatile("mrc p6, 0, %0, c0, c3, 0":"=r" (val)); read_intpnd_0()
21 asm volatile("mrc p6, 0, %0, c1, c3, 0":"=r" (val)); read_intpnd_1()
30 asm volatile("mrc p6, 0, %0, c2, c3, 0":"=r" (val)); read_intpnd_2()
39 asm volatile("mrc p6, 0, %0, c3, c3, 0":"=r" (val)); read_intpnd_3()
H A Diop13xx.h23 asm volatile("mrc p6, 0, %0, c0, c0, 0":"=r" (id)); iop13xx_cpu_id()
31 asm volatile("mrc p6, 0, %0, c7, c9, 0":"=r" (val)); read_wdtcr()
43 asm volatile("mrc p6, 0, %0, c8, c9, 0":"=r" (val)); read_wdtsr()
55 asm volatile("mrc p6, 0, %0, c0, c1, 0":"=r" (val)); read_rcsr()
/linux-4.1.27/arch/arm/mach-mvebu/
H A Dpmsu_ll.S17 mrc p15, 4, r1, c15, c0 @ get SCU base address
19 mrc 15, 0, r0, cr0, cr0, 5 @ get the CPU ID
38 mrc p15, 0, r1, c1, c0, 0
H A Dcoherency_ll.S32 mrc p15, 0, r1, c1, c0, 0
69 mrc 15, 0, r3, cr0, cr0, 5
H A Dpmsu.c298 "mrc p15, 0, r0, c1, c0, 0 \n\t" armada_370_xp_pmsu_idle_enter()
/linux-4.1.27/arch/arm/mach-iop13xx/
H A Dmsi.c33 asm volatile("mrc p6, 0, %0, c8, c1, 0":"=r" (val)); read_imipr_0()
46 asm volatile("mrc p6, 0, %0, c9, c1, 0":"=r" (val)); read_imipr_1()
59 asm volatile("mrc p6, 0, %0, c10, c1, 0":"=r" (val)); read_imipr_2()
72 asm volatile("mrc p6, 0, %0, c11, c1, 0":"=r" (val)); read_imipr_3()
H A Dirq.c35 asm volatile("mrc p6, 0, %0, c0, c4, 0":"=r" (val)); read_intctl_0()
48 asm volatile("mrc p6, 0, %0, c1, c4, 0":"=r" (val)); read_intctl_1()
61 asm volatile("mrc p6, 0, %0, c2, c4, 0":"=r" (val)); read_intctl_2()
74 asm volatile("mrc p6, 0, %0, c3, c4, 0":"=r" (val)); read_intctl_3()
/linux-4.1.27/arch/arm/mach-imx/
H A Dhotplug.c30 " mrc p15, 0, %0, c1, c0, 1\n" cpu_enter_lowpower()
33 " mrc p15, 0, %0, c1, c0, 0\n" cpu_enter_lowpower()
H A Dplatsmp.c40 asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base)); imx_scu_map_io()
87 asm("mrc p15, 0, %0, c15, c0, 1" : "=r" (g_diag_reg) : : "cc"); imx_smp_prepare_cpus()
H A Dmm-imx3.c45 "mrc p15, 0, %0, c1, c0, 0\n" imx3_idle()
61 "mrc p15, 0, %0, c1, c0, 0\n" imx3_idle()
/linux-4.1.27/arch/arm/boot/compressed/
H A Dhead-sa1100.S26 mrc p15, 0, r0, c1, c0, 0 @ read control reg
44 mrc p15, 0, r0, c1, c0, 0 @ read control reg
H A Dmisc.c42 asm volatile ("mrc p14, 0, %0, c0, c1, 0" : "=r" (status)); icedcc_putc()
59 asm volatile ("mrc p14, 0, %0, c14, c0, 0" : "=r" (status)); icedcc_putc()
75 asm volatile ("mrc p14, 0, %0, c0, c0, 0" : "=r" (status)); icedcc_putc()
H A Dhead-xscale.S30 mrc p15, 0, r0, c1, c0, 0 @ read control reg
H A Dhead.S93 mrc p15, 0, r0, c1, c0
634 mrc p15, 0, r0, c1, c0, 0 @ read control reg
663 mrc p15, 0, r0, c1, c0, 0 @ read control reg
724 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
744 mrc p15, 0, r0, c1, c0, 0 @ read control reg
757 mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0
766 mrc p15, 0, r0, c1, c0, 0 @ read control reg
786 mrc p15, 0, r0, c1, c0, 0 @ and read it back
799 mrc p15, 0, r0, c1, c0, 0 @ read control reg
817 mrc p15, 0, r0, c1, c0, 0 @ and read it back to
839 mrc p15, 0, r9, c0, c0 @ get processor ID
1046 mrc p15, 0, r0, c1, c0
1056 mrc p15, 0, r0, c1, c0
1065 mrc p15, 0, r0, c1, c0
1075 mrc p15, 0, r0, c1, c0
1146 mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
1155 mrc p15, 1, r0, c0, c0, 1 @ read clidr
1168 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
1208 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
1219 mrc p15, 0, r3, c0, c0, 1 @ read cache type
H A Dhead-sharpsl.S35 mrc p15, 0, r4, c0, c0 @ Get Processor ID
/linux-4.1.27/arch/arm/mach-omap2/
H A Domap-headsmp.S38 mrc p15, 0, r4, c0, c0, 5
54 mrc p15, 0, r4, c0, c0, 5
76 mrc p15, 0, r4, c0, c0, 5
93 mrc p15, 0, r4, c0, c0, 5
H A Dsleep44xx.S88 mrc p15, 0, r0, c1, c0, 0
113 mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR
124 mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR
131 mrc p15, 0, r0, c1, c1, 2 @ Read NSACR data
151 mrc p15, 0, r5, c0, c0, 5 @ Read MPIDR
194 mrc p15, 0, r0, c1, c0, 0
206 mrc p15, 0, r0, c1, c0, 1
258 mrc p15, 0, r0, c0, c0, 5
275 mrc p15, 0, r0, c1, c0, 1
H A Domap-secure.c129 asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); rx51_secure_update_aux_cr()
H A Dsleep34xx.S201 mrc p15, 0, r0, c1, c0, 0
334 mrc p15, 0, r0, c1, c0, 0
430 mrc p15, 0, r0, c1, c0, 1
503 mrc p15, 0, r1, c1, c0, 1
H A Dpm34xx.c172 asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val)); omap34xx_save_context()
177 asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val)); omap34xx_save_context()
H A Dsram34xx.S157 mrc p15, 0, r8, c1, c0, 0 @ read ctrl register
H A Dsram242x.S151 mov r3, #0x0 @ clear for mrc call
H A Dsram243x.S151 mov r3, #0x0 @ clear for mrc call
/linux-4.1.27/arch/arm/mach-prima2/
H A Dheadsmp.S18 mrc p15, 0, r0, c0, c0, 5
/linux-4.1.27/arch/arm/mach-sti/
H A Dheadsmp.S25 mrc p15, 0, r0, c0, c0, 5
/linux-4.1.27/arch/arm/mach-tegra/
H A Dsleep.S53 mrc p15, 0, r2, c1, c0, 0
77 mrc p15, 0, r0, c0, c0, 5
82 mrc p15, 0x1, r0, c9, c0, 2
128 mrc p15, 0, r3, c1, c0, 0
H A Dsleep.h81 mrc p15, 0, \rd, c0, c0, 5
93 mrc p15, 0, \tmp1, c0, c0, 0
101 mrc p15, 0, \tmp1, c1, c0, 1 @ ACTLR
H A Dreset-handler.S130 mrc p15, 0, r0, c1, c0, 0 @ read system control register
133 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
146 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
154 mrc p15, 0, r10, c0, c0, 5 @ MPIDR
H A Dsleep-tegra20.S257 mrc p15, 0, r11, c1, c0, 1 @ save actlr before exiting coherency
290 mrc p15, 0, r10, c1, c0, 0
/linux-4.1.27/arch/arm/mach-ux500/
H A Dheadsmp.S18 mrc p15, 0, r0, c0, c0, 5
/linux-4.1.27/arch/arm/plat-versatile/
H A Dheadsmp.S22 mrc p15, 0, r0, c0, c0, 5
/linux-4.1.27/arch/arm/include/debug/
H A Dexynos.S24 mrc p15, 0, \tmp, c0, c0, 0
H A Dsa1100.S22 mrc p15, 0, \rp, c1, c0
H A Dvexpress.S33 mrc p15, 0, \rp, c0, c0, 0
/linux-4.1.27/arch/arm/mach-exynos/
H A Dheadsmp.S21 mrc p15, 0, r0, c0, c0, 5
H A Dsleep.S45 mrc p15, 0, r0, c0, c0, 0
58 mrc p15, 0, r0, c0, c0, 0
H A Dfirmware.c36 asm ("mrc p15, 0, %0, c15, c0, 0\n" exynos_save_cp15()
37 "mrc p15, 0, %1, c15, c0, 1\n" exynos_save_cp15()
H A Dmcpm-exynos.c45 "mrc p15, 0, r0, c1, c0, 0 @ get SCTLR\n\t" \
50 "mrc p15, 0, r0, c1, c0, 1 @ get ACTLR\n\t" \
H A Dpm.c62 asm ("mrc p15, 0, %0, c15, c0, 0" exynos_cpu_save_register()
68 asm ("mrc p15, 0, %0, c15, c0, 1" exynos_cpu_save_register()
H A Dplatsmp.c43 "mrc p15, 0, %0, c1, c0, 0\n" cpu_leave_lowpower()
46 " mrc p15, 0, %0, c1, c0, 1\n" cpu_leave_lowpower()
/linux-4.1.27/drivers/clk/pxa/
H A Dclk-pxa27x.c156 asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg)); clk_pxa27x_cpll_get_rate()
228 asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg)); clk_pxa27x_core_get_rate()
251 asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg)); clk_pxa27x_core_get_parent()
291 asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg)); clk_pxa27x_system_bus_get_rate()
H A Dclk-pxa3xx.c231 __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg)); clk_pxa3xx_core_get_parent()
249 __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg)); clk_pxa3xx_run_get_rate()
266 __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg)); clk_pxa3xx_cpll_get_rate()
H A Dclk-pxa25x.c148 asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg)); clk_pxa25x_core_get_parent()
180 asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg)); clk_pxa25x_cpll_get_rate()
/linux-4.1.27/arch/arm/mach-rockchip/
H A Dsleep.S30 mrc p15, 0, r1, c0, c0, 5
H A Dpm.c56 asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (l2ctlr)); rk3288_l2_config()
H A Dplatsmp.c312 asm ("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr)); rockchip_smp_prepare_cpus()
/linux-4.1.27/arch/arm/mach-zynq/
H A Dcommon.h44 asm volatile ("mrc p15, 0, r12, c15, c0, 0\n" zynq_core_pm_init()
/linux-4.1.27/arch/arm/plat-iop/
H A Dcp6.c29 "mrc p15, 0, %0, c15, c1, 0\n\t" cp6_trap()
/linux-4.1.27/arch/arm/mach-hisi/
H A Dhotplug.c253 " mrc p15, 0, %0, c1, c0, 1\n" cpu_enter_lowpower()
256 " mrc p15, 0, %0, c1, c0, 0\n" cpu_enter_lowpower()
H A Dplatmcpm.c255 " mrc p15, 0, r0, c0, c0, 5 \n" hip04_mcpm_power_up_setup()
/linux-4.1.27/arch/unicore32/kernel/
H A Ddebug-macro.S48 mrc p0, #0, \rx, c1, c0
/linux-4.1.27/arch/arm/vfp/
H A Dvfpinstr.h76 asm("mrc p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmrx %0, " #_vfp_ \
H A Dvfphw.S265 1: mrc p10, 0, r0, c\dr, c0, 0 @ fmrs r0, s0
268 1: mrc p10, 0, r0, c\dr, c0, 4 @ fmrs r0, s1
/linux-4.1.27/arch/arm/mach-socfpga/
H A Dsocfpga.c54 asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base)); socfpga_scu_map_io()
/linux-4.1.27/arch/arm/include/asm/hardware/
H A Diop3xx.h224 asm volatile("mrc p6, 0, %0, c0, c1, 0" : "=r" (val)); read_tmr0()
241 asm volatile("mrc p6, 0, %0, c2, c1, 0" : "=r" (val)); read_tcr0()
253 asm volatile("mrc p6, 0, %0, c3, c1, 0" : "=r" (val)); read_tcr1()
280 asm volatile("mrc p6, 0, %0, c7, c1, 0":"=r" (val)); read_wdtcr()
H A Dcp14.h28 asm volatile("mrc p14, "#op1", %0, "#crn", "#crm", "#op2 : "=r" (val)); \
/linux-4.1.27/arch/arm64/kernel/
H A Dkuser32.S70 .inst 0xee1d0f70 // mrc p15, 0, r0, c13, c0, 3
/linux-4.1.27/arch/arm/mach-pxa/
H A Dclock-pxa3xx.c43 __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg)); pxa3xx_get_clk_frequency_khz()
H A Dirq.c115 __asm__ __volatile__("mrc p6, 0, %0, c5, c0, 0\n": "=r"(ichp)); ichp_handle_irq()
H A Dpxa27x.c94 asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) ); pxa27x_get_clk_frequency_khz()
136 asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) ); clk_pxa27x_mem_getrate()
H A Dpxa25x.c71 asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (turbo) ); pxa25x_get_clk_frequency_khz()
H A Dpxa3xx.c394 __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value)); __pxa3xx_init_irq()
/linux-4.1.27/arch/arm/mach-highbank/
H A Dhighbank.c48 asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base)); highbank_scu_map_io()
/linux-4.1.27/arch/arm/common/
H A Dmcpm_head.S56 mrc p15, 0, r0, c0, c0, 5 @ MPIDR
H A DbL_switcher.c56 asm volatile ("mrc p15, 0, %0, c0, c0, 5" : "=r" (id)); read_mpidr()
/linux-4.1.27/arch/arm/mach-mv78xx0/
H A Dcommon.c42 __asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (extra)); mv78xx0_core_index()
/linux-4.1.27/arch/arm/mach-omap1/
H A Dsleep.S109 mrc p15, 0, r9, c1, c0, 0
/linux-4.1.27/drivers/iommu/
H A Dmsm_iommu.c39 " mrc " #processor "," #op1 ", %0," #crn "," #crm "," #op2 "\n" \
/linux-4.1.27/drivers/firmware/
H A Dqcom_scm.c242 asm volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (ctr)); qcom_scm_inv_range()
/linux-4.1.27/drivers/net/wireless/iwlwifi/dvm/
H A Dcalib.c460 IWL_DEBUG_CALIB(priv, "ofdm: ac %u mrc %u x1 %u mrc_x1 %u thresh %u\n", iwl_prepare_legacy_sensitivity_tbl()
465 IWL_DEBUG_CALIB(priv, "cck: ac %u mrc %u thresh %u\n", iwl_prepare_legacy_sensitivity_tbl()
/linux-4.1.27/drivers/net/wireless/iwlegacy/
H A D4965-calib.c382 D_CALIB("ofdm: ac %u mrc %u x1 %u mrc_x1 %u thresh %u\n", il4965_prepare_legacy_sensitivity_tbl()
387 D_CALIB("cck: ac %u mrc %u thresh %u\n", data->auto_corr_cck, il4965_prepare_legacy_sensitivity_tbl()
H A D3945.c931 D_INFO("SKU OP mode is mrc\n"); il3945_nic_config()
/linux-4.1.27/drivers/staging/lustre/lustre/include/lustre/
H A Dlustre_idl.h2431 static inline void set_mrc_cr_flags(struct mdt_rec_create *mrc, __u64 flags) set_mrc_cr_flags() argument
2433 mrc->cr_flags_l = (__u32)(flags & 0xFFFFFFFFUll); set_mrc_cr_flags()
2434 mrc->cr_flags_h = (__u32)(flags >> 32); set_mrc_cr_flags()
2437 static inline __u64 get_mrc_cr_flags(struct mdt_rec_create *mrc) get_mrc_cr_flags() argument
2439 return ((__u64)(mrc->cr_flags_l) | ((__u64)mrc->cr_flags_h << 32)); get_mrc_cr_flags()
/linux-4.1.27/arch/arm/probes/kprobes/
H A Dtest-arm.c1252 TEST_COPROCESSOR( "mrc"two" 15, 7, r15, cr15, cr15, 7") \ kprobe_arm_test_cases()
1253 TEST_COPROCESSOR( "mrc"two" 0, 0, r0, cr0, cr0, 0") kprobe_arm_test_cases()
/linux-4.1.27/drivers/bus/
H A Darm-cci.c1255 " mrc p15, 0, r0, c0, c0, 5 @ get MPIDR value \n" cci_enable_port_for_self()
/linux-4.1.27/arch/arm64/kvm/
H A Dsys_regs.c877 * kvm_handle_cp15_32 -- handles a mrc/mcr trap on a guest CP15 access
/linux-4.1.27/drivers/usb/gadget/udc/
H A Dpxa25x_udc.c2086 asm("mrc%? p15, 0, %0, c0, c0" : "=r" (chiprev)); pxa25x_udc_probe()

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