| /linux-4.1.27/drivers/clk/st/ |
| D | clkgen-fsyn.c | 38 unsigned long mdiv; member
45 { .mdiv = 0x1f, .pe = 0x0, .sdiv = 0x7, .nsdiv = 0 }, /* 312.5 Khz */
46 { .mdiv = 0x17, .pe = 0x25ed, .sdiv = 0x1, .nsdiv = 0 }, /* 27 MHz */
47 { .mdiv = 0x1a, .pe = 0x7b36, .sdiv = 0x2, .nsdiv = 1 }, /* 36.87 MHz */
48 { .mdiv = 0x13, .pe = 0x0, .sdiv = 0x2, .nsdiv = 1 }, /* 48 MHz */
49 { .mdiv = 0x11, .pe = 0x1c72, .sdiv = 0x1, .nsdiv = 1 }, /* 108 MHz */
53 { .mdiv = 0x1f, .pe = 0x0, .sdiv = 0x7, .nsdiv = 0 }, /* 625 Khz */
54 { .mdiv = 0x13, .pe = 0x777c, .sdiv = 0x4, .nsdiv = 1 }, /* 25.175 MHz */
55 { .mdiv = 0x19, .pe = 0x4d35, .sdiv = 0x2, .nsdiv = 0 }, /* 25.200 MHz */
56 { .mdiv = 0x11, .pe = 0x1c72, .sdiv = 0x4, .nsdiv = 1 }, /* 27.000 MHz */
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| D | clkgen-pll.c | 46 struct clkgen_field mdiv; member
65 .mdiv = CLKGEN_FIELD(0x0, C65_MDIV_PLL1600_MASK, 0),
73 .mdiv = CLKGEN_FIELD(0x0, C65_MDIV_PLL800_MASK, 0),
277 unsigned long mdiv, ndiv, pdiv; in recalc_stm_pll800c65() local
285 mdiv = CLKGEN_READ(pll, mdiv); in recalc_stm_pll800c65()
288 if (!mdiv) in recalc_stm_pll800c65()
289 mdiv++; /* mdiv=0 or 1 => MDIV=1 */ in recalc_stm_pll800c65()
292 rate = (unsigned long)div64_u64(res, mdiv * (1 << pdiv)); in recalc_stm_pll800c65()
304 unsigned long mdiv, ndiv; in recalc_stm_pll1600c65() local
310 mdiv = CLKGEN_READ(pll, mdiv); in recalc_stm_pll1600c65()
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| /linux-4.1.27/drivers/clk/samsung/ |
| D | clk-pll.c | 77 u32 pll_con, mdiv, pdiv, sdiv; in samsung_pll2126_recalc_rate() local
81 mdiv = (pll_con >> PLL2126_MDIV_SHIFT) & PLL2126_MDIV_MASK; in samsung_pll2126_recalc_rate()
85 fvco *= (mdiv + 8); in samsung_pll2126_recalc_rate()
110 u32 pll_con, mdiv, pdiv, sdiv; in samsung_pll3000_recalc_rate() local
114 mdiv = (pll_con >> PLL3000_MDIV_SHIFT) & PLL3000_MDIV_MASK; in samsung_pll3000_recalc_rate()
118 fvco *= (2 * (mdiv + 8)); in samsung_pll3000_recalc_rate()
147 u32 mdiv, pdiv, sdiv, pll_con; in samsung_pll35xx_recalc_rate() local
151 mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK; in samsung_pll35xx_recalc_rate()
155 fvco *= mdiv; in samsung_pll35xx_recalc_rate()
169 return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv); in samsung_pll35xx_mp_change()
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| D | clk-pll.h | 45 .mdiv = (_m), \
53 .mdiv = (_m), \
62 .mdiv = (_m), \
71 .mdiv = (_m), \
81 .mdiv = (_m), \
95 unsigned int mdiv; member
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| /linux-4.1.27/arch/arm/mach-s3c24xx/include/mach/ |
| D | regs-s3c2443-clock.h | 154 unsigned int mdiv, pdiv, sdiv; in s3c2443_get_mpll() local
157 mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT; in s3c2443_get_mpll()
161 mdiv &= S3C2443_PLLCON_MDIVMASK; in s3c2443_get_mpll()
165 fvco = (uint64_t)baseclk * (2 * (mdiv + 8)); in s3c2443_get_mpll()
174 unsigned int mdiv, pdiv, sdiv; in s3c2443_get_epll() local
177 mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT; in s3c2443_get_epll()
181 mdiv &= S3C2443_PLLCON_MDIVMASK; in s3c2443_get_epll()
185 fvco = (uint64_t)baseclk * (mdiv + 8); in s3c2443_get_epll()
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| /linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| D | gk104.c | 35 u32 mdiv; member
313 info->mdiv |= 0x80000000; in calc_clk()
314 info->mdiv |= div1D; in calc_clk()
320 info->mdiv |= 0x80000000; in calc_clk()
321 info->mdiv |= div1P << 8; in calc_clk()
392 nv_mask(priv, 0x137250 + (clk * 0x04), 0x00003f00, info->mdiv); in gk104_clk_prog_3()
394 nv_mask(priv, 0x137250 + (clk * 0x04), 0x0000003f, info->mdiv); in gk104_clk_prog_3()
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| D | gf100.c | 35 u32 mdiv; member
296 info->mdiv |= 0x80000000; in calc_clk()
297 info->mdiv |= div1D; in calc_clk()
303 info->mdiv |= 0x80000000; in calc_clk()
304 info->mdiv |= div1P << 8; in calc_clk()
380 nv_mask(priv, 0x137250 + (clk * 0x04), 0x00003f3f, info->mdiv); in gf100_clk_prog_4()
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| D | base.c | 273 lo /= clock->mdiv; in nvkm_pstate_info()
274 hi /= clock->mdiv; in nvkm_pstate_info()
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| /linux-4.1.27/drivers/gpu/drm/sti/ |
| D | sti_hdmi_tx3g0c55phy.c | 139 u32 mdiv, ndiv, pdiv, val; in enable_pll_rejection() local
168 mdiv = 30; in enable_pll_rejection()
172 mdiv = 30; in enable_pll_rejection()
184 (mdiv << REJECTION_PLL_HDMI_MDIV_SHIFT) | in enable_pll_rejection()
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| /linux-4.1.27/arch/mips/netlogic/xlp/ |
| D | nlm_hal.c | 309 u32 mdiv, fdiv, pll_out_freq_den, reg_select, ref_div, pic_div; in nlm_xlp2_get_pic_frequency() local
405 mdiv = ctrl_val2 & 0xff; in nlm_xlp2_get_pic_frequency()
429 pll_out_freq_num = ((ref_clk >> 1) * (6 + mdiv)) + fdiv; in nlm_xlp2_get_pic_frequency()
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| /linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/device/ |
| D | ctrl.c | 125 args->v0.min = lo / domain->mdiv; in nvkm_control_mthd_pstate_attr()
126 args->v0.max = hi / domain->mdiv; in nvkm_control_mthd_pstate_attr()
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| /linux-4.1.27/drivers/iio/frequency/ |
| D | adf4350.c | 136 u16 mdiv, r_cnt = 0; in adf4350_set_freq() local
144 mdiv = 75; in adf4350_set_freq()
147 mdiv = 23; in adf4350_set_freq()
183 } while (mdiv > st->r0_int); in adf4350_set_freq()
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| /linux-4.1.27/drivers/i2c/busses/ |
| D | i2c-octeon.c | 450 int thp = 0x18, mdiv = 2, ndiv = 0, delta_hz = 1000000; in octeon_i2c_setclock() local
478 mdiv = mdiv_idx; in octeon_i2c_setclock()
485 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CLKCTL, (mdiv << 3) | ndiv); in octeon_i2c_setclock()
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| /linux-4.1.27/drivers/gpu/drm/nouveau/include/nvkm/subdev/ |
| D | clk.h | 70 int mdiv; member
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| /linux-4.1.27/drivers/media/dvb-frontends/ |
| D | stb0899_drv.c | 583 u8 mdiv = 0; in stb0899_set_mclk() local
586 mdiv = ((6 * Mclk) / state->config->xtal_freq) - 1; in stb0899_set_mclk()
587 dprintk(state->verbose, FE_DEBUG, 1, "mdiv=%d", mdiv); in stb0899_set_mclk()
589 stb0899_write_reg(state, STB0899_NCOARSE, mdiv); in stb0899_set_mclk()
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| /linux-4.1.27/drivers/video/fbdev/savage/ |
| D | savagefb_driver.c | 421 long freq_max, unsigned int *mdiv, in SavageCalcClock() argument
463 *mdiv = best_m - 2; in SavageCalcClock()
468 long freq_max, unsigned char *mdiv, in common_calc_clock() argument
504 *mdiv = best_m - 2; in common_calc_clock()
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| /linux-4.1.27/drivers/gpu/drm/i915/ |
| D | intel_display.c | 6222 u32 mdiv; in vlv_prepare_pll() local
6252 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); in vlv_prepare_pll()
6253 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); in vlv_prepare_pll()
6254 mdiv |= ((bestn << DPIO_N_SHIFT)); in vlv_prepare_pll()
6255 mdiv |= (1 << DPIO_K_SHIFT); in vlv_prepare_pll()
6262 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); in vlv_prepare_pll()
6263 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); in vlv_prepare_pll()
6265 mdiv |= DPIO_ENABLE_CALIBRATION; in vlv_prepare_pll()
6266 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); in vlv_prepare_pll()
6916 u32 mdiv; in vlv_crtc_clock_get() local
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