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Searched refs:intel_crtc (Results 1 – 27 of 27) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/i915/
Dintel_display.c80 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
82 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
92 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
93 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
94 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
100 static void vlv_prepare_pll(struct intel_crtc *crtc,
102 static void chv_prepare_pll(struct intel_crtc *crtc,
416 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) in intel_pipe_has_type()
627 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); in i9xx_find_best_dpll()
690 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); in pnv_find_best_dpll()
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Dintel_sprite.c80 bool intel_pipe_update_start(struct intel_crtc *crtc, uint32_t *start_vbl_count) in intel_pipe_update_start()
153 void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count) in intel_pipe_update_end()
168 static void intel_update_primary_plane(struct intel_crtc *crtc) in intel_update_primary_plane()
363 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in vlv_update_plane() local
451 intel_update_primary_plane(intel_crtc); in vlv_update_plane()
480 intel_flush_primary_plane(dev_priv, intel_crtc->plane); in vlv_update_plane()
489 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in vlv_disable_plane() local
493 intel_update_primary_plane(intel_crtc); in vlv_disable_plane()
500 intel_flush_primary_plane(dev_priv, intel_crtc->plane); in vlv_disable_plane()
517 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in ivb_update_plane() local
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Dintel_fbdev.c293 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_fb_gamma_set() local
295 intel_crtc->lut_r[regno] = red >> 8; in intel_crtc_fb_gamma_set()
296 intel_crtc->lut_g[regno] = green >> 8; in intel_crtc_fb_gamma_set()
297 intel_crtc->lut_b[regno] = blue >> 8; in intel_crtc_fb_gamma_set()
303 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_fb_gamma_get() local
305 *red = intel_crtc->lut_r[regno] << 8; in intel_crtc_fb_gamma_get()
306 *green = intel_crtc->lut_g[regno] << 8; in intel_crtc_fb_gamma_get()
307 *blue = intel_crtc->lut_b[regno] << 8; in intel_crtc_fb_gamma_get()
558 struct intel_crtc *intel_crtc; in intel_fbdev_init_bios() local
567 intel_crtc = to_intel_crtc(crtc); in intel_fbdev_init_bios()
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Dintel_hdmi.c190 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); in ibx_write_infoframe() local
191 int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); in ibx_write_infoframe()
205 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); in ibx_write_infoframe()
210 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); in ibx_write_infoframe()
225 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); in ibx_infoframe_enabled() local
226 int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); in ibx_infoframe_enabled()
239 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); in cpt_write_infoframe() local
240 int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); in cpt_write_infoframe()
257 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); in cpt_write_infoframe()
262 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); in cpt_write_infoframe()
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Dintel_fbc.c74 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in i8xx_fbc_enable() local
101 fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane); in i8xx_fbc_enable()
117 cfb_pitch, crtc->y, plane_name(intel_crtc->plane)); in i8xx_fbc_enable()
133 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in g4x_fbc_enable() local
138 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN; in g4x_fbc_enable()
150 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane)); in g4x_fbc_enable()
189 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in ilk_fbc_enable() local
194 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane); in ilk_fbc_enable()
227 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane)); in ilk_fbc_enable()
260 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in gen7_fbc_enable() local
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Dintel_atomic_plane.c113 struct intel_crtc *intel_crtc; in intel_plane_atomic_check() local
118 intel_crtc = to_intel_crtc(crtc); in intel_plane_atomic_check()
147 intel_crtc->active ? intel_crtc->config->pipe_src_w : 0; in intel_plane_atomic_check()
149 intel_crtc->active ? intel_crtc->config->pipe_src_h : 0; in intel_plane_atomic_check()
161 intel_crtc->atomic.disabled_planes |= in intel_plane_atomic_check()
Dintel_ddi.c346 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in hsw_fdi_link_train() local
363 FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); in hsw_fdi_link_train()
373 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel); in hsw_fdi_link_train()
374 WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL); in hsw_fdi_link_train()
392 ((intel_crtc->config->fdi_lanes - 1) << 1) | in hsw_fdi_link_train()
477 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_ddi_get_crtc_encoder() local
488 pipe_name(intel_crtc->pipe)); in intel_ddi_get_crtc_encoder()
497 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); in intel_ddi_get_crtc_new_encoder()
958 hsw_ddi_pll_select(struct intel_crtc *intel_crtc, in hsw_ddi_pll_select() argument
976 pll = intel_get_shared_dpll(intel_crtc, crtc_state); in hsw_ddi_pll_select()
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Dintel_fifo_underrun.c54 struct intel_crtc *crtc; in ivb_can_enable_err_int()
73 struct intel_crtc *crtc; in cpt_can_enable_serr_int()
97 struct intel_crtc *crtc; in i9xx_check_fifo_underruns()
235 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in __intel_set_cpu_fifo_underrun_reporting() local
240 old = !intel_crtc->cpu_fifo_underrun_disabled; in __intel_set_cpu_fifo_underrun_reporting()
241 intel_crtc->cpu_fifo_underrun_disabled = !enable; in __intel_set_cpu_fifo_underrun_reporting()
304 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_set_pch_fifo_underrun_reporting() local
319 old = !intel_crtc->pch_fifo_underrun_disabled; in intel_set_pch_fifo_underrun_reporting()
320 intel_crtc->pch_fifo_underrun_disabled = !enable; in intel_set_pch_fifo_underrun_reporting()
Dintel_audio.c181 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); in hsw_audio_codec_disable() local
182 enum pipe pipe = intel_crtc->pipe; in hsw_audio_codec_disable()
193 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) in hsw_audio_codec_disable()
209 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); in hsw_audio_codec_enable() local
210 enum pipe pipe = intel_crtc->pipe; in hsw_audio_codec_enable()
251 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) in hsw_audio_codec_enable()
261 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); in ilk_audio_codec_disable() local
265 enum pipe pipe = intel_crtc->pipe; in ilk_audio_codec_disable()
290 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) in ilk_audio_codec_disable()
312 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); in ilk_audio_codec_enable() local
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Dintel_atomic.c78 struct intel_crtc *crtc = to_intel_crtc(state->crtcs[i]); in intel_atomic_check()
216 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_duplicate_state() local
219 if (WARN_ON(!intel_crtc->config)) in intel_crtc_duplicate_state()
222 crtc_state = kmemdup(intel_crtc->config, in intel_crtc_duplicate_state()
223 sizeof(*intel_crtc->config), GFP_KERNEL); in intel_crtc_duplicate_state()
Dintel_drv.h137 struct intel_crtc *new_crtc;
440 struct intel_crtc { struct
563 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
805 static inline unsigned int intel_num_planes(struct intel_crtc *crtc) in intel_num_planes()
842 int intel_get_crtc_scanline(struct intel_crtc *crtc);
861 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
862 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
863 bool intel_ddi_pll_select(struct intel_crtc *crtc,
948 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
1005 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
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Dintel_pm.c844 static void vlv_write_wm_values(struct intel_crtc *crtc, in vlv_write_wm_values()
914 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in vlv_compute_drain_latency() local
916 int clock = intel_crtc->config->base.adjusted_mode.crtc_clock; in vlv_compute_drain_latency()
923 if (!intel_crtc->active || !plane->state->fb) in vlv_compute_drain_latency()
951 static int vlv_compute_wm(struct intel_crtc *crtc, in vlv_compute_wm()
1029 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in valleyview_update_wm() local
1030 enum pipe pipe = intel_crtc->pipe; in valleyview_update_wm()
1035 wm.pipe[pipe].primary = vlv_compute_wm(intel_crtc, in valleyview_update_wm()
1040 wm.pipe[pipe].cursor = vlv_compute_wm(intel_crtc, in valleyview_update_wm()
1068 vlv_write_wm_values(intel_crtc, &wm); in valleyview_update_wm()
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Dintel_psr.c81 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); in intel_psr_write_vsc()
266 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_psr_match_conditions() local
285 I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config->cpu_transcoder)) & in intel_psr_match_conditions()
292 intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { in intel_psr_match_conditions()
401 struct intel_crtc *intel_crtc = in vlv_psr_disable() local
407 if (wait_for((I915_READ(VLV_PSRSTAT(intel_crtc->pipe)) & in vlv_psr_disable()
411 val = I915_READ(VLV_PSRCTL(intel_crtc->pipe)); in vlv_psr_disable()
415 I915_WRITE(VLV_PSRCTL(intel_crtc->pipe), val); in vlv_psr_disable()
419 WARN_ON(vlv_is_psr_active_on_pipe(dev, intel_crtc->pipe)); in vlv_psr_disable()
Dintel_dsi.c293 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); in intel_dsi_port_enable() local
314 temp |= intel_crtc->pipe ? in intel_dsi_port_enable()
411 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); in intel_dsi_pre_enable() local
412 enum pipe pipe = intel_crtc->pipe; in intel_dsi_pre_enable()
425 intel_crtc->config->dpll_hw_state.dpll = DPLL_INTEGRATED_CLOCK_VLV | in intel_dsi_pre_enable()
694 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); in set_dsi_timings() local
697 unsigned int bpp = intel_crtc->config->pipe_bpp; in set_dsi_timings()
749 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); in intel_dsi_prepare() local
752 &intel_crtc->config->base.adjusted_mode; in intel_dsi_prepare()
754 unsigned int bpp = intel_crtc->config->pipe_bpp; in intel_dsi_prepare()
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Dintel_dp.c1335 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); in intel_dp_compute_config() local
1366 intel_gmch_panel_fitting(intel_crtc, pipe_config, in intel_dp_compute_config()
1369 intel_pch_panel_fitting(intel_crtc, pipe_config, in intel_dp_compute_config()
1488 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); in ironlake_set_pll_cpu_edp()
1522 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); in intel_dp_prepare()
2219 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); in intel_dp_get_config()
2299 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); in intel_disable_dp()
2342 struct intel_crtc *intel_crtc = in chv_post_disable_dp() local
2345 enum pipe pipe = intel_crtc->pipe; in chv_post_disable_dp()
2484 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); in intel_enable_dp()
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Dintel_dp_mst.c156 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_mst_pre_enable_dp() local
177 intel_crtc->config->ddi_pll_sel); in intel_mst_pre_enable_dp()
191 intel_crtc->config->pbn, &slots); in intel_mst_pre_enable_dp()
241 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); in intel_dp_mst_enc_get_config()
Dintel_lvds.c141 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); in intel_pre_enable_lvds()
289 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); in intel_lvds_compute_config() local
293 if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) { in intel_lvds_compute_config()
321 intel_pch_panel_fitting(intel_crtc, pipe_config, in intel_lvds_compute_config()
324 intel_gmch_panel_fitting(intel_crtc, pipe_config, in intel_lvds_compute_config()
Dintel_tv.c1025 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); in intel_tv_pre_enable() local
1069 if (intel_crtc->pipe == 1) in intel_tv_pre_enable()
1120 assert_pipe_disabled(dev_priv, intel_crtc->pipe); in intel_tv_pre_enable()
1183 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_tv_detect_type() local
1205 if (intel_crtc->pipe == 1) in intel_tv_detect_type()
Di915_debugfs.c542 struct intel_crtc *crtc; in i915_gem_pageflip_info()
2514 struct intel_crtc *intel_crtc, in intel_encoder_info() argument
2519 struct drm_crtc *crtc = &intel_crtc->base; in intel_encoder_info()
2542 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc) in intel_crtc_info() argument
2546 struct drm_crtc *crtc = &intel_crtc->base; in intel_crtc_info()
2556 intel_encoder_info(m, intel_crtc, intel_encoder); in intel_crtc_info()
2667 struct intel_crtc *crtc; in i915_display_info()
2883 struct drm_device *dev, struct intel_crtc *intel_crtc) in drrs_status_per_crtc() argument
2890 for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) { in drrs_status_per_crtc()
2923 if (intel_crtc->config->has_drrs) { in drrs_status_per_crtc()
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Dintel_panel.c101 intel_pch_panel_fitting(struct intel_crtc *intel_crtc, in intel_pch_panel_fitting() argument
304 void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc, in intel_gmch_panel_fitting() argument
308 struct drm_device *dev = intel_crtc->base.dev; in intel_gmch_panel_fitting()
362 pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) | in intel_gmch_panel_fitting()
Dintel_dvo.c185 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); in intel_enable_dvo()
298 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); in intel_dvo_pre_enable()
Dintel_sdvo.c998 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_sdvo_set_avi_infoframe() local
1011 if (intel_crtc->config->limited_color_range) in intel_sdvo_set_avi_infoframe()
1183 struct intel_crtc *crtc = to_intel_crtc(intel_encoder->base.crtc); in intel_sdvo_pre_enable()
1474 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); in intel_enable_sdvo() local
1485 temp |= SDVO_PIPE_SEL(intel_crtc->pipe); in intel_enable_sdvo()
1490 intel_wait_for_vblank(dev, intel_crtc->pipe); in intel_enable_sdvo()
Di915_trace.h20 TP_PROTO(struct intel_crtc *crtc, u32 min, u32 max),
46 TP_PROTO(struct intel_crtc *crtc, u32 min, u32 max, u32 frame),
71 TP_PROTO(struct intel_crtc *crtc, u32 frame),
Di915_drv.h241 #define for_each_intel_crtc(dev, intel_crtc) \ argument
242 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
525 struct intel_crtc;
561 bool (*get_pipe_config)(struct intel_crtc *,
563 void (*get_initial_plane_config)(struct intel_crtc *,
565 int (*crtc_compute_clock)(struct intel_crtc *crtc,
815 struct intel_crtc *crtc;
Di915_irq.c559 struct intel_crtc *intel_crtc = in i915_get_vblank_counter() local
562 &intel_crtc->config->base.adjusted_mode; in i915_get_vblank_counter()
613 static int __intel_get_crtc_scanline(struct intel_crtc *crtc) in __intel_get_crtc_scanline()
643 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in i915_get_crtc_scanoutpos() local
644 const struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode; in i915_get_crtc_scanoutpos()
651 if (!intel_crtc->active) { in i915_get_crtc_scanoutpos()
688 position = __intel_get_crtc_scanline(intel_crtc); in i915_get_crtc_scanoutpos()
761 int intel_get_crtc_scanline(struct intel_crtc *crtc) in intel_get_crtc_scanline()
Dintel_overlay.c172 struct intel_crtc *crtc;
854 struct intel_crtc *crtc) in check_overlay_possible_on_crtc()
1064 struct intel_crtc *crtc; in intel_overlay_put_image()
Dintel_crt.c160 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); in intel_crt_set_dpms()