Lines Matching refs:intel_crtc
80 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
82 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
92 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
93 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
94 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
100 static void vlv_prepare_pll(struct intel_crtc *crtc,
102 static void chv_prepare_pll(struct intel_crtc *crtc,
416 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) in intel_pipe_has_type()
627 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); in i9xx_find_best_dpll()
690 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); in pnv_find_best_dpll()
751 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); in g4x_find_best_dpll()
850 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); in vlv_find_best_dpll()
904 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); in chv_find_best_dpll()
958 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_active() local
973 return intel_crtc->active && crtc->primary->state->fb && in intel_crtc_active()
974 intel_crtc->config->base.adjusted_mode.crtc_clock; in intel_crtc_active()
981 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_pipe_to_cpu_transcoder() local
983 return intel_crtc->config->cpu_transcoder; in intel_pipe_to_cpu_transcoder()
1021 static void intel_wait_for_pipe_off(struct intel_crtc *crtc) in intel_wait_for_pipe_off()
1127 intel_crtc_to_shared_dpll(struct intel_crtc *crtc) in intel_crtc_to_shared_dpll()
1583 static void vlv_enable_pll(struct intel_crtc *crtc, in vlv_enable_pll()
1622 static void chv_enable_pll(struct intel_crtc *crtc, in chv_enable_pll()
1663 struct intel_crtc *crtc; in intel_num_dvo_pipes()
1673 static void i9xx_enable_pll(struct intel_crtc *crtc) in i9xx_enable_pll()
1741 static void i9xx_disable_pll(struct intel_crtc *crtc) in i9xx_disable_pll()
1851 static void intel_prepare_shared_dpll(struct intel_crtc *crtc) in intel_prepare_shared_dpll()
1878 static void intel_enable_shared_dpll(struct intel_crtc *crtc) in intel_enable_shared_dpll()
1908 static void intel_disable_shared_dpll(struct intel_crtc *crtc) in intel_disable_shared_dpll()
1948 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in ironlake_enable_pch_transcoder() local
1956 intel_crtc_to_shared_dpll(intel_crtc)); in ironlake_enable_pch_transcoder()
1987 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) in ironlake_enable_pch_transcoder()
2084 static void intel_enable_pipe(struct intel_crtc *crtc) in intel_enable_pipe()
2146 static void intel_disable_pipe(struct intel_crtc *crtc) in intel_disable_pipe()
2210 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_enable_primary_hw_plane() local
2213 assert_pipe_enabled(dev_priv, intel_crtc->pipe); in intel_enable_primary_hw_plane()
2215 if (intel_crtc->primary_enabled) in intel_enable_primary_hw_plane()
2218 intel_crtc->primary_enabled = true; in intel_enable_primary_hw_plane()
2229 intel_wait_for_vblank(dev, intel_crtc->pipe); in intel_enable_primary_hw_plane()
2244 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_disable_primary_hw_plane() local
2246 if (WARN_ON(!intel_crtc->active)) in intel_disable_primary_hw_plane()
2249 if (!intel_crtc->primary_enabled) in intel_disable_primary_hw_plane()
2252 intel_crtc->primary_enabled = false; in intel_disable_primary_hw_plane()
2540 intel_alloc_initial_plane_obj(struct intel_crtc *crtc, in intel_alloc_initial_plane_obj()
2606 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, in intel_find_initial_plane_obj() argument
2609 struct drm_device *dev = intel_crtc->base.dev; in intel_find_initial_plane_obj()
2612 struct intel_crtc *i; in intel_find_initial_plane_obj()
2614 struct drm_plane *primary = intel_crtc->base.primary; in intel_find_initial_plane_obj()
2620 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { in intel_find_initial_plane_obj()
2634 if (c == &intel_crtc->base) in intel_find_initial_plane_obj()
2659 primary->state->crtc = &intel_crtc->base; in intel_find_initial_plane_obj()
2660 primary->crtc = &intel_crtc->base; in intel_find_initial_plane_obj()
2662 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe); in intel_find_initial_plane_obj()
2671 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in i9xx_update_primary_plane() local
2673 int plane = intel_crtc->plane; in i9xx_update_primary_plane()
2679 if (!intel_crtc->primary_enabled) { in i9xx_update_primary_plane()
2700 if (intel_crtc->pipe == PIPE_B) in i9xx_update_primary_plane()
2707 ((intel_crtc->config->pipe_src_h - 1) << 16) | in i9xx_update_primary_plane()
2708 (intel_crtc->config->pipe_src_w - 1)); in i9xx_update_primary_plane()
2712 ((intel_crtc->config->pipe_src_h - 1) << 16) | in i9xx_update_primary_plane()
2713 (intel_crtc->config->pipe_src_w - 1)); in i9xx_update_primary_plane()
2759 intel_crtc->dspaddr_offset = in i9xx_update_primary_plane()
2763 linear_offset -= intel_crtc->dspaddr_offset; in i9xx_update_primary_plane()
2765 intel_crtc->dspaddr_offset = linear_offset; in i9xx_update_primary_plane()
2771 x += (intel_crtc->config->pipe_src_w - 1); in i9xx_update_primary_plane()
2772 y += (intel_crtc->config->pipe_src_h - 1); in i9xx_update_primary_plane()
2777 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + in i9xx_update_primary_plane()
2778 (intel_crtc->config->pipe_src_w - 1) * pixel_size; in i9xx_update_primary_plane()
2786 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); in i9xx_update_primary_plane()
2800 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in ironlake_update_primary_plane() local
2802 int plane = intel_crtc->plane; in ironlake_update_primary_plane()
2808 if (!intel_crtc->primary_enabled) { in ironlake_update_primary_plane()
2862 intel_crtc->dspaddr_offset = in ironlake_update_primary_plane()
2866 linear_offset -= intel_crtc->dspaddr_offset; in ironlake_update_primary_plane()
2871 x += (intel_crtc->config->pipe_src_w - 1); in ironlake_update_primary_plane()
2872 y += (intel_crtc->config->pipe_src_h - 1); in ironlake_update_primary_plane()
2877 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + in ironlake_update_primary_plane()
2878 (intel_crtc->config->pipe_src_w - 1) * pixel_size; in ironlake_update_primary_plane()
2886 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); in ironlake_update_primary_plane()
2947 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in skylake_update_primary_plane() local
2949 int pipe = intel_crtc->pipe; in skylake_update_primary_plane()
2953 if (!intel_crtc->primary_enabled) { in skylake_update_primary_plane()
3024 (intel_crtc->config->pipe_src_h - 1) << 16 | in skylake_update_primary_plane()
3025 (intel_crtc->config->pipe_src_w - 1)); in skylake_update_primary_plane()
3053 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_complete_page_flips() local
3054 enum plane plane = intel_crtc->plane; in intel_complete_page_flips()
3067 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_update_primary_planes() local
3075 if (intel_crtc->active && crtc->primary->fb) in intel_update_primary_planes()
3087 struct intel_crtc *crtc; in intel_prepare_reset()
3184 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_has_pending_flip() local
3188 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) in intel_crtc_has_pending_flip()
3198 static void intel_update_pipe_size(struct intel_crtc *crtc) in intel_update_pipe_size()
3241 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_fdi_normal_train() local
3242 int pipe = intel_crtc->pipe; in intel_fdi_normal_train()
3283 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in ironlake_fdi_link_train() local
3284 int pipe = intel_crtc->pipe; in ironlake_fdi_link_train()
3304 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); in ironlake_fdi_link_train()
3383 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in gen6_fdi_link_train() local
3384 int pipe = intel_crtc->pipe; in gen6_fdi_link_train()
3402 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); in gen6_fdi_link_train()
3515 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in ivb_manual_fdi_link_train() local
3516 int pipe = intel_crtc->pipe; in ivb_manual_fdi_link_train()
3553 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); in ivb_manual_fdi_link_train()
3629 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) in ironlake_fdi_pll_enable() argument
3631 struct drm_device *dev = intel_crtc->base.dev; in ironlake_fdi_pll_enable()
3633 int pipe = intel_crtc->pipe; in ironlake_fdi_pll_enable()
3641 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); in ironlake_fdi_pll_enable()
3666 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) in ironlake_fdi_pll_disable() argument
3668 struct drm_device *dev = intel_crtc->base.dev; in ironlake_fdi_pll_disable()
3670 int pipe = intel_crtc->pipe; in ironlake_fdi_pll_disable()
3699 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in ironlake_fdi_disable() local
3700 int pipe = intel_crtc->pipe; in ironlake_fdi_disable()
3749 struct intel_crtc *crtc; in intel_has_pending_fb_unpin()
3771 static void page_flip_completed(struct intel_crtc *intel_crtc) in page_flip_completed() argument
3773 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); in page_flip_completed()
3774 struct intel_unpin_work *work = intel_crtc->unpin_work; in page_flip_completed()
3778 intel_crtc->unpin_work = NULL; in page_flip_completed()
3781 drm_send_vblank_event(intel_crtc->base.dev, in page_flip_completed()
3782 intel_crtc->pipe, in page_flip_completed()
3785 drm_crtc_vblank_put(&intel_crtc->base); in page_flip_completed()
3790 trace_i915_flip_complete(intel_crtc->plane, in page_flip_completed()
3803 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_wait_for_pending_flips() local
3806 if (intel_crtc->unpin_work) { in intel_crtc_wait_for_pending_flips()
3808 page_flip_completed(intel_crtc); in intel_crtc_wait_for_pending_flips()
3909 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, in ironlake_pch_transcoder_set_timings()
3954 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) in ivybridge_update_fdi_bc_bifurcation() argument
3956 struct drm_device *dev = intel_crtc->base.dev; in ivybridge_update_fdi_bc_bifurcation()
3958 switch (intel_crtc->pipe) { in ivybridge_update_fdi_bc_bifurcation()
3962 if (intel_crtc->config->fdi_lanes > 2) in ivybridge_update_fdi_bc_bifurcation()
3989 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in ironlake_pch_enable() local
3990 int pipe = intel_crtc->pipe; in ironlake_pch_enable()
3996 ivybridge_update_fdi_bc_bifurcation(intel_crtc); in ironlake_pch_enable()
4014 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B) in ironlake_pch_enable()
4028 intel_enable_shared_dpll(intel_crtc); in ironlake_pch_enable()
4032 ironlake_pch_transcoder_set_timings(intel_crtc, pipe); in ironlake_pch_enable()
4037 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { in ironlake_pch_enable()
4077 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in lpt_pch_enable() local
4078 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; in lpt_pch_enable()
4085 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); in lpt_pch_enable()
4090 void intel_put_shared_dpll(struct intel_crtc *crtc) in intel_put_shared_dpll()
4111 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, in intel_get_shared_dpll()
4256 static void skylake_pfit_enable(struct intel_crtc *crtc) in skylake_pfit_enable()
4269 static void ironlake_pfit_enable(struct intel_crtc *crtc) in ironlake_pfit_enable()
4336 void hsw_enable_ips(struct intel_crtc *crtc) in hsw_enable_ips()
4369 void hsw_disable_ips(struct intel_crtc *crtc) in hsw_disable_ips()
4399 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_load_lut() local
4400 enum pipe pipe = intel_crtc->pipe; in intel_crtc_load_lut()
4406 if (!crtc->state->enable || !intel_crtc->active) in intel_crtc_load_lut()
4410 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) in intel_crtc_load_lut()
4423 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled && in intel_crtc_load_lut()
4426 hsw_disable_ips(intel_crtc); in intel_crtc_load_lut()
4432 (intel_crtc->lut_r[i] << 16) | in intel_crtc_load_lut()
4433 (intel_crtc->lut_g[i] << 8) | in intel_crtc_load_lut()
4434 intel_crtc->lut_b[i]); in intel_crtc_load_lut()
4438 hsw_enable_ips(intel_crtc); in intel_crtc_load_lut()
4441 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) in intel_crtc_dpms_overlay() argument
4443 if (!enable && intel_crtc->overlay) { in intel_crtc_dpms_overlay()
4444 struct drm_device *dev = intel_crtc->base.dev; in intel_crtc_dpms_overlay()
4449 (void) intel_overlay_switch_off(intel_crtc->overlay); in intel_crtc_dpms_overlay()
4462 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_enable_planes() local
4463 int pipe = intel_crtc->pipe; in intel_crtc_enable_planes()
4468 intel_crtc_dpms_overlay(intel_crtc, true); in intel_crtc_enable_planes()
4470 hsw_enable_ips(intel_crtc); in intel_crtc_enable_planes()
4488 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_disable_planes() local
4489 int pipe = intel_crtc->pipe; in intel_crtc_disable_planes()
4493 if (dev_priv->fbc.crtc == intel_crtc) in intel_crtc_disable_planes()
4496 hsw_disable_ips(intel_crtc); in intel_crtc_disable_planes()
4498 intel_crtc_dpms_overlay(intel_crtc, false); in intel_crtc_disable_planes()
4515 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in ironlake_crtc_enable() local
4517 int pipe = intel_crtc->pipe; in ironlake_crtc_enable()
4521 if (intel_crtc->active) in ironlake_crtc_enable()
4524 if (intel_crtc->config->has_pch_encoder) in ironlake_crtc_enable()
4525 intel_prepare_shared_dpll(intel_crtc); in ironlake_crtc_enable()
4527 if (intel_crtc->config->has_dp_encoder) in ironlake_crtc_enable()
4528 intel_dp_set_m_n(intel_crtc, M1_N1); in ironlake_crtc_enable()
4530 intel_set_pipe_timings(intel_crtc); in ironlake_crtc_enable()
4532 if (intel_crtc->config->has_pch_encoder) { in ironlake_crtc_enable()
4533 intel_cpu_transcoder_set_m_n(intel_crtc, in ironlake_crtc_enable()
4534 &intel_crtc->config->fdi_m_n, NULL); in ironlake_crtc_enable()
4539 intel_crtc->active = true; in ironlake_crtc_enable()
4548 if (intel_crtc->config->has_pch_encoder) { in ironlake_crtc_enable()
4552 ironlake_fdi_pll_enable(intel_crtc); in ironlake_crtc_enable()
4558 ironlake_pfit_enable(intel_crtc); in ironlake_crtc_enable()
4567 intel_enable_pipe(intel_crtc); in ironlake_crtc_enable()
4569 if (intel_crtc->config->has_pch_encoder) in ironlake_crtc_enable()
4579 cpt_verify_modeset(dev, intel_crtc->pipe); in ironlake_crtc_enable()
4585 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) in hsw_crtc_supports_ips()
4596 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc) in haswell_mode_set_planes_workaround()
4599 struct intel_crtc *crtc_it, *other_active_crtc = NULL; in haswell_mode_set_planes_workaround()
4623 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in haswell_crtc_enable() local
4625 int pipe = intel_crtc->pipe; in haswell_crtc_enable()
4629 if (intel_crtc->active) in haswell_crtc_enable()
4632 if (intel_crtc_to_shared_dpll(intel_crtc)) in haswell_crtc_enable()
4633 intel_enable_shared_dpll(intel_crtc); in haswell_crtc_enable()
4635 if (intel_crtc->config->has_dp_encoder) in haswell_crtc_enable()
4636 intel_dp_set_m_n(intel_crtc, M1_N1); in haswell_crtc_enable()
4638 intel_set_pipe_timings(intel_crtc); in haswell_crtc_enable()
4640 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) { in haswell_crtc_enable()
4641 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder), in haswell_crtc_enable()
4642 intel_crtc->config->pixel_multiplier - 1); in haswell_crtc_enable()
4645 if (intel_crtc->config->has_pch_encoder) { in haswell_crtc_enable()
4646 intel_cpu_transcoder_set_m_n(intel_crtc, in haswell_crtc_enable()
4647 &intel_crtc->config->fdi_m_n, NULL); in haswell_crtc_enable()
4654 intel_crtc->active = true; in haswell_crtc_enable()
4661 if (intel_crtc->config->has_pch_encoder) { in haswell_crtc_enable()
4667 intel_ddi_enable_pipe_clock(intel_crtc); in haswell_crtc_enable()
4670 skylake_pfit_enable(intel_crtc); in haswell_crtc_enable()
4672 ironlake_pfit_enable(intel_crtc); in haswell_crtc_enable()
4684 intel_enable_pipe(intel_crtc); in haswell_crtc_enable()
4686 if (intel_crtc->config->has_pch_encoder) in haswell_crtc_enable()
4689 if (intel_crtc->config->dp_encoder_is_mst) in haswell_crtc_enable()
4702 haswell_mode_set_planes_workaround(intel_crtc); in haswell_crtc_enable()
4706 static void skylake_pfit_disable(struct intel_crtc *crtc) in skylake_pfit_disable()
4721 static void ironlake_pfit_disable(struct intel_crtc *crtc) in ironlake_pfit_disable()
4740 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in ironlake_crtc_disable() local
4742 int pipe = intel_crtc->pipe; in ironlake_crtc_disable()
4745 if (!intel_crtc->active) in ironlake_crtc_disable()
4756 if (intel_crtc->config->has_pch_encoder) in ironlake_crtc_disable()
4759 intel_disable_pipe(intel_crtc); in ironlake_crtc_disable()
4761 ironlake_pfit_disable(intel_crtc); in ironlake_crtc_disable()
4767 if (intel_crtc->config->has_pch_encoder) { in ironlake_crtc_disable()
4788 intel_disable_shared_dpll(intel_crtc); in ironlake_crtc_disable()
4790 ironlake_fdi_pll_disable(intel_crtc); in ironlake_crtc_disable()
4793 intel_crtc->active = false; in ironlake_crtc_disable()
4805 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in haswell_crtc_disable() local
4807 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; in haswell_crtc_disable()
4809 if (!intel_crtc->active) in haswell_crtc_disable()
4822 if (intel_crtc->config->has_pch_encoder) in haswell_crtc_disable()
4825 intel_disable_pipe(intel_crtc); in haswell_crtc_disable()
4827 if (intel_crtc->config->dp_encoder_is_mst) in haswell_crtc_disable()
4833 skylake_pfit_disable(intel_crtc); in haswell_crtc_disable()
4835 ironlake_pfit_disable(intel_crtc); in haswell_crtc_disable()
4837 intel_ddi_disable_pipe_clock(intel_crtc); in haswell_crtc_disable()
4839 if (intel_crtc->config->has_pch_encoder) { in haswell_crtc_disable()
4848 intel_crtc->active = false; in haswell_crtc_disable()
4855 if (intel_crtc_to_shared_dpll(intel_crtc)) in haswell_crtc_disable()
4856 intel_disable_shared_dpll(intel_crtc); in haswell_crtc_disable()
4861 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in ironlake_crtc_off() local
4862 intel_put_shared_dpll(intel_crtc); in ironlake_crtc_off()
4866 static void i9xx_pfit_enable(struct intel_crtc *crtc) in i9xx_pfit_enable()
4942 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in get_crtc_power_domains() local
4943 enum pipe pipe = intel_crtc->pipe; in get_crtc_power_domains()
4951 if (intel_crtc->config->pch_pfit.enabled || in get_crtc_power_domains()
4952 intel_crtc->config->pch_pfit.force_thru) in get_crtc_power_domains()
4966 struct intel_crtc *crtc; in modeset_update_crtc_power_domains()
5168 struct intel_crtc *intel_crtc; in intel_mode_max_pixclk() local
5171 for_each_intel_crtc(dev, intel_crtc) { in intel_mode_max_pixclk()
5172 if (intel_crtc->new_enabled) in intel_mode_max_pixclk()
5174 intel_crtc->new_config->base.adjusted_mode.crtc_clock); in intel_mode_max_pixclk()
5184 struct intel_crtc *intel_crtc; in valleyview_modeset_global_pipes() local
5192 for_each_intel_crtc(dev, intel_crtc) in valleyview_modeset_global_pipes()
5193 if (intel_crtc->base.state->enable) in valleyview_modeset_global_pipes()
5194 *prepare_pipes |= (1 << intel_crtc->pipe); in valleyview_modeset_global_pipes()
5267 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in valleyview_crtc_enable() local
5269 int pipe = intel_crtc->pipe; in valleyview_crtc_enable()
5274 if (intel_crtc->active) in valleyview_crtc_enable()
5277 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI); in valleyview_crtc_enable()
5281 chv_prepare_pll(intel_crtc, intel_crtc->config); in valleyview_crtc_enable()
5283 vlv_prepare_pll(intel_crtc, intel_crtc->config); in valleyview_crtc_enable()
5286 if (intel_crtc->config->has_dp_encoder) in valleyview_crtc_enable()
5287 intel_dp_set_m_n(intel_crtc, M1_N1); in valleyview_crtc_enable()
5289 intel_set_pipe_timings(intel_crtc); in valleyview_crtc_enable()
5298 i9xx_set_pipeconf(intel_crtc); in valleyview_crtc_enable()
5300 intel_crtc->active = true; in valleyview_crtc_enable()
5310 chv_enable_pll(intel_crtc, intel_crtc->config); in valleyview_crtc_enable()
5312 vlv_enable_pll(intel_crtc, intel_crtc->config); in valleyview_crtc_enable()
5319 i9xx_pfit_enable(intel_crtc); in valleyview_crtc_enable()
5324 intel_enable_pipe(intel_crtc); in valleyview_crtc_enable()
5338 static void i9xx_set_pll_dividers(struct intel_crtc *crtc) in i9xx_set_pll_dividers()
5351 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in i9xx_crtc_enable() local
5353 int pipe = intel_crtc->pipe; in i9xx_crtc_enable()
5357 if (intel_crtc->active) in i9xx_crtc_enable()
5360 i9xx_set_pll_dividers(intel_crtc); in i9xx_crtc_enable()
5362 if (intel_crtc->config->has_dp_encoder) in i9xx_crtc_enable()
5363 intel_dp_set_m_n(intel_crtc, M1_N1); in i9xx_crtc_enable()
5365 intel_set_pipe_timings(intel_crtc); in i9xx_crtc_enable()
5367 i9xx_set_pipeconf(intel_crtc); in i9xx_crtc_enable()
5369 intel_crtc->active = true; in i9xx_crtc_enable()
5378 i9xx_enable_pll(intel_crtc); in i9xx_crtc_enable()
5380 i9xx_pfit_enable(intel_crtc); in i9xx_crtc_enable()
5385 intel_enable_pipe(intel_crtc); in i9xx_crtc_enable()
5409 static void i9xx_pfit_disable(struct intel_crtc *crtc) in i9xx_pfit_disable()
5428 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in i9xx_crtc_disable() local
5430 int pipe = intel_crtc->pipe; in i9xx_crtc_disable()
5432 if (!intel_crtc->active) in i9xx_crtc_disable()
5470 intel_disable_pipe(intel_crtc); in i9xx_crtc_disable()
5472 i9xx_pfit_disable(intel_crtc); in i9xx_crtc_disable()
5478 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) { in i9xx_crtc_disable()
5484 i9xx_disable_pll(intel_crtc); in i9xx_crtc_disable()
5490 intel_crtc->active = false; in i9xx_crtc_disable()
5507 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_control() local
5512 if (!intel_crtc->active) { in intel_crtc_control()
5516 intel_crtc->enabled_power_domains = domains; in intel_crtc_control()
5521 if (intel_crtc->active) { in intel_crtc_control()
5524 domains = intel_crtc->enabled_power_domains; in intel_crtc_control()
5527 intel_crtc->enabled_power_domains = 0; in intel_crtc_control()
5698 struct intel_crtc *crtc = in pipe_required_fdi_lanes()
5761 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, in ironlake_fdi_compute_config() argument
5764 struct drm_device *dev = intel_crtc->base.dev; in ironlake_fdi_compute_config()
5789 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev, in ironlake_fdi_compute_config()
5790 intel_crtc->pipe, pipe_config); in ironlake_fdi_compute_config()
5807 static void hsw_compute_ips_config(struct intel_crtc *crtc, in hsw_compute_ips_config()
5815 static int intel_crtc_compute_config(struct intel_crtc *crtc, in intel_crtc_compute_config()
6063 static void i9xx_update_pll_dividers(struct intel_crtc *crtc, in i9xx_update_pll_dividers()
6121 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, in intel_pch_transcoder_set_m_n()
6134 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, in intel_cpu_transcoder_set_m_n()
6168 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) in intel_dp_set_m_n()
6193 static void vlv_update_pll(struct intel_crtc *crtc, in vlv_update_pll()
6216 static void vlv_prepare_pll(struct intel_crtc *crtc, in vlv_prepare_pll()
6307 static void chv_update_pll(struct intel_crtc *crtc, in chv_update_pll()
6320 static void chv_prepare_pll(struct intel_crtc *crtc, in chv_prepare_pll()
6438 struct intel_crtc *crtc = in vlv_force_pll_on()
6473 static void i9xx_update_pll(struct intel_crtc *crtc, in i9xx_update_pll()
6550 static void i8xx_update_pll(struct intel_crtc *crtc, in i8xx_update_pll()
6588 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) in intel_set_pipe_timings() argument
6590 struct drm_device *dev = intel_crtc->base.dev; in intel_set_pipe_timings()
6592 enum pipe pipe = intel_crtc->pipe; in intel_set_pipe_timings()
6593 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; in intel_set_pipe_timings()
6595 &intel_crtc->config->base.adjusted_mode; in intel_set_pipe_timings()
6609 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) in intel_set_pipe_timings()
6653 ((intel_crtc->config->pipe_src_w - 1) << 16) | in intel_set_pipe_timings()
6654 (intel_crtc->config->pipe_src_h - 1)); in intel_set_pipe_timings()
6657 static void intel_get_pipe_timings(struct intel_crtc *crtc, in intel_get_pipe_timings()
6718 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) in i9xx_set_pipeconf() argument
6720 struct drm_device *dev = intel_crtc->base.dev; in i9xx_set_pipeconf()
6726 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || in i9xx_set_pipeconf()
6727 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) in i9xx_set_pipeconf()
6728 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; in i9xx_set_pipeconf()
6730 if (intel_crtc->config->double_wide) in i9xx_set_pipeconf()
6736 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) in i9xx_set_pipeconf()
6740 switch (intel_crtc->config->pipe_bpp) { in i9xx_set_pipeconf()
6757 if (intel_crtc->lowfreq_avail) { in i9xx_set_pipeconf()
6765 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { in i9xx_set_pipeconf()
6767 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) in i9xx_set_pipeconf()
6774 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range) in i9xx_set_pipeconf()
6777 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); in i9xx_set_pipeconf()
6778 POSTING_READ(PIPECONF(intel_crtc->pipe)); in i9xx_set_pipeconf()
6781 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, in i9xx_crtc_compute_clock()
6879 static void i9xx_get_pfit_config(struct intel_crtc *crtc, in i9xx_get_pfit_config()
6909 static void vlv_crtc_clock_get(struct intel_crtc *crtc, in vlv_crtc_clock_get()
6940 i9xx_get_initial_plane_config(struct intel_crtc *crtc, in i9xx_get_initial_plane_config()
7008 static void chv_crtc_clock_get(struct intel_crtc *crtc, in chv_crtc_clock_get()
7038 static bool i9xx_get_pipe_config(struct intel_crtc *crtc, in i9xx_get_pipe_config()
7521 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in ironlake_set_pipeconf() local
7522 int pipe = intel_crtc->pipe; in ironlake_set_pipeconf()
7527 switch (intel_crtc->config->pipe_bpp) { in ironlake_set_pipeconf()
7545 if (intel_crtc->config->dither) in ironlake_set_pipeconf()
7548 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) in ironlake_set_pipeconf()
7553 if (intel_crtc->config->limited_color_range) in ironlake_set_pipeconf()
7571 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_set_pipe_csc() local
7572 int pipe = intel_crtc->pipe; in intel_set_pipe_csc()
7582 if (intel_crtc->config->limited_color_range) in intel_set_pipe_csc()
7606 if (intel_crtc->config->limited_color_range) in intel_set_pipe_csc()
7617 if (intel_crtc->config->limited_color_range) in intel_set_pipe_csc()
7628 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in haswell_set_pipeconf() local
7629 enum pipe pipe = intel_crtc->pipe; in haswell_set_pipeconf()
7630 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; in haswell_set_pipeconf()
7635 if (IS_HASWELL(dev) && intel_crtc->config->dither) in haswell_set_pipeconf()
7638 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) in haswell_set_pipeconf()
7646 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); in haswell_set_pipeconf()
7647 POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); in haswell_set_pipeconf()
7652 switch (intel_crtc->config->pipe_bpp) { in haswell_set_pipeconf()
7670 if (intel_crtc->config->dither) in haswell_set_pipeconf()
7738 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, in ironlake_compute_dpll() argument
7743 struct drm_crtc *crtc = &intel_crtc->base; in ironlake_compute_dpll()
7837 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, in ironlake_crtc_compute_clock()
7900 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, in intel_pch_transcoder_get_m_n()
7916 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, in intel_cpu_transcoder_get_m_n()
7958 void intel_dp_get_m_n(struct intel_crtc *crtc, in intel_dp_get_m_n()
7969 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, in ironlake_get_fdi_m_n_config()
7976 static void skylake_get_pfit_config(struct intel_crtc *crtc, in skylake_get_pfit_config()
7993 skylake_get_initial_plane_config(struct intel_crtc *crtc, in skylake_get_initial_plane_config()
8076 static void ironlake_get_pfit_config(struct intel_crtc *crtc, in ironlake_get_pfit_config()
8101 ironlake_get_initial_plane_config(struct intel_crtc *crtc, in ironlake_get_initial_plane_config()
8169 static bool ironlake_get_pipe_config(struct intel_crtc *crtc, in ironlake_get_pipe_config()
8254 struct intel_crtc *crtc; in assert_can_disable_lcpll()
8473 static int haswell_crtc_compute_clock(struct intel_crtc *crtc, in haswell_crtc_compute_clock()
8531 static void haswell_get_ddi_port_state(struct intel_crtc *crtc, in haswell_get_ddi_port_state()
8573 static bool haswell_get_pipe_config(struct intel_crtc *crtc, in haswell_get_pipe_config()
8648 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in i845_update_cursor() local
8652 unsigned int width = intel_crtc->base.cursor->state->crtc_w; in i845_update_cursor()
8653 unsigned int height = intel_crtc->base.cursor->state->crtc_h; in i845_update_cursor()
8677 if (intel_crtc->cursor_cntl != 0 && in i845_update_cursor()
8678 (intel_crtc->cursor_base != base || in i845_update_cursor()
8679 intel_crtc->cursor_size != size || in i845_update_cursor()
8680 intel_crtc->cursor_cntl != cntl)) { in i845_update_cursor()
8686 intel_crtc->cursor_cntl = 0; in i845_update_cursor()
8689 if (intel_crtc->cursor_base != base) { in i845_update_cursor()
8691 intel_crtc->cursor_base = base; in i845_update_cursor()
8694 if (intel_crtc->cursor_size != size) { in i845_update_cursor()
8696 intel_crtc->cursor_size = size; in i845_update_cursor()
8699 if (intel_crtc->cursor_cntl != cntl) { in i845_update_cursor()
8702 intel_crtc->cursor_cntl = cntl; in i845_update_cursor()
8710 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in i9xx_update_cursor() local
8711 int pipe = intel_crtc->pipe; in i9xx_update_cursor()
8717 switch (intel_crtc->base.cursor->state->crtc_w) { in i9xx_update_cursor()
8728 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w); in i9xx_update_cursor()
8740 if (intel_crtc->cursor_cntl != cntl) { in i9xx_update_cursor()
8743 intel_crtc->cursor_cntl = cntl; in i9xx_update_cursor()
8750 intel_crtc->cursor_base = base; in i9xx_update_cursor()
8759 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_update_cursor() local
8760 int pipe = intel_crtc->pipe; in intel_crtc_update_cursor()
8766 base = intel_crtc->cursor_addr; in intel_crtc_update_cursor()
8768 if (x >= intel_crtc->config->pipe_src_w) in intel_crtc_update_cursor()
8771 if (y >= intel_crtc->config->pipe_src_h) in intel_crtc_update_cursor()
8775 if (x + intel_crtc->base.cursor->state->crtc_w <= 0) in intel_crtc_update_cursor()
8784 if (y + intel_crtc->base.cursor->state->crtc_h <= 0) in intel_crtc_update_cursor()
8792 if (base == 0 && intel_crtc->cursor_base == 0) in intel_crtc_update_cursor()
8800 base += (intel_crtc->base.cursor->state->crtc_h * in intel_crtc_update_cursor()
8801 intel_crtc->base.cursor->state->crtc_w - 1) * 4; in intel_crtc_update_cursor()
8851 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_gamma_set() local
8854 intel_crtc->lut_r[i] = red[i] >> 8; in intel_crtc_gamma_set()
8855 intel_crtc->lut_g[i] = green[i] >> 8; in intel_crtc_gamma_set()
8856 intel_crtc->lut_b[i] = blue[i] >> 8; in intel_crtc_gamma_set()
8984 struct intel_crtc *intel_crtc; in intel_get_load_detect_pipe() local
9069 intel_crtc = to_intel_crtc(crtc); in intel_get_load_detect_pipe()
9070 intel_crtc->new_enabled = true; in intel_get_load_detect_pipe()
9071 intel_crtc->new_config = intel_crtc->config; in intel_get_load_detect_pipe()
9122 intel_wait_for_vblank(dev, intel_crtc->pipe); in intel_get_load_detect_pipe()
9126 intel_crtc->new_enabled = crtc->state->enable; in intel_get_load_detect_pipe()
9127 if (intel_crtc->new_enabled) in intel_get_load_detect_pipe()
9128 intel_crtc->new_config = intel_crtc->config; in intel_get_load_detect_pipe()
9130 intel_crtc->new_config = NULL; in intel_get_load_detect_pipe()
9154 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_release_load_detect_pipe() local
9175 intel_crtc->new_enabled = false; in intel_release_load_detect_pipe()
9176 intel_crtc->new_config = NULL; in intel_release_load_detect_pipe()
9220 static void i9xx_crtc_clock_get(struct intel_crtc *crtc, in i9xx_crtc_clock_get()
9327 static void ironlake_pch_clock_get(struct intel_crtc *crtc, in ironlake_pch_clock_get()
9351 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_mode_get() local
9352 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; in intel_crtc_mode_get()
9359 enum pipe pipe = intel_crtc->pipe; in intel_crtc_mode_get()
9377 i9xx_crtc_clock_get(intel_crtc, &pipe_config); in intel_crtc_mode_get()
9398 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_decrease_pllclock() local
9410 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { in intel_decrease_pllclock()
9411 int pipe = intel_crtc->pipe; in intel_decrease_pllclock()
9467 static void intel_crtc_set_state(struct intel_crtc *crtc, in intel_crtc_set_state()
9477 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_destroy() local
9482 work = intel_crtc->unpin_work; in intel_crtc_destroy()
9483 intel_crtc->unpin_work = NULL; in intel_crtc_destroy()
9491 intel_crtc_set_state(intel_crtc, NULL); in intel_crtc_destroy()
9494 kfree(intel_crtc); in intel_crtc_destroy()
9526 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in do_intel_finish_page_flip() local
9531 if (intel_crtc == NULL) in do_intel_finish_page_flip()
9539 work = intel_crtc->unpin_work; in do_intel_finish_page_flip()
9549 page_flip_completed(intel_crtc); in do_intel_finish_page_flip()
9576 static bool page_flip_finished(struct intel_crtc *crtc) in page_flip_finished()
9619 struct intel_crtc *intel_crtc = in intel_prepare_page_flip() local
9633 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) in intel_prepare_page_flip()
9634 atomic_inc_not_zero(&intel_crtc->unpin_work->pending); in intel_prepare_page_flip()
9638 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) in intel_mark_page_flip_active() argument
9642 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); in intel_mark_page_flip_active()
9654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_gen2_queue_flip() local
9665 if (intel_crtc->plane) in intel_gen2_queue_flip()
9672 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); in intel_gen2_queue_flip()
9674 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); in intel_gen2_queue_flip()
9677 intel_mark_page_flip_active(intel_crtc); in intel_gen2_queue_flip()
9689 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_gen3_queue_flip() local
9697 if (intel_crtc->plane) in intel_gen3_queue_flip()
9704 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); in intel_gen3_queue_flip()
9706 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); in intel_gen3_queue_flip()
9709 intel_mark_page_flip_active(intel_crtc); in intel_gen3_queue_flip()
9722 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_gen4_queue_flip() local
9735 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); in intel_gen4_queue_flip()
9737 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | in intel_gen4_queue_flip()
9745 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; in intel_gen4_queue_flip()
9748 intel_mark_page_flip_active(intel_crtc); in intel_gen4_queue_flip()
9761 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_gen6_queue_flip() local
9770 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); in intel_gen6_queue_flip()
9772 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); in intel_gen6_queue_flip()
9781 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; in intel_gen6_queue_flip()
9784 intel_mark_page_flip_active(intel_crtc); in intel_gen6_queue_flip()
9796 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_gen7_queue_flip() local
9800 switch (intel_crtc->plane) { in intel_gen7_queue_flip()
9876 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); in intel_gen7_queue_flip()
9879 intel_mark_page_flip_active(intel_crtc); in intel_gen7_queue_flip()
9911 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc) in skl_do_mmio_flip() argument
9913 struct drm_device *dev = intel_crtc->base.dev; in skl_do_mmio_flip()
9915 struct drm_framebuffer *fb = intel_crtc->base.primary->fb; in skl_do_mmio_flip()
9918 const enum pipe pipe = intel_crtc->pipe; in skl_do_mmio_flip()
9941 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset); in skl_do_mmio_flip()
9945 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc) in ilk_do_mmio_flip() argument
9947 struct drm_device *dev = intel_crtc->base.dev; in ilk_do_mmio_flip()
9950 to_intel_framebuffer(intel_crtc->base.primary->fb); in ilk_do_mmio_flip()
9955 reg = DSPCNTR(intel_crtc->plane); in ilk_do_mmio_flip()
9965 I915_WRITE(DSPSURF(intel_crtc->plane), in ilk_do_mmio_flip()
9966 intel_crtc->unpin_work->gtt_offset); in ilk_do_mmio_flip()
9967 POSTING_READ(DSPSURF(intel_crtc->plane)); in ilk_do_mmio_flip()
9975 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc) in intel_do_mmio_flip() argument
9977 struct drm_device *dev = intel_crtc->base.dev; in intel_do_mmio_flip()
9981 intel_mark_page_flip_active(intel_crtc); in intel_do_mmio_flip()
9983 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count); in intel_do_mmio_flip()
9986 skl_do_mmio_flip(intel_crtc); in intel_do_mmio_flip()
9989 ilk_do_mmio_flip(intel_crtc); in intel_do_mmio_flip()
9992 intel_pipe_update_end(intel_crtc, start_vbl_count); in intel_do_mmio_flip()
9997 struct intel_crtc *crtc = in intel_mmio_flip_work_func()
9998 container_of(work, struct intel_crtc, mmio_flip.work); in intel_mmio_flip_work_func()
10022 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_queue_mmio_flip() local
10024 i915_gem_request_assign(&intel_crtc->mmio_flip.req, in intel_queue_mmio_flip()
10027 schedule_work(&intel_crtc->mmio_flip.work); in intel_queue_mmio_flip()
10046 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in __intel_pageflip_stall_check() local
10047 struct intel_unpin_work *work = intel_crtc->unpin_work; in __intel_pageflip_stall_check()
10070 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); in __intel_pageflip_stall_check()
10072 addr = I915_READ(DSPADDR(intel_crtc->plane)); in __intel_pageflip_stall_check()
10085 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_check_page_flip() local
10093 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) { in intel_check_page_flip()
10095 intel_crtc->unpin_work->flip_queued_vblank, in intel_check_page_flip()
10097 page_flip_completed(intel_crtc); in intel_check_page_flip()
10111 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_crtc_page_flip() local
10113 enum pipe pipe = intel_crtc->pipe; in intel_crtc_page_flip()
10157 if (intel_crtc->unpin_work) { in intel_crtc_page_flip()
10163 page_flip_completed(intel_crtc); in intel_crtc_page_flip()
10173 intel_crtc->unpin_work = work; in intel_crtc_page_flip()
10176 if (atomic_read(&intel_crtc->unpin_work_count) >= 2) in intel_crtc_page_flip()
10192 atomic_inc(&intel_crtc->unpin_work_count); in intel_crtc_page_flip()
10193 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); in intel_crtc_page_flip()
10219 + intel_crtc->dspaddr_offset; in intel_crtc_page_flip()
10249 trace_i915_flip_request(intel_crtc->plane, obj); in intel_crtc_page_flip()
10256 atomic_dec(&intel_crtc->unpin_work_count); in intel_crtc_page_flip()
10266 intel_crtc->unpin_work = NULL; in intel_crtc_page_flip()
10300 struct intel_crtc *crtc; in intel_modeset_update_staged_output_state()
10352 struct intel_crtc *crtc; in intel_modeset_commit_output_state()
10409 compute_baseline_pipe_bpp(struct intel_crtc *crtc, in compute_baseline_pipe_bpp()
10484 static void intel_dump_pipe_config(struct intel_crtc *crtc, in intel_dump_pipe_config()
10546 static bool check_single_encoder_cloning(struct intel_crtc *crtc, in check_single_encoder_cloning()
10563 static bool check_encoder_cloning(struct intel_crtc *crtc) in check_encoder_cloning()
10772 struct intel_crtc *intel_crtc; in intel_modeset_affected_pipes() local
10814 for_each_intel_crtc(dev, intel_crtc) { in intel_modeset_affected_pipes()
10815 if (intel_crtc->base.state->enable == intel_crtc->new_enabled) in intel_modeset_affected_pipes()
10818 if (!intel_crtc->new_enabled) in intel_modeset_affected_pipes()
10819 *disable_pipes |= 1 << intel_crtc->pipe; in intel_modeset_affected_pipes()
10821 *prepare_pipes |= 1 << intel_crtc->pipe; in intel_modeset_affected_pipes()
10826 intel_crtc = to_intel_crtc(crtc); in intel_modeset_affected_pipes()
10827 if (intel_crtc->new_enabled) in intel_modeset_affected_pipes()
10828 *prepare_pipes |= 1 << intel_crtc->pipe; in intel_modeset_affected_pipes()
10847 *modeset_pipes &= 1 << intel_crtc->pipe; in intel_modeset_affected_pipes()
10848 *prepare_pipes &= 1 << intel_crtc->pipe; in intel_modeset_affected_pipes()
10871 struct intel_crtc *intel_crtc; in intel_modeset_update_state() local
10880 intel_crtc = to_intel_crtc(intel_encoder->base.crtc); in intel_modeset_update_state()
10882 if (prepare_pipes & (1 << intel_crtc->pipe)) in intel_modeset_update_state()
10889 for_each_intel_crtc(dev, intel_crtc) { in intel_modeset_update_state()
10890 WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base)); in intel_modeset_update_state()
10891 WARN_ON(intel_crtc->new_config && in intel_modeset_update_state()
10892 intel_crtc->new_config != intel_crtc->config); in intel_modeset_update_state()
10893 WARN_ON(intel_crtc->base.state->enable != !!intel_crtc->new_config); in intel_modeset_update_state()
10900 intel_crtc = to_intel_crtc(connector->encoder->crtc); in intel_modeset_update_state()
10902 if (prepare_pipes & (1 << intel_crtc->pipe)) { in intel_modeset_update_state()
10936 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ argument
10937 list_for_each_entry((intel_crtc), \
10940 if (mask & (1 <<(intel_crtc)->pipe))
11136 struct intel_crtc *intel_crtc; in check_wm_state() local
11145 for_each_intel_crtc(dev, intel_crtc) { in check_wm_state()
11147 const enum pipe pipe = intel_crtc->pipe; in check_wm_state()
11149 if (!intel_crtc->active) in check_wm_state()
11258 struct intel_crtc *crtc; in check_crtc_state()
11325 struct intel_crtc *crtc; in check_shared_dpll_state()
11392 static void update_scanline_offset(struct intel_crtc *crtc) in update_scanline_offset()
11441 struct intel_crtc *intel_crtc; in intel_modeset_compute_config() local
11451 for_each_intel_crtc_masked(dev, *disable_pipes, intel_crtc) { in intel_modeset_compute_config()
11452 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); in intel_modeset_compute_config()
11465 for_each_intel_crtc_masked(dev, *modeset_pipes, intel_crtc) { in intel_modeset_compute_config()
11468 if (WARN_ON(&intel_crtc->base != crtc)) in intel_modeset_compute_config()
11488 struct intel_crtc *intel_crtc; in __intel_set_mode_setup_plls() local
11498 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { in __intel_set_mode_setup_plls()
11499 struct intel_crtc_state *state = intel_crtc->new_config; in __intel_set_mode_setup_plls()
11500 ret = dev_priv->display.crtc_compute_clock(intel_crtc, in __intel_set_mode_setup_plls()
11524 struct intel_crtc *intel_crtc; in __intel_set_mode() local
11560 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) in __intel_set_mode()
11561 intel_crtc_disable(&intel_crtc->base); in __intel_set_mode()
11563 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { in __intel_set_mode()
11564 if (intel_crtc->base.state->enable) in __intel_set_mode()
11565 dev_priv->display.crtc_disable(&intel_crtc->base); in __intel_set_mode()
11599 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { in __intel_set_mode()
11600 struct drm_plane *primary = intel_crtc->base.primary; in __intel_set_mode()
11604 ret = primary->funcs->update_plane(primary, &intel_crtc->base, in __intel_set_mode()
11612 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { in __intel_set_mode()
11613 update_scanline_offset(intel_crtc); in __intel_set_mode()
11615 dev_priv->display.crtc_enable(&intel_crtc->base); in __intel_set_mode()
11624 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in __intel_set_mode() local
11628 memcpy(crtc_state_copy, intel_crtc->config, in __intel_set_mode()
11630 intel_crtc->config = crtc_state_copy; in __intel_set_mode()
11631 intel_crtc->base.state = &crtc_state_copy->base; in __intel_set_mode()
11634 intel_crtc->new_config = intel_crtc->config; in __intel_set_mode()
11805 struct intel_crtc *crtc; in intel_set_config_restore_state()
11870 struct intel_crtc *intel_crtc = in intel_set_config_compute_mode_changes() local
11873 if (intel_crtc->active) { in intel_set_config_compute_mode_changes()
11913 struct intel_crtc *crtc; in intel_modeset_stage_output_state()
12053 static void disable_crtc_nofb(struct intel_crtc *crtc) in disable_crtc_nofb()
12167 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc); in intel_crtc_set_config() local
12181 if (!intel_crtc->primary_enabled && ret == 0) { in intel_crtc_set_config()
12182 WARN_ON(!intel_crtc->active); in intel_crtc_set_config()
12290 struct intel_crtc *crtc; in ibx_pch_dpll_disable()
12455 struct intel_crtc *intel_crtc; in intel_check_primary_plane() local
12463 intel_crtc = to_intel_crtc(crtc); in intel_check_primary_plane()
12473 if (intel_crtc->active) { in intel_check_primary_plane()
12474 intel_crtc->atomic.wait_for_flips = true; in intel_check_primary_plane()
12486 if (intel_crtc->primary_enabled && in intel_check_primary_plane()
12488 dev_priv->fbc.crtc == intel_crtc && in intel_check_primary_plane()
12490 intel_crtc->atomic.disable_fbc = true; in intel_check_primary_plane()
12499 if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled) in intel_check_primary_plane()
12500 intel_crtc->atomic.wait_vblank = true; in intel_check_primary_plane()
12511 intel_crtc->atomic.disable_ips = true; in intel_check_primary_plane()
12513 intel_crtc->atomic.fb_bits |= in intel_check_primary_plane()
12514 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe); in intel_check_primary_plane()
12516 intel_crtc->atomic.update_fbc = true; in intel_check_primary_plane()
12519 intel_crtc->atomic.update_wm = true; in intel_check_primary_plane()
12533 struct intel_crtc *intel_crtc; in intel_commit_primary_plane() local
12537 intel_crtc = to_intel_crtc(crtc); in intel_commit_primary_plane()
12543 if (intel_crtc->active) { in intel_commit_primary_plane()
12546 intel_update_pipe_size(intel_crtc); in intel_commit_primary_plane()
12548 intel_crtc->primary_enabled = true; in intel_commit_primary_plane()
12569 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_begin_crtc_commit() local
12578 if (intel_crtc->atomic.disabled_planes & in intel_begin_crtc_commit()
12598 if (intel_crtc->atomic.wait_for_flips) in intel_begin_crtc_commit()
12601 if (intel_crtc->atomic.disable_fbc) in intel_begin_crtc_commit()
12604 if (intel_crtc->atomic.disable_ips) in intel_begin_crtc_commit()
12605 hsw_disable_ips(intel_crtc); in intel_begin_crtc_commit()
12607 if (intel_crtc->atomic.pre_disable_primary) in intel_begin_crtc_commit()
12610 if (intel_crtc->atomic.update_wm) in intel_begin_crtc_commit()
12616 if (intel_crtc->active) in intel_begin_crtc_commit()
12617 intel_crtc->atomic.evade = in intel_begin_crtc_commit()
12618 intel_pipe_update_start(intel_crtc, in intel_begin_crtc_commit()
12619 &intel_crtc->atomic.start_vbl_count); in intel_begin_crtc_commit()
12626 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); in intel_finish_crtc_commit() local
12629 if (intel_crtc->atomic.evade) in intel_finish_crtc_commit()
12630 intel_pipe_update_end(intel_crtc, in intel_finish_crtc_commit()
12631 intel_crtc->atomic.start_vbl_count); in intel_finish_crtc_commit()
12635 if (intel_crtc->atomic.wait_vblank) in intel_finish_crtc_commit()
12636 intel_wait_for_vblank(dev, intel_crtc->pipe); in intel_finish_crtc_commit()
12638 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits); in intel_finish_crtc_commit()
12640 if (intel_crtc->atomic.update_fbc) { in intel_finish_crtc_commit()
12646 if (intel_crtc->atomic.post_enable_primary) in intel_finish_crtc_commit()
12650 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p)) in intel_finish_crtc_commit()
12654 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic)); in intel_finish_crtc_commit()
12752 struct intel_crtc *intel_crtc; in intel_check_cursor_plane() local
12757 intel_crtc = to_intel_crtc(crtc); in intel_check_cursor_plane()
12791 if (intel_crtc->active) { in intel_check_cursor_plane()
12793 intel_crtc->atomic.update_wm = true; in intel_check_cursor_plane()
12795 intel_crtc->atomic.fb_bits |= in intel_check_cursor_plane()
12796 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe); in intel_check_cursor_plane()
12808 struct intel_crtc *intel_crtc; in intel_commit_cursor_plane() local
12813 intel_crtc = to_intel_crtc(crtc); in intel_commit_cursor_plane()
12819 if (intel_crtc->cursor_bo == obj) in intel_commit_cursor_plane()
12829 intel_crtc->cursor_addr = addr; in intel_commit_cursor_plane()
12830 intel_crtc->cursor_bo = obj; in intel_commit_cursor_plane()
12833 if (intel_crtc->active) in intel_commit_cursor_plane()
12887 struct intel_crtc *intel_crtc; in intel_crtc_init() local
12893 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); in intel_crtc_init()
12894 if (intel_crtc == NULL) in intel_crtc_init()
12900 intel_crtc_set_state(intel_crtc, crtc_state); in intel_crtc_init()
12901 crtc_state->base.crtc = &intel_crtc->base; in intel_crtc_init()
12911 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, in intel_crtc_init()
12916 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); in intel_crtc_init()
12918 intel_crtc->lut_r[i] = i; in intel_crtc_init()
12919 intel_crtc->lut_g[i] = i; in intel_crtc_init()
12920 intel_crtc->lut_b[i] = i; in intel_crtc_init()
12927 intel_crtc->pipe = pipe; in intel_crtc_init()
12928 intel_crtc->plane = pipe; in intel_crtc_init()
12931 intel_crtc->plane = !pipe; in intel_crtc_init()
12934 intel_crtc->cursor_base = ~0; in intel_crtc_init()
12935 intel_crtc->cursor_cntl = ~0; in intel_crtc_init()
12936 intel_crtc->cursor_size = ~0; in intel_crtc_init()
12939 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); in intel_crtc_init()
12940 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; in intel_crtc_init()
12941 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; in intel_crtc_init()
12943 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func); in intel_crtc_init()
12945 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); in intel_crtc_init()
12947 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); in intel_crtc_init()
12956 kfree(intel_crtc); in intel_crtc_init()
12977 struct intel_crtc *crtc; in intel_get_pipe_from_crtc_id()
13769 struct intel_crtc *crtc; in intel_modeset_init()
13912 intel_check_plane_mapping(struct intel_crtc *crtc) in intel_check_plane_mapping()
13931 static void intel_sanitize_crtc(struct intel_crtc *crtc) in intel_sanitize_crtc()
14120 static bool primary_get_hw_state(struct intel_crtc *crtc) in primary_get_hw_state()
14134 struct intel_crtc *crtc; in intel_modeset_readout_hw_state()
14219 struct intel_crtc *crtc; in intel_modeset_setup_hw_state()
14622 struct intel_crtc *crtc; in intel_modeset_preclose()