844 static void vlv_write_wm_values(struct intel_crtc *crtc,  in vlv_write_wm_values()
914 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in vlv_compute_drain_latency()  local
916 	int clock = intel_crtc->config->base.adjusted_mode.crtc_clock;  in vlv_compute_drain_latency()
923 	if (!intel_crtc->active || !plane->state->fb)  in vlv_compute_drain_latency()
951 static int vlv_compute_wm(struct intel_crtc *crtc,  in vlv_compute_wm()
1029 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in valleyview_update_wm()  local
1030 	enum pipe pipe = intel_crtc->pipe;  in valleyview_update_wm()
1035 	wm.pipe[pipe].primary = vlv_compute_wm(intel_crtc,  in valleyview_update_wm()
1040 	wm.pipe[pipe].cursor = vlv_compute_wm(intel_crtc,  in valleyview_update_wm()
1068 	vlv_write_wm_values(intel_crtc, &wm);  in valleyview_update_wm()
1083 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in valleyview_update_sprite_wm()  local
1084 	enum pipe pipe = intel_crtc->pipe;  in valleyview_update_sprite_wm()
1094 			vlv_compute_wm(intel_crtc,  in valleyview_update_sprite_wm()
1116 	vlv_write_wm_values(intel_crtc, &wm);  in valleyview_update_sprite_wm()
1417 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in ilk_pipe_pixel_rate()  local
1420 	pixel_rate = intel_crtc->config->base.adjusted_mode.crtc_clock;  in ilk_pipe_pixel_rate()
1425 	if (intel_crtc->config->pch_pfit.enabled) {  in ilk_pipe_pixel_rate()
1427 		uint32_t pfit_size = intel_crtc->config->pch_pfit.size;  in ilk_pipe_pixel_rate()
1429 		pipe_w = intel_crtc->config->pipe_src_w;  in ilk_pipe_pixel_rate()
1430 		pipe_h = intel_crtc->config->pipe_src_h;  in ilk_pipe_pixel_rate()
1782 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in hsw_compute_linetime_wm()  local
1783 	struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode;  in hsw_compute_linetime_wm()
1786 	if (!intel_crtc->active)  in hsw_compute_linetime_wm()
2037 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in ilk_compute_wm_parameters()  local
2038 	enum pipe pipe = intel_crtc->pipe;  in ilk_compute_wm_parameters()
2041 	if (!intel_crtc->active)  in ilk_compute_wm_parameters()
2045 	p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;  in ilk_compute_wm_parameters()
2062 	p->pri.horiz_pixels = intel_crtc->config->pipe_src_w;  in ilk_compute_wm_parameters()
2063 	p->cur.horiz_pixels = intel_crtc->base.cursor->state->crtc_w;  in ilk_compute_wm_parameters()
2078 	struct intel_crtc *intel_crtc;  in ilk_compute_wm_config()  local
2081 	for_each_intel_crtc(dev, intel_crtc) {  in ilk_compute_wm_config()
2082 		const struct intel_pipe_wm *wm = &intel_crtc->wm.active;  in ilk_compute_wm_config()
2161 	const struct intel_crtc *intel_crtc;  in ilk_merge_wm_level()  local
2165 	for_each_intel_crtc(dev, intel_crtc) {  in ilk_merge_wm_level()
2166 		const struct intel_pipe_wm *active = &intel_crtc->wm.active;  in ilk_merge_wm_level()
2266 	struct intel_crtc *intel_crtc;  in ilk_compute_wm_results()  local
2311 	for_each_intel_crtc(dev, intel_crtc) {  in ilk_compute_wm_results()
2312 		enum pipe pipe = intel_crtc->pipe;  in ilk_compute_wm_results()
2314 			&intel_crtc->wm.active.wm[0];  in ilk_compute_wm_results()
2319 		results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;  in ilk_compute_wm_results()
2624 skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc,  in skl_get_total_relative_data_rate()  argument
2630 	for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {  in skl_get_total_relative_data_rate()
2651 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in skl_allocate_pipe_ddb()  local
2652 	enum pipe pipe = intel_crtc->pipe;  in skl_allocate_pipe_ddb()
2692 	total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params);  in skl_allocate_pipe_ddb()
2695 	for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {  in skl_allocate_pipe_ddb()
2778 				       const struct intel_crtc *intel_crtc)  in skl_ddb_allocation_changed()  argument
2780 	struct drm_device *dev = intel_crtc->base.dev;  in skl_ddb_allocation_changed()
2783 	enum pipe pipe = intel_crtc->pipe;  in skl_ddb_allocation_changed()
2818 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in skl_compute_wm_pipe_parameters()  local
2819 	enum pipe pipe = intel_crtc->pipe;  in skl_compute_wm_pipe_parameters()
2824 	p->active = intel_crtc->active;  in skl_compute_wm_pipe_parameters()
2826 		p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;  in skl_compute_wm_pipe_parameters()
2827 		p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config);  in skl_compute_wm_pipe_parameters()
2839 		p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;  in skl_compute_wm_pipe_parameters()
2840 		p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;  in skl_compute_wm_pipe_parameters()
2985 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in skl_compute_transition_wm()  local
2992 	for (i = 0; i < intel_num_planes(intel_crtc); i++)  in skl_compute_transition_wm()
3004 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in skl_compute_pipe_wm()  local
3008 		skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe,  in skl_compute_pipe_wm()
3009 				     level, intel_num_planes(intel_crtc),  in skl_compute_pipe_wm()
3021 				   struct intel_crtc *intel_crtc)  in skl_compute_wm_results()  argument
3024 	enum pipe pipe = intel_crtc->pipe;  in skl_compute_wm_results()
3029 		for (i = 0; i < intel_num_planes(intel_crtc); i++) {  in skl_compute_wm_results()
3054 	for (i = 0; i < intel_num_planes(intel_crtc); i++) {  in skl_compute_wm_results()
3088 	struct intel_crtc *crtc;  in skl_write_wm_values()
3180 	struct intel_crtc *crtc;  in skl_flush_wm_values()
3262 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in skl_update_pipe_wm()  local
3268 	if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm)))  in skl_update_pipe_wm()
3271 	intel_crtc->wm.skl_active = *pipe_wm;  in skl_update_pipe_wm()
3280 	struct intel_crtc *intel_crtc;  in skl_update_other_pipe_wm()  local
3281 	struct intel_crtc *this_crtc = to_intel_crtc(crtc);  in skl_update_other_pipe_wm()
3296 	list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,  in skl_update_other_pipe_wm()
3302 		if (this_crtc->pipe == intel_crtc->pipe)  in skl_update_other_pipe_wm()
3305 		if (!intel_crtc->active)  in skl_update_other_pipe_wm()
3308 		wm_changed = skl_update_pipe_wm(&intel_crtc->base,  in skl_update_other_pipe_wm()
3319 		skl_compute_wm_results(dev, &params, &pipe_wm, r, intel_crtc);  in skl_update_other_pipe_wm()
3320 		r->dirty[intel_crtc->pipe] = true;  in skl_update_other_pipe_wm()
3326 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in skl_update_wm()  local
3342 	skl_compute_wm_results(dev, &params, &pipe_wm, results, intel_crtc);  in skl_update_wm()
3343 	results->dirty[intel_crtc->pipe] = true;  in skl_update_wm()
3380 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in ilk_update_wm()  local
3395 	if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))  in ilk_update_wm()
3398 	intel_crtc->wm.active = pipe_wm;  in ilk_update_wm()
3501 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in skl_pipe_wm_get_hw_state()  local
3502 	struct skl_pipe_wm *active = &intel_crtc->wm.skl_active;  in skl_pipe_wm_get_hw_state()
3503 	enum pipe pipe = intel_crtc->pipe;  in skl_pipe_wm_get_hw_state()
3512 		for (i = 0; i < intel_num_planes(intel_crtc); i++)  in skl_pipe_wm_get_hw_state()
3518 	for (i = 0; i < intel_num_planes(intel_crtc); i++)  in skl_pipe_wm_get_hw_state()
3522 	if (!intel_crtc->active)  in skl_pipe_wm_get_hw_state()
3530 		for (i = 0; i < intel_num_planes(intel_crtc); i++) {  in skl_pipe_wm_get_hw_state()
3539 	for (i = 0; i < intel_num_planes(intel_crtc); i++) {  in skl_pipe_wm_get_hw_state()
3564 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);  in ilk_pipe_wm_get_hw_state()  local
3565 	struct intel_pipe_wm *active = &intel_crtc->wm.active;  in ilk_pipe_wm_get_hw_state()
3566 	enum pipe pipe = intel_crtc->pipe;  in ilk_pipe_wm_get_hw_state()
3579 	active->pipe_enabled = intel_crtc->active;  in ilk_pipe_wm_get_hw_state()