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Searched refs:i915_gem_obj_ggtt_offset (Results 1 – 17 of 17) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/i915/
Di915_gem_tiling.c298 if (i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) in i915_gem_object_fence_ok()
301 if (i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) in i915_gem_object_fence_ok()
309 if (i915_gem_obj_ggtt_offset(obj) & (size - 1)) in i915_gem_object_fence_ok()
Dintel_overlay.c199 i915_gem_obj_ggtt_offset(overlay->reg_bo)); in intel_overlay_map_regs()
769 iowrite32(i915_gem_obj_ggtt_offset(new_bo) + params->offset_Y, &regs->OBUF_0Y); in intel_overlay_do_put_image()
783 iowrite32(i915_gem_obj_ggtt_offset(new_bo) + params->offset_U, &regs->OBUF_0U); in intel_overlay_do_put_image()
784 iowrite32(i915_gem_obj_ggtt_offset(new_bo) + params->offset_V, &regs->OBUF_0V); in intel_overlay_do_put_image()
1384 overlay->flip_addr = i915_gem_obj_ggtt_offset(reg_bo); in intel_setup_overlay()
1461 i915_gem_obj_ggtt_offset(overlay->reg_bo)); in intel_overlay_map_regs_atomic()
1494 error->base = i915_gem_obj_ggtt_offset(overlay->reg_bo); in intel_overlay_capture_error_state()
Dintel_ringbuffer.h55 (i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \
60 (i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \
Di915_gem_render_state.c68 so->ggtt_offset = i915_gem_obj_ggtt_offset(so->obj); in render_state_init()
Dintel_fbdev.c246 info->fix.smem_start = dev->mode_config.fb_base + i915_gem_obj_ggtt_offset(obj); in intelfb_create()
250 ioremap_wc(dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj), in intelfb_create()
275 i915_gem_obj_ggtt_offset(obj), obj); in intelfb_create()
Di915_gem.c807 offset = i915_gem_obj_ggtt_offset(obj) + args->offset; in i915_gem_gtt_pwrite_fast()
1665 pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj); in i915_gem_fault()
3096 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) & in i965_write_fence_reg()
3098 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000; in i965_write_fence_reg()
3126 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) || in i915_write_fence_reg()
3128 (i915_gem_obj_ggtt_offset(obj) & (size - 1)), in i915_write_fence_reg()
3130 i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size); in i915_write_fence_reg()
3141 val = i915_gem_obj_ggtt_offset(obj); in i915_write_fence_reg()
3169 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) || in i830_write_fence_reg()
3171 (i915_gem_obj_ggtt_offset(obj) & (size - 1)), in i830_write_fence_reg()
[all …]
Dintel_ringbuffer.c610 I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj)); in init_ring_common()
625 I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) && in init_ring_common()
632 I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj)); in init_ring_common()
689 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj); in intel_init_pipe_control()
1872 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj); in init_status_page()
1924 i915_gem_obj_ggtt_offset(obj), ringbuf->size); in intel_pin_and_map_ringbuffer_obj()
2622 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj); in intel_init_render_ring_buffer()
Dintel_sprite.c477 I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) + in vlv_update_plane()
628 i915_gem_obj_ggtt_offset(obj) + sprsurf_offset); in ivb_update_plane()
763 i915_gem_obj_ggtt_offset(obj) + dvssurf_offset); in ilk_update_plane()
Dintel_lrc.c250 u32 lrca = i915_gem_obj_ggtt_offset(ctx_obj); in intel_execlists_ctx_id()
262 uint64_t lrca = i915_gem_obj_ggtt_offset(ctx_obj); in execlists_ctx_descriptor()
332 reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(ring_obj); in execlists_update_context()
1904 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(default_ctx_obj); in lrc_setup_hardware_status_page()
Dintel_fbc.c215 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID); in ilk_fbc_enable()
Di915_gem_context.c547 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(new_context->legacy_hw_ctx.rcs_state) | in mi_set_context()
Di915_gem_execbuffer.c314 offset = i915_gem_obj_ggtt_offset(obj); in relocate_entry_gtt()
1600 exec_start += i915_gem_obj_ggtt_offset(batch_obj); in i915_gem_do_execbuffer()
Di915_gpu_error.c616 reloc_offset = i915_gem_obj_ggtt_offset(src); in i915_error_object_create()
960 if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) { in i915_gem_record_active_context()
Di915_gem_gtt.c2057 i915_gem_obj_ggtt_offset(obj), obj->base.size); in i915_gem_setup_global_gtt()
Di915_drv.h2804 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o) in i915_gem_obj_ggtt_offset() function
Dintel_display.c2645 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { in intel_find_initial_plane_obj()
2786 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); in i9xx_update_primary_plane()
2790 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); in i9xx_update_primary_plane()
2886 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); in ironlake_update_primary_plane()
12825 addr = i915_gem_obj_ggtt_offset(obj); in intel_commit_cursor_plane()
Di915_debugfs.c1913 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj); in i915_dump_lrc_obj()