Searched refs:fcr (Results 1 - 39 of 39) sorted by relevance

/linux-4.1.27/arch/m68k/include/asm/
H A Dsun3xflop.h38 unsigned char fcr; member in struct:sun3xflop_private
85 unsigned char fcr = sun3x_fdc.fcr; sun3x_82072_fd_outb() local
88 fcr |= (FCR_DSEL0 | FCR_MTRON); sun3x_82072_fd_outb()
90 fcr &= ~(FCR_DSEL0 | FCR_MTRON); sun3x_82072_fd_outb()
93 if(fcr != sun3x_fdc.fcr) { sun3x_82072_fd_outb()
94 *(sun3x_fdc.fcr_r) = fcr; sun3x_82072_fd_outb()
95 sun3x_fdc.fcr = fcr; sun3x_82072_fd_outb()
226 sun3x_fdc.fcr = 0; sun3xflop_init()
250 sun3x_fdc.fcr |= (FCR_DSEL0 | FCR_EJECT); sun3x_eject()
251 *(sun3x_fdc.fcr_r) = sun3x_fdc.fcr; sun3x_eject()
253 sun3x_fdc.fcr &= ~(FCR_DSEL0 | FCR_EJECT); sun3x_eject()
254 *(sun3x_fdc.fcr_r) = sun3x_fdc.fcr; sun3x_eject()
/linux-4.1.27/drivers/mtd/nand/
H A Dtmio_nand.c112 void __iomem *fcr; member in struct:tmio_nand
152 tmio_iowrite8(mode, tmio->fcr + FCR_MODE); tmio_nand_hwcontrol()
164 return !(tmio_ioread8(tmio->fcr + FCR_STATUS) & FCR_STATUS_BUSY); tmio_nand_dev_ready()
173 tmio_iowrite8(0x00, tmio->fcr + FCR_IMR); tmio_irq()
195 tmio_iowrite8(0x0f, tmio->fcr + FCR_ISR); tmio_nand_wait()
196 tmio_iowrite8(0x81, tmio->fcr + FCR_IMR); tmio_nand_wait()
203 tmio_iowrite8(0x00, tmio->fcr + FCR_IMR); tmio_nand_wait()
209 tmio_iowrite8(0x00, tmio->fcr + FCR_IMR); tmio_nand_wait()
233 data = tmio_ioread16(tmio->fcr + FCR_DATA); tmio_nand_read_byte()
249 tmio_iowrite16_rep(tmio->fcr + FCR_DATA, buf, len >> 1); tmio_nand_write_buf()
256 tmio_ioread16_rep(tmio->fcr + FCR_DATA, buf, len >> 1); tmio_nand_read_buf()
263 tmio_iowrite8(FCR_MODE_HWECC_RESET, tmio->fcr + FCR_MODE); tmio_nand_enable_hwecc()
264 tmio_ioread8(tmio->fcr + FCR_DATA); /* dummy read */ tmio_nand_enable_hwecc()
265 tmio_iowrite8(FCR_MODE_HWECC_CALC, tmio->fcr + FCR_MODE); tmio_nand_enable_hwecc()
274 tmio_iowrite8(FCR_MODE_HWECC_RESULT, tmio->fcr + FCR_MODE); tmio_nand_calculate_ecc()
276 ecc = tmio_ioread16(tmio->fcr + FCR_DATA); tmio_nand_calculate_ecc()
279 ecc = tmio_ioread16(tmio->fcr + FCR_DATA); tmio_nand_calculate_ecc()
282 ecc = tmio_ioread16(tmio->fcr + FCR_DATA); tmio_nand_calculate_ecc()
286 tmio_iowrite8(FCR_MODE_DATA, tmio->fcr + FCR_MODE); tmio_nand_calculate_ecc()
334 tmio_iowrite8(0x0f, tmio->fcr + FCR_ISR); tmio_hw_init()
337 tmio_iowrite8(FCR_MODE_POWER_ON, tmio->fcr + FCR_MODE); tmio_hw_init()
338 tmio_iowrite8(FCR_MODE_COMMAND, tmio->fcr + FCR_MODE); tmio_hw_init()
339 tmio_iowrite8(NAND_CMD_RESET, tmio->fcr + FCR_DATA); tmio_hw_init()
342 tmio_iowrite8(FCR_MODE_STANDBY, tmio->fcr + FCR_MODE); tmio_hw_init()
353 tmio_iowrite8(FCR_MODE_POWER_OFF, tmio->fcr + FCR_MODE); tmio_hw_stop()
361 struct resource *fcr = platform_get_resource(dev, tmio_probe() local
390 tmio->fcr_base = fcr->start & 0xfffff; tmio_probe()
391 tmio->fcr = devm_ioremap(&dev->dev, fcr->start, resource_size(fcr)); tmio_probe()
392 if (!tmio->fcr) tmio_probe()
400 nand_chip->IO_ADDR_R = tmio->fcr; tmio_probe()
401 nand_chip->IO_ADDR_W = tmio->fcr; tmio_probe()
H A Dfsl_elbc_nand.c210 "fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n", fsl_elbc_run_command()
211 in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr)); fsl_elbc_run_command()
234 "command failed: fir %x fcr %x status %x mdr %x\n", fsl_elbc_run_command()
235 in_be32(&lbc->fir), in_be32(&lbc->fcr), fsl_elbc_run_command()
283 out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) | fsl_elbc_do_read()
293 out_be32(&lbc->fcr, NAND_CMD_READOOB << FCR_CMD0_SHIFT); fsl_elbc_do_read()
295 out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT); fsl_elbc_do_read()
360 out_be32(&lbc->fcr, command << FCR_CMD0_SHIFT); fsl_elbc_cmdfunc()
392 out_be32(&lbc->fcr, fsl_elbc_cmdfunc()
406 __be32 fcr; fsl_elbc_cmdfunc() local
424 fcr = (NAND_CMD_STATUS << FCR_CMD1_SHIFT) | fsl_elbc_cmdfunc()
450 fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT; fsl_elbc_cmdfunc()
453 fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT; fsl_elbc_cmdfunc()
456 out_be32(&lbc->fcr, fcr); fsl_elbc_cmdfunc()
488 out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT); fsl_elbc_cmdfunc()
505 out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT); fsl_elbc_cmdfunc()
/linux-4.1.27/lib/reed_solomon/
H A Dreed_solomon.c59 * @fcr: first root of RS code generator polynomial, index form
67 int fcr, int prim, int nroots) rs_init()
81 rs->fcr = fcr; rs_init()
132 for (i = 0, root = fcr * prim; i < nroots; i++, root += prim) { rs_init()
194 * @fcr: the first consecutive root of the rs code generator polynomial
200 int (*gffunc)(int), int fcr, init_rs_internal()
209 if (fcr < 0 || fcr >= (1<<symsize)) init_rs_internal()
227 if (fcr != rs->fcr) init_rs_internal()
239 rs = rs_init(symsize, gfpoly, gffunc, fcr, prim, nroots); init_rs_internal()
255 * @fcr: the first consecutive root of the rs code generator polynomial
260 struct rs_control *init_rs(int symsize, int gfpoly, int fcr, int prim, init_rs() argument
263 return init_rs_internal(symsize, gfpoly, NULL, fcr, prim, nroots); init_rs()
274 * @fcr: the first consecutive root of the rs code generator polynomial
280 int fcr, int prim, int nroots) init_rs_non_canonical()
282 return init_rs_internal(symsize, 0, gffunc, fcr, prim, nroots); init_rs_non_canonical()
66 rs_init(int symsize, int gfpoly, int (*gffunc)(int), int fcr, int prim, int nroots) rs_init() argument
199 init_rs_internal(int symsize, int gfpoly, int (*gffunc)(int), int fcr, int prim, int nroots) init_rs_internal() argument
279 init_rs_non_canonical(int symsize, int (*gffunc)(int), int fcr, int prim, int nroots) init_rs_non_canonical() argument
H A Ddecode_rs.c24 int fcr = rs->fcr; variable
62 (fcr + i) * prim)];
74 (fcr+i)*prim)];
225 * inv(X(l))**(fcr-1) and den = lambda_pr(inv(X(l))) all in poly-form
234 num2 = alpha_to[rs_modnn(rs, root[j] * (fcr - 1) + nn)];
/linux-4.1.27/include/linux/
H A Drslib.h33 * @fcr: First consecutive root, index form
48 int fcr; member in struct:rs_control
80 struct rs_control *init_rs(int symsize, int gfpoly, int fcr, int prim,
83 int fcr, int prim, int nroots);
H A Dserial_8250.h94 unsigned char fcr; member in struct:uart_8250_port
/linux-4.1.27/arch/powerpc/platforms/powermac/
H A Dfeature.c168 unsigned long fcr; ohare_htw_scc_enable() local
194 fcr = MACIO_IN32(OHARE_FCR); ohare_htw_scc_enable()
196 if (!(fcr & OH_SCC_ENABLE)) { ohare_htw_scc_enable()
197 fcr |= OH_SCC_ENABLE; ohare_htw_scc_enable()
205 fcr &= ~HRW_SCC_TRANS_EN_N; ohare_htw_scc_enable()
206 MACIO_OUT32(OHARE_FCR, fcr); ohare_htw_scc_enable()
207 fcr |= (rmask = HRW_RESET_SCC); ohare_htw_scc_enable()
208 MACIO_OUT32(OHARE_FCR, fcr); ohare_htw_scc_enable()
210 fcr |= (rmask = OH_SCC_RESET); ohare_htw_scc_enable()
211 MACIO_OUT32(OHARE_FCR, fcr); ohare_htw_scc_enable()
217 fcr &= ~rmask; ohare_htw_scc_enable()
218 MACIO_OUT32(OHARE_FCR, fcr); ohare_htw_scc_enable()
221 fcr |= OH_SCCA_IO; ohare_htw_scc_enable()
223 fcr |= OH_SCCB_IO; ohare_htw_scc_enable()
224 MACIO_OUT32(OHARE_FCR, fcr); ohare_htw_scc_enable()
233 fcr = MACIO_IN32(OHARE_FCR); ohare_htw_scc_enable()
235 fcr &= ~OH_SCCA_IO; ohare_htw_scc_enable()
237 fcr &= ~OH_SCCB_IO; ohare_htw_scc_enable()
238 MACIO_OUT32(OHARE_FCR, fcr); ohare_htw_scc_enable()
239 if ((fcr & (OH_SCCA_IO | OH_SCCB_IO)) == 0) { ohare_htw_scc_enable()
240 fcr &= ~OH_SCC_ENABLE; ohare_htw_scc_enable()
242 fcr |= HRW_SCC_TRANS_EN_N; ohare_htw_scc_enable()
243 MACIO_OUT32(OHARE_FCR, fcr); ohare_htw_scc_enable()
608 u32 fcr; core99_scc_enable() local
625 fcr = MACIO_IN32(KEYLARGO_FCR0); core99_scc_enable()
627 if (!(fcr & KL0_SCC_CELL_ENABLE)) { core99_scc_enable()
628 fcr |= KL0_SCC_CELL_ENABLE; core99_scc_enable()
632 fcr |= KL0_SCCA_ENABLE; core99_scc_enable()
635 fcr &= ~KL0_SCC_A_INTF_ENABLE; core99_scc_enable()
637 fcr |= KL0_SCC_A_INTF_ENABLE; core99_scc_enable()
640 fcr |= KL0_SCCB_ENABLE; core99_scc_enable()
643 fcr &= ~KL0_SCC_B_INTF_ENABLE; core99_scc_enable()
644 fcr |= KL0_IRDA_ENABLE; core99_scc_enable()
645 fcr |= KL0_IRDA_CLK32_ENABLE | KL0_IRDA_CLK19_ENABLE; core99_scc_enable()
646 fcr |= KL0_IRDA_SOURCE1_SEL; core99_scc_enable()
647 fcr &= ~(KL0_IRDA_FAST_CONNECT|KL0_IRDA_DEFAULT1|KL0_IRDA_DEFAULT0); core99_scc_enable()
648 fcr &= ~(KL0_IRDA_SOURCE2_SEL|KL0_IRDA_HIGH_BAND); core99_scc_enable()
651 fcr |= KL0_SCC_B_INTF_ENABLE; core99_scc_enable()
653 MACIO_OUT32(KEYLARGO_FCR0, fcr); core99_scc_enable()
678 fcr = MACIO_IN32(KEYLARGO_FCR0); core99_scc_enable()
680 fcr &= ~KL0_SCCA_ENABLE; core99_scc_enable()
682 fcr &= ~KL0_SCCB_ENABLE; core99_scc_enable()
685 fcr &= ~KL0_IRDA_ENABLE; core99_scc_enable()
686 fcr &= ~(KL0_IRDA_CLK32_ENABLE | KL0_IRDA_CLK19_ENABLE); core99_scc_enable()
687 fcr &= ~(KL0_IRDA_FAST_CONNECT|KL0_IRDA_DEFAULT1|KL0_IRDA_DEFAULT0); core99_scc_enable()
688 fcr &= ~(KL0_IRDA_SOURCE1_SEL|KL0_IRDA_SOURCE2_SEL|KL0_IRDA_HIGH_BAND); core99_scc_enable()
691 MACIO_OUT32(KEYLARGO_FCR0, fcr); core99_scc_enable()
692 if ((fcr & (KL0_SCCA_ENABLE | KL0_SCCB_ENABLE)) == 0) { core99_scc_enable()
693 fcr &= ~KL0_SCC_CELL_ENABLE; core99_scc_enable()
694 MACIO_OUT32(KEYLARGO_FCR0, fcr); core99_scc_enable()
/linux-4.1.27/drivers/net/ethernet/freescale/
H A Dgianfar_ethtool.c677 u32 fcr = 0x0, fpr = FPR_FILER_MASK; ethflow_to_filer_rules() local
680 fcr = RQFCR_PID_DAH |RQFCR_CMP_NOMATCH | ethflow_to_filer_rules()
683 priv->ftp_rqfcr[priv->cur_filer_idx] = fcr; ethflow_to_filer_rules()
684 gfar_write_filer(priv, priv->cur_filer_idx, fcr, fpr); ethflow_to_filer_rules()
687 fcr = RQFCR_PID_DAL | RQFCR_AND | RQFCR_CMP_NOMATCH | ethflow_to_filer_rules()
690 priv->ftp_rqfcr[priv->cur_filer_idx] = fcr; ethflow_to_filer_rules()
691 gfar_write_filer(priv, priv->cur_filer_idx, fcr, fpr); ethflow_to_filer_rules()
696 fcr = RQFCR_PID_VID | RQFCR_CMP_NOMATCH | RQFCR_HASH | ethflow_to_filer_rules()
698 gfar_write_filer(priv, priv->cur_filer_idx, fcr, fpr); ethflow_to_filer_rules()
700 priv->ftp_rqfcr[priv->cur_filer_idx] = fcr; ethflow_to_filer_rules()
705 fcr = RQFCR_PID_SIA | RQFCR_CMP_NOMATCH | RQFCR_HASH | ethflow_to_filer_rules()
708 priv->ftp_rqfcr[priv->cur_filer_idx] = fcr; ethflow_to_filer_rules()
709 gfar_write_filer(priv, priv->cur_filer_idx, fcr, fpr); ethflow_to_filer_rules()
714 fcr = RQFCR_PID_DIA | RQFCR_CMP_NOMATCH | RQFCR_HASH | ethflow_to_filer_rules()
717 priv->ftp_rqfcr[priv->cur_filer_idx] = fcr; ethflow_to_filer_rules()
718 gfar_write_filer(priv, priv->cur_filer_idx, fcr, fpr); ethflow_to_filer_rules()
723 fcr = RQFCR_PID_L4P | RQFCR_CMP_NOMATCH | RQFCR_HASH | ethflow_to_filer_rules()
726 priv->ftp_rqfcr[priv->cur_filer_idx] = fcr; ethflow_to_filer_rules()
727 gfar_write_filer(priv, priv->cur_filer_idx, fcr, fpr); ethflow_to_filer_rules()
732 fcr = RQFCR_PID_SPT | RQFCR_CMP_NOMATCH | RQFCR_HASH | ethflow_to_filer_rules()
735 priv->ftp_rqfcr[priv->cur_filer_idx] = fcr; ethflow_to_filer_rules()
736 gfar_write_filer(priv, priv->cur_filer_idx, fcr, fpr); ethflow_to_filer_rules()
741 fcr = RQFCR_PID_DPT | RQFCR_CMP_NOMATCH | RQFCR_HASH | ethflow_to_filer_rules()
744 priv->ftp_rqfcr[priv->cur_filer_idx] = fcr; ethflow_to_filer_rules()
745 gfar_write_filer(priv, priv->cur_filer_idx, fcr, fpr); ethflow_to_filer_rules()
H A Dgianfar.h1215 unsigned int far, unsigned int fcr, unsigned int fpr) gfar_write_filer()
1220 gfar_write(&regs->rqfcr, fcr); gfar_write_filer()
1225 unsigned int far, unsigned int *fcr, unsigned int *fpr) gfar_read_filer()
1230 *fcr = gfar_read(&regs->rqfcr); gfar_read_filer()
1214 gfar_write_filer(struct gfar_private *priv, unsigned int far, unsigned int fcr, unsigned int fpr) gfar_write_filer() argument
1224 gfar_read_filer(struct gfar_private *priv, unsigned int far, unsigned int *fcr, unsigned int *fpr) gfar_read_filer() argument
/linux-4.1.27/drivers/bluetooth/
H A Dbtuart_cs.c348 int fcr; /* FIFO control reg */ btuart_change_speed() local
366 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT; btuart_change_speed()
375 fcr |= UART_FCR_TRIGGER_1; btuart_change_speed()
377 fcr |= UART_FCR_TRIGGER_14; btuart_change_speed()
386 outb(fcr, iobase + UART_FCR); /* Enable FIFO's */ btuart_change_speed()
/linux-4.1.27/drivers/tty/serial/
H A Dserial-tegra.c248 unsigned long fcr = tup->fcr_shadow; tegra_uart_fifo_reset() local
251 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); tegra_uart_fifo_reset()
252 tegra_uart_write(tup, fcr, UART_FCR); tegra_uart_fifo_reset()
254 fcr &= ~UART_FCR_ENABLE_FIFO; tegra_uart_fifo_reset()
255 tegra_uart_write(tup, fcr, UART_FCR); tegra_uart_fifo_reset()
257 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); tegra_uart_fifo_reset()
258 tegra_uart_write(tup, fcr, UART_FCR); tegra_uart_fifo_reset()
259 fcr |= UART_FCR_ENABLE_FIFO; tegra_uart_fifo_reset()
260 tegra_uart_write(tup, fcr, UART_FCR); tegra_uart_fifo_reset()
H A Dpxa.c437 unsigned char cval, fcr = 0; serial_pxa_set_termios() local
472 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR1; serial_pxa_set_termios()
474 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR8; serial_pxa_set_termios()
476 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR32; serial_pxa_set_termios()
551 serial_out(up, UART_FCR, fcr); serial_pxa_set_termios()
H A Dpch_uart.c243 unsigned int fcr; member in struct:eg20t_port
508 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR); pch_uart_hal_fifo_reset()
509 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag, pch_uart_hal_fifo_reset()
511 iowrite8(priv->fcr, priv->membase + UART_FCR); pch_uart_hal_fifo_reset()
520 u8 fcr; pch_uart_hal_set_fifo() local
558 fcr = pch_uart_hal_set_fifo()
563 iowrite8(fcr, priv->membase + UART_FCR); pch_uart_hal_set_fifo()
564 priv->fcr = fcr; pch_uart_hal_set_fifo()
1827 priv->fcr = 0; pch_uart_init_port()
H A Dsunsu.c782 unsigned char cval, fcr = 0; sunsu_change_speed() local
823 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1; sunsu_change_speed()
826 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_14; sunsu_change_speed()
829 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_8; sunsu_change_speed()
832 fcr |= UART_FCR7_64BYTE; sunsu_change_speed()
890 serial_outp(up, UART_FCR, fcr); /* set fcr */ sunsu_change_speed()
894 if (fcr & UART_FCR_ENABLE_FIFO) { sunsu_change_speed()
898 serial_outp(up, UART_FCR, fcr); /* set fcr */ sunsu_change_speed()
H A Domap-serial.c143 unsigned char fcr; member in struct:uart_omap_port
363 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_RCVR); serial_omap_stop_tx()
910 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 | serial_omap_set_termios()
1000 up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK; serial_omap_set_termios()
1001 up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK; serial_omap_set_termios()
1002 up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 | serial_omap_set_termios()
1005 serial_out(up, UART_FCR, up->fcr); serial_omap_set_termios()
1777 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | serial_omap_mdr1_errataset()
1813 serial_out(up, UART_FCR, up->fcr); serial_omap_restore_context()
H A Dserial_ks8695.c384 unsigned int lcr, fcr = 0; ks8695uart_set_termios() local
428 fcr = URFC_URFRT_8 | URFC_URTFR | URFC_URRFR | URFC_URFE; ks8695uart_set_termios()
475 UART_PUT_FCR(port, fcr); ks8695uart_set_termios()
H A Dvr41xx_siu.c519 uint8_t lcr, fcr, ier; siu_set_termios() local
551 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10; siu_set_termios()
590 siu_write(port, UART_FCR, fcr); siu_set_termios()
H A Dserial_txx9.c633 unsigned int cval, fcr = 0; serial_txx9_set_termios() local
677 fcr = TXX9_SIFCR_TDIL_MAX | TXX9_SIFCR_RDIL_1; serial_txx9_set_termios()
731 sio_out(up, TXX9_SIFCR, fcr); serial_txx9_set_termios()
H A Dioc4_serial.c262 char fcr; /* write only */ member in union:ioc4_uartregs::__anon10360
283 #define i4u_fcr u3.fcr
/linux-4.1.27/drivers/tty/serial/8250/
H A D8250_core.c163 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
182 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
191 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
205 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
213 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
222 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
229 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
236 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
243 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
250 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
257 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
264 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
271 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
280 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
288 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
297 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
314 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
321 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
328 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
338 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
346 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
588 serial_out(p, UART_FCR, p->fcr); serial8250_clear_and_reinit_fifos()
2592 up->fcr &= ~UART_FCR_TRIGGER_MASK; serial8250_do_set_termios()
2593 up->fcr |= UART_FCR_TRIGGER_1; serial8250_do_set_termios()
2682 serial_port_out(port, UART_FCR, up->fcr); serial8250_do_set_termios()
2687 if (up->fcr & UART_FCR_ENABLE_FIFO) serial8250_do_set_termios()
2689 serial_port_out(port, UART_FCR, up->fcr); /* set fcr */ serial8250_do_set_termios()
2896 bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)]; fcr_get_rxtrig_bytes()
2972 up->fcr &= ~UART_FCR_TRIGGER_MASK; do_set_rxtrig()
2973 up->fcr |= (unsigned char)rxtrig; do_set_rxtrig()
2974 serial_out(up, UART_FCR, up->fcr); do_set_rxtrig()
3073 up->fcr = uart_config[up->port.type].fcr; serial8250_config_port()
H A D8250.h67 unsigned char fcr; member in struct:serial8250_config
H A D8250_omap.c151 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | omap_8250_mdr1_errataset()
254 serial_out(up, UART_FCR, up->fcr); omap8250_restore_regs()
405 up->fcr = UART_FCR_ENABLE_FIFO; omap_8250_set_termios()
406 up->fcr |= TRIGGER_FCR_MASK(TX_TRIGGER) << OMAP_UART_FCR_TX_TRIG; omap_8250_set_termios()
407 up->fcr |= TRIGGER_FCR_MASK(RX_TRIGGER) << OMAP_UART_FCR_RX_TRIG; omap_8250_set_termios()
/linux-4.1.27/arch/ia64/include/asm/sn/
H A Dioc3.h23 char fcr; /* write only */ member in union:ioc3_uartregs::__anon1546
46 #define iu_fcr u3.fcr
/linux-4.1.27/arch/ia64/kernel/
H A Dparavirt.c427 __DEFINE_GET_AR(FCR, fcr)
510 __DEFINE_SET_AR(FCR, fcr)
708 IA64_NATIVE_PATCH_DEFINE_AR(fcr, fcr);
820 IA64_NATIVE_PATCH_BUNDLE_ELEM_AR(fcr, FCR),
/linux-4.1.27/drivers/isdn/hisax/
H A Delsa_ser.c111 unsigned cval, fcr = 0; change_speed() local
125 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1; change_speed()
127 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_8; change_speed()
128 serial_outp(cs, UART_FCR, fcr); change_speed()
/linux-4.1.27/drivers/tty/
H A Dmxser.c642 unsigned cflag, cval, fcr; mxser_change_speed() local
682 fcr = UART_FCR_ENABLE_FIFO; mxser_change_speed()
683 fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE; mxser_change_speed()
686 fcr = 0; mxser_change_speed()
688 fcr = UART_FCR_ENABLE_FIFO; mxser_change_speed()
690 fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE; mxser_change_speed()
695 fcr |= UART_FCR_TRIGGER_1; mxser_change_speed()
698 fcr |= UART_FCR_TRIGGER_4; mxser_change_speed()
701 fcr |= UART_FCR_TRIGGER_8; mxser_change_speed()
704 fcr |= UART_FCR_TRIGGER_14; mxser_change_speed()
807 outb(fcr, info->ioaddr + UART_FCR); /* set fcr */ mxser_change_speed()
1023 char fcr; mxser_flush_buffer() local
1030 fcr = inb(info->ioaddr + UART_FCR); mxser_flush_buffer()
1031 outb((fcr | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT), mxser_flush_buffer()
1033 outb(fcr, info->ioaddr + UART_FCR); mxser_flush_buffer()
/linux-4.1.27/arch/sh/include/asm/
H A Dsmc37c93x.h91 #define fcr iir macro
/linux-4.1.27/drivers/ide/
H A Dpmac.c873 u32 fcr = readl(pmif->kauai_fcr); pmac_ide_do_suspend() local
874 fcr &= ~(KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE); pmac_ide_do_suspend()
875 writel(fcr, pmif->kauai_fcr); pmac_ide_do_suspend()
899 u32 fcr = readl(pmif->kauai_fcr); pmac_ide_do_resume() local
900 fcr |= KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE; pmac_ide_do_resume()
901 writel(fcr, pmif->kauai_fcr); pmac_ide_do_resume()
/linux-4.1.27/drivers/mmc/card/
H A Dsdio_uart.c256 unsigned char cval, fcr = 0; sdio_uart_change_speed() local
302 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1; sdio_uart_change_speed()
304 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10; sdio_uart_change_speed()
348 sdio_out(port, UART_FCR, fcr); sdio_uart_change_speed()
/linux-4.1.27/drivers/net/irda/
H A Dsmsc-ircc2.c1135 int fcr; /* FIFO control reg */ smsc_ircc_set_sir_speed() local
1152 fcr = UART_FCR_ENABLE_FIFO; smsc_ircc_set_sir_speed()
1159 fcr |= self->io.speed < 38400 ? smsc_ircc_set_sir_speed()
1169 outb(fcr, iobase + UART_FCR); /* Enable FIFO's */ smsc_ircc_set_sir_speed()
1960 int fcr; smsc_ircc_sir_write_wakeup() local
2001 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR; smsc_ircc_sir_write_wakeup()
2002 fcr |= self->io.speed < 38400 ? smsc_ircc_sir_write_wakeup()
2005 outb(fcr, iobase + UART_FCR); smsc_ircc_sir_write_wakeup()
H A Dali-ircc.c1036 int fcr; /* FIFO control reg */ ali_ircc_sir_change_speed() local
1068 fcr = UART_FCR_ENABLE_FIFO; ali_ircc_sir_change_speed()
1076 fcr |= UART_FCR_TRIGGER_1; ali_ircc_sir_change_speed()
1078 fcr |= UART_FCR_TRIGGER_14; ali_ircc_sir_change_speed()
1087 outb(fcr, iobase+UART_FCR); /* Enable FIFO's */ ali_ircc_sir_change_speed()
/linux-4.1.27/arch/mips/include/asm/sn/
H A Dioc3.h23 volatile u8 fcr; /* write only */ member in union:ioc3_uartregs::__anon2065
38 #define iu_fcr u3.fcr
/linux-4.1.27/arch/powerpc/include/asm/
H A Dfsl_lbc.h220 __be32 fcr; /**< Flash Command Register */ member in struct:fsl_lbc_regs
/linux-4.1.27/drivers/ata/
H A Dpata_macio.c871 u32 fcr = readl(priv->kauai_fcr); pata_macio_do_suspend() local
872 fcr &= ~(KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE); pata_macio_do_suspend()
873 writel(fcr, priv->kauai_fcr); pata_macio_do_suspend()
/linux-4.1.27/drivers/net/ethernet/broadcom/
H A Dbcmsysport.h515 u32 fcr; /* RO # of carrier sense error pkt */ member in struct:bcm_sysport_rx_counters
H A Dbcmsysport.c227 STAT_MIB_RX("rx_carrier", mib.rx.fcr),
/linux-4.1.27/drivers/net/ethernet/broadcom/genet/
H A Dbcmgenet.h102 u32 fcr; /* RO # of carrier sense error pkt */ member in struct:bcmgenet_rx_counters
H A Dbcmgenet.c589 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),

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