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Searched refs:enable_bit (Results 1 – 38 of 38) sorted by relevance

/linux-4.1.27/drivers/clk/sirf/
Dclk-common.c41 signed char enable_bit; /* enable bit: 0 ~ 63 */ member
49 signed char enable_bit; /* enable bit: 0 ~ 63 */ member
534 .enable_bit = 0,
549 .enable_bit = 8,
564 .enable_bit = 9,
584 .enable_bit = 10,
599 .enable_bit = 11,
636 bit = clk->enable_bit % 32; in std_clk_is_enabled()
637 reg = clk->enable_bit / 32; in std_clk_is_enabled()
649 BUG_ON(clk->enable_bit < 0 || clk->enable_bit > 63); in std_clk_enable()
[all …]
Dclk-prima2.c24 .enable_bit = 59,
32 .enable_bit = 60,
40 .enable_bit = 61,
54 .enable_bit = 34,
Dclk-atlas6.c24 .enable_bit = 59,
32 .enable_bit = 60,
40 .enable_bit = 61,
55 .enable_bit = 34,
/linux-4.1.27/arch/arm/mach-omap1/
Dclock_data.c102 .enable_bit = EN_CKOUT_ARM,
114 .enable_bit = CONF_MOD_SOSSI_CLK_EN_R,
136 .enable_bit = EN_PERCK,
155 .enable_bit = EN_GPIOCK,
166 .enable_bit = EN_XORPCK,
179 .enable_bit = EN_TIMCK,
192 .enable_bit = EN_WDTCK,
216 .enable_bit = EN_DSPCK,
238 .enable_bit = EN_PERCK,
250 .enable_bit = EN_XORPCK,
[all …]
Dclock.c47 return val & clk->enable_bit ? 48000000 : 12000000; in omap1_uart_recalc()
336 val &= ~(1 << clk->enable_bit); in omap1_set_uart_rate()
338 val |= (1 << clk->enable_bit); in omap1_set_uart_rate()
465 regval32 |= (1 << clk->enable_bit); in omap1_clk_enable_generic()
469 regval16 |= (1 << clk->enable_bit); in omap1_clk_enable_generic()
486 regval32 &= ~(1 << clk->enable_bit); in omap1_clk_disable_generic()
490 regval16 &= ~(1 << clk->enable_bit); in omap1_clk_disable_generic()
602 if ((regval32 & (1 << clk->enable_bit)) == 0) in omap1_clk_disable_unused()
Dclock.h154 u8 enable_bit; member
/linux-4.1.27/tools/power/cpupower/utils/idle_monitor/
Damd_fam14h_idle.c99 unsigned int *enable_bit, in amd_fam14h_get_pci_info() argument
104 *enable_bit = PCI_NON_PC0_ENABLE_BIT; in amd_fam14h_get_pci_info()
108 *enable_bit = PCI_PC1_ENABLE_BIT; in amd_fam14h_get_pci_info()
112 *enable_bit = PCI_PC6_ENABLE_BIT; in amd_fam14h_get_pci_info()
116 *enable_bit = PCI_NBP1_ENTERED_BIT; in amd_fam14h_get_pci_info()
127 int enable_bit, pci_offset, ret; in amd_fam14h_init() local
130 ret = amd_fam14h_get_pci_info(state, &pci_offset, &enable_bit, cpu); in amd_fam14h_init()
137 val |= 1 << enable_bit; in amd_fam14h_init()
146 val |= 1 << enable_bit; in amd_fam14h_init()
150 state->name, PCI_MONITOR_ENABLE_REG, enable_bit, in amd_fam14h_init()
[all …]
/linux-4.1.27/arch/arm/mach-omap2/
Dclock3517.c56 *idlest_bit = clk->enable_bit + AM35XX_IPSS_ICK_EN_ACK_OFFSET; in am35xx_clk_find_idlest()
79 if (clk->enable_bit & AM35XX_IPSS_ICK_MASK) in am35xx_clk_find_companion()
80 *other_bit = clk->enable_bit + AM35XX_IPSS_ICK_FCK_OFFSET; in am35xx_clk_find_companion()
82 *other_bit = clk->enable_bit - AM35XX_IPSS_ICK_FCK_OFFSET; in am35xx_clk_find_companion()
Dclock.c339 *other_bit = clk->enable_bit; in omap2_clk_dflt_find_companion()
363 *idlest_bit = clk->enable_bit; in omap2_clk_dflt_find_idlest()
413 v &= ~(1 << clk->enable_bit); in omap2_dflt_clk_enable()
415 v |= (1 << clk->enable_bit); in omap2_dflt_clk_enable()
457 v |= (1 << clk->enable_bit); in omap2_dflt_clk_disable()
459 v &= ~(1 << clk->enable_bit); in omap2_dflt_clk_disable()
559 v ^= BIT(clk->enable_bit); in omap2_dflt_clk_is_enabled()
561 v &= BIT(clk->enable_bit); in omap2_dflt_clk_is_enabled()
Dclkt_iclk.c35 v |= (1 << clk->enable_bit); in omap2_clkt_iclk_allow_idle()
49 v &= ~(1 << clk->enable_bit); in omap2_clkt_iclk_deny_idle()
Dcm2xxx.c140 static int _omap2xxx_apll_enable(u8 enable_bit, u8 status_bit) in _omap2xxx_apll_enable() argument
144 m = EN_APLL_LOCKED << enable_bit; in _omap2xxx_apll_enable()
163 static void _omap2xxx_apll_disable(u8 enable_bit) in _omap2xxx_apll_disable() argument
168 v &= ~(EN_APLL_LOCKED << enable_bit); in _omap2xxx_apll_disable()
Dclock2430.c49 *idlest_bit = clk->enable_bit; in omap2430_clk_i2chs_find_idlest()
Dclock.h102 .enable_bit = _enable_bit, \
/linux-4.1.27/drivers/regulator/
Dmc13xxx.h20 int enable_bit; member
71 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
89 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
104 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
Dtps6586x-regulator.c62 int enable_bit[2]; member
131 .enable_bit[0] = (ebit0), \
133 .enable_bit[1] = (ebit1),
156 .enable_bit[0] = (ebit0), \
158 .enable_bit[1] = (ebit1),
277 ri->enable_bit[0] == ri->enable_bit[1]) in tps6586x_regulator_preinit()
288 if (!(val2 & (1 << ri->enable_bit[1]))) in tps6586x_regulator_preinit()
295 if (!(val1 & (1 << ri->enable_bit[0]))) { in tps6586x_regulator_preinit()
297 1 << ri->enable_bit[0]); in tps6586x_regulator_preinit()
303 1 << ri->enable_bit[1]); in tps6586x_regulator_preinit()
Dmc13xxx-regulator-core.c40 mc13xxx_regulators[id].enable_bit, in mc13xxx_regulator_enable()
41 mc13xxx_regulators[id].enable_bit); in mc13xxx_regulator_enable()
53 mc13xxx_regulators[id].enable_bit, 0); in mc13xxx_regulator_disable()
67 return (val & mc13xxx_regulators[id].enable_bit) != 0; in mc13xxx_regulator_is_enabled()
Dmc13783-regulator.c334 u32 en_val = mc13xxx_regulators[id].enable_bit; in mc13783_gpo_regulator_enable()
343 return mc13783_powermisc_rmw(priv, mc13xxx_regulators[id].enable_bit, in mc13783_gpo_regulator_enable()
359 dis_val = mc13xxx_regulators[id].enable_bit; in mc13783_gpo_regulator_disable()
361 return mc13783_powermisc_rmw(priv, mc13xxx_regulators[id].enable_bit, in mc13783_gpo_regulator_disable()
384 return (val & mc13xxx_regulators[id].enable_bit) != 0; in mc13783_gpo_regulator_is_enabled()
Dda903x.c86 int enable_bit; member
145 1 << info->enable_bit); in da903x_enable()
154 1 << info->enable_bit); in da903x_disable()
168 return !!(reg_val & (1 << info->enable_bit)); in da903x_is_enabled()
330 .enable_bit = (ebit), \
352 .enable_bit = (ebit), \
Dmc13892-regulator.c341 u32 en_val = mc13892_regulators[id].enable_bit; in mc13892_gpo_regulator_enable()
342 u32 mask = mc13892_regulators[id].enable_bit; in mc13892_gpo_regulator_enable()
366 dis_val = mc13892_regulators[id].enable_bit; in mc13892_gpo_regulator_disable()
368 return mc13892_powermisc_rmw(priv, mc13892_regulators[id].enable_bit, in mc13892_gpo_regulator_disable()
390 return (val & mc13892_regulators[id].enable_bit) != 0; in mc13892_gpo_regulator_is_enabled()
/linux-4.1.27/drivers/clk/shmobile/
Dclk-sh73a0.c94 u32 enable_bit = name[3] - '0'; in sh73a0_cpg_register_clock() local
97 switch (enable_bit) { in sh73a0_cpg_register_clock()
113 if (clk_readl(cpg->reg + CPG_PLLECR) & BIT(enable_bit)) { in sh73a0_cpg_register_clock()
116 if (enable_bit == 1 || enable_bit == 2) in sh73a0_cpg_register_clock()
/linux-4.1.27/include/linux/
Dsh_clk.h56 unsigned int enable_bit; member
124 .enable_bit = _enable_bit, \
158 .enable_bit = _shift, \
182 .enable_bit = 0, /* unused */ \
195 .enable_bit = 0, /* unused */ \
/linux-4.1.27/drivers/clk/ti/
Dinterface.c52 clk_hw->enable_bit = bit_idx; in _register_interface()
110 u8 enable_bit = 0; in _of_ti_interface_clk_setup() local
118 enable_bit = val; in _of_ti_interface_clk_setup()
127 enable_bit, ops); in _of_ti_interface_clk_setup()
Dgate.c115 clk_hw->enable_bit = bit_idx; in _register_gate()
199 gate->enable_bit = setup->bit_shift; in ti_clk_build_component_gate()
221 u8 enable_bit = 0; in _of_ti_gate_clk_setup() local
232 enable_bit = val; in _of_ti_gate_clk_setup()
249 enable_bit, clk_gate_flags, ops, hw_ops); in _of_ti_gate_clk_setup()
272 gate->enable_bit = val; in _of_ti_composite_gate_clk_setup()
Dapll.c372 clk_hw->enable_bit = val; in of_omap2_apll_setup()
/linux-4.1.27/drivers/sh/clk/
Dcpg.c56 sh_clk_write(sh_clk_read(clk) & ~(1 << clk->enable_bit), clk); in sh_clk_mstp_enable()
71 (read(mapped_status) & (1 << clk->enable_bit)) && i; in sh_clk_mstp_enable()
76 clk->enable_reg, clk->enable_bit); in sh_clk_mstp_enable()
85 sh_clk_write(sh_clk_read(clk) | (1 << clk->enable_bit), clk); in sh_clk_mstp_disable()
138 idx = (sh_clk_read(clk) >> clk->enable_bit) & clk->div_mask; in sh_clk_div_recalc()
154 value &= ~(clk->div_mask << clk->enable_bit); in sh_clk_div_set_rate()
155 value |= (idx << clk->enable_bit); in sh_clk_div_set_rate()
/linux-4.1.27/arch/mips/pci/
Dpci-virtio-guest.c23 __BITFIELD_FIELD(unsigned enable_bit : 1, /* 31 */
51 pca.enable_bit = 1; in pci_virtio_guest_write_config_addr()
/linux-4.1.27/arch/arm/mach-shmobile/
Dclock-sh73a0.c98 if (__raw_readl(PLLECR) & (1 << clk->enable_bit)) { in pll_recalc()
101 switch (clk->enable_bit) { in pll_recalc()
121 .enable_bit = 0,
129 .enable_bit = 1,
137 .enable_bit = 2,
145 .enable_bit = 3,
/linux-4.1.27/drivers/clk/spear/
Dclk-aux-synth.c41 .enable_bit = AUX_SYNT_ENB,
184 aux->masks->enable_bit, 0, lock); in clk_register_aux()
Dclk.h40 u32 enable_bit; member
Dspear1340_clock.c348 .enable_bit = SPEAR1340_I2S_SCLK_SYNTH_ENB,
Dspear1310_clock.c309 .enable_bit = SPEAR1310_I2S_SCLK_SYNTH_ENB,
/linux-4.1.27/sound/soc/ux500/
Dux500_msp_i2s.c577 u32 reg_val_GCR, enable_bit; in ux500_msp_i2s_trigger() local
590 enable_bit = TX_ENABLE; in ux500_msp_i2s_trigger()
592 enable_bit = RX_ENABLE; in ux500_msp_i2s_trigger()
594 writel(reg_val_GCR | enable_bit, msp->registers + MSP_GCR); in ux500_msp_i2s_trigger()
/linux-4.1.27/drivers/clk/bcm/
Dclk-kona.c270 u32 enable_bit; in __ccu_policy_engine_stop() local
279 enable_bit = enable->bit; in __ccu_policy_engine_stop()
280 ret = __ccu_wait_bit(ccu, offset, enable_bit, false); in __ccu_policy_engine_stop()
288 __ccu_write(ccu, offset, (u32)1 << enable_bit); in __ccu_policy_engine_stop()
291 ret = __ccu_wait_bit(ccu, offset, enable_bit, false); in __ccu_policy_engine_stop()
/linux-4.1.27/include/linux/clk/
Dti.h143 u8 enable_bit; member
/linux-4.1.27/arch/sh/drivers/pci/
Dpcie-sh7786.c240 clk->enable_bit = BITS_CKE; in pcie_clk_init()
/linux-4.1.27/drivers/spi/
Dspi-rspi.c435 u8 enable_bit) in rspi_wait_for_interrupt() argument
443 rspi_enable_irq(rspi, enable_bit); in rspi_wait_for_interrupt()
/linux-4.1.27/drivers/net/ethernet/qlogic/qlge/
Dqlge_main.c421 u32 enable_bit = *((u32 *) &addr[0]); in ql_set_mac_addr_reg() local
435 enable_bit); /* enable/disable */ in ql_set_mac_addr_reg()
2406 u32 enable_bit = MAC_ADDR_E; in __qlge_vlan_rx_add_vid() local
2409 err = ql_set_mac_addr_reg(qdev, (u8 *) &enable_bit, in __qlge_vlan_rx_add_vid()
2437 u32 enable_bit = 0; in __qlge_vlan_rx_kill_vid() local
2440 err = ql_set_mac_addr_reg(qdev, (u8 *) &enable_bit, in __qlge_vlan_rx_kill_vid()
/linux-4.1.27/drivers/net/ethernet/broadcom/
Dtg3.c8803 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, bool silent) in tg3_stop_block() argument
8826 val &= ~enable_bit; in tg3_stop_block()
8834 ofs, enable_bit); in tg3_stop_block()
8840 if ((val & enable_bit) == 0) in tg3_stop_block()
8847 ofs, enable_bit); in tg3_stop_block()