Searched refs:div_mask (Results 1 – 14 of 14) sorted by relevance
| /linux-4.1.27/arch/arm/mach-imx/ |
| D | clk-pllv3.c | 43 u32 div_mask; member
102 u32 div = (readl_relaxed(pll->base) >> pll->div_shift) & pll->div_mask; in clk_pllv3_recalc_rate()
130 val &= ~(pll->div_mask << pll->div_shift); in clk_pllv3_set_rate()
149 u32 div = readl_relaxed(pll->base) & pll->div_mask; in clk_pllv3_sys_recalc_rate()
184 val &= ~pll->div_mask; in clk_pllv3_sys_set_rate()
205 u32 div = readl_relaxed(pll->base) & pll->div_mask; in clk_pllv3_av_recalc_rate()
254 val &= ~pll->div_mask; in clk_pllv3_av_set_rate()
285 u32 div_mask) in imx_clk_pllv3() argument
316 pll->div_mask = div_mask; in imx_clk_pllv3()
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| D | clk-fixup-div.c | 19 #define div_mask(d) ((1 << (d->width)) - 1) macro
73 if (value > div_mask(div)) in clk_fixup_div_set_rate()
74 value = div_mask(div); in clk_fixup_div_set_rate()
79 val &= ~(div_mask(div) << div->shift); in clk_fixup_div_set_rate()
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| D | clk.h | 29 const char *parent_name, void __iomem *base, u32 div_mask);
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| /linux-4.1.27/drivers/clk/ |
| D | clk-divider.c | 33 #define div_mask(width) ((1 << (width)) - 1) macro
61 return div_mask(width); in _get_maxdiv()
63 return 1 << div_mask(width); in _get_maxdiv()
66 return div_mask(width) + 1; in _get_maxdiv()
141 val &= div_mask(divider->width); in clk_divider_recalc_rate()
353 bestdiv &= div_mask(divider->width); in clk_divider_round_rate()
375 return min_t(unsigned int, value, div_mask(width)); in divider_get_val()
394 val = div_mask(divider->width) << (divider->shift + 16); in clk_divider_set_rate()
397 val &= ~(div_mask(divider->width) << divider->shift); in clk_divider_set_rate()
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| D | clk-vt8500.c | 32 unsigned int div_mask; member
127 u32 div = readl(cdev->div_reg) & cdev->div_mask; in vt8500_dclk_recalc_rate()
130 if ((cdev->div_mask == 0x3F) && (div & BIT(5))) in vt8500_dclk_recalc_rate()
135 div = (cdev->div_mask + 1); in vt8500_dclk_recalc_rate()
159 if ((cdev->div_mask == 0x3F) && (divisor > 31)) { in vt8500_dclk_round_rate()
178 if (divisor == cdev->div_mask + 1) in vt8500_dclk_set_rate()
182 if ((cdev->div_mask == 0x3F) && (divisor > 31)) { in vt8500_dclk_set_rate()
190 if (divisor > cdev->div_mask) { in vt8500_dclk_set_rate()
271 dev_clk->div_mask = 0x1f; in vtwm_device_clk_init()
273 of_property_read_u32(node, "divisor-mask", &dev_clk->div_mask); in vtwm_device_clk_init()
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| /linux-4.1.27/drivers/clk/tegra/ |
| D | clk-divider.c | 27 #define div_mask(d) ((1 << (d->width)) - 1) macro
29 #define get_max_div(d) div_mask(d)
76 div = reg & div_mask(divider); in clk_frac_div_recalc_rate()
123 val &= ~(div_mask(divider) << divider->shift); in clk_frac_div_set_rate()
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| /linux-4.1.27/drivers/clk/ti/ |
| D | divider.c | 31 #define div_mask(d) ((1 << ((d)->width)) - 1) macro
47 return div_mask(divider); in _get_maxdiv()
49 return 1 << div_mask(divider); in _get_maxdiv()
52 return div_mask(divider) + 1; in _get_maxdiv()
106 val &= div_mask(divider); in ti_clk_divider_recalc_rate()
228 if (value > div_mask(divider)) in ti_clk_divider_set_rate()
229 value = div_mask(divider); in ti_clk_divider_set_rate()
235 val = div_mask(divider) << (divider->shift + 16); in ti_clk_divider_set_rate()
238 val &= ~(div_mask(divider) << divider->shift); in ti_clk_divider_set_rate()
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| /linux-4.1.27/include/linux/ |
| D | sh_clk.h | 59 unsigned int div_mask; member
160 .div_mask = SH_CLK_DIV4_MSK, \
184 .div_mask = SH_CLK_DIV6_MSK, \
196 .div_mask = SH_CLK_DIV6_MSK, \
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| /linux-4.1.27/drivers/sh/clk/ |
| D | cpg.c | 138 idx = (sh_clk_read(clk) >> clk->enable_bit) & clk->div_mask; in sh_clk_div_recalc()
154 value &= ~(clk->div_mask << clk->enable_bit); in sh_clk_div_set_rate()
167 if (clk->div_mask == SH_CLK_DIV6_MSK) { in sh_clk_div_enable()
190 val |= clk->div_mask; in sh_clk_div_disable()
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| /linux-4.1.27/drivers/clk/socfpga/ |
| D | clk.h | 30 #define div_mask(width) ((1 << (width)) - 1) macro
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| D | clk-periph.c | 39 val &= div_mask(socfpgaclk->width); in clk_periclk_recalc_rate()
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| D | clk-gate.c | 113 val &= div_mask(socfpgaclk->width); in socfpga_clk_recalc_rate()
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| /linux-4.1.27/drivers/clk/mmp/ |
| D | clk-mix.c | 29 unsigned int div_mask = (1 << mix->reg_info.width_div) - 1; in _get_maxdiv() local
34 return div_mask; in _get_maxdiv()
36 return 1 << div_mask; in _get_maxdiv()
43 return div_mask + 1; in _get_maxdiv()
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| /linux-4.1.27/drivers/mfd/ |
| D | db8500-prcmu.c | 522 u32 div_mask; member
529 .div_mask = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK,
534 .div_mask = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK,
539 .div_mask = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK,
733 u32 div_mask; in prcmu_config_clkout() local
744 div_mask = PRCM_CLKOCR_CLKODIV0_MASK; in prcmu_config_clkout()
750 div_mask = PRCM_CLKOCR_CLKODIV1_MASK; in prcmu_config_clkout()
762 if (val & div_mask) { in prcmu_config_clkout()
769 if ((val & mask & ~div_mask) != bits) { in prcmu_config_clkout()
1629 div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift)); in dsiescclk_rate()
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