| /linux-4.1.27/drivers/pci/host/ |
| D | pci-imx6.c | 80 static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val) in pcie_phy_poll_ack() argument
87 val = readl(dbi_base + PCIE_PHY_STAT); in pcie_phy_poll_ack()
100 static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr) in pcie_phy_wait_ack() argument
106 writel(val, dbi_base + PCIE_PHY_CTRL); in pcie_phy_wait_ack()
109 writel(val, dbi_base + PCIE_PHY_CTRL); in pcie_phy_wait_ack()
111 ret = pcie_phy_poll_ack(dbi_base, 1); in pcie_phy_wait_ack()
116 writel(val, dbi_base + PCIE_PHY_CTRL); in pcie_phy_wait_ack()
118 ret = pcie_phy_poll_ack(dbi_base, 0); in pcie_phy_wait_ack()
126 static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data) in pcie_phy_read() argument
131 ret = pcie_phy_wait_ack(dbi_base, addr); in pcie_phy_read()
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| D | pcie-spear13xx.c | 166 dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_DEVCTL, 4, &val); in spear13xx_pcie_establish_link()
168 dw_pcie_cfg_write(pp->dbi_base, exp_cap_off + PCI_EXP_DEVCTL, 4, val); in spear13xx_pcie_establish_link()
170 dw_pcie_cfg_write(pp->dbi_base, PCI_VENDOR_ID, 2, 0x104A); in spear13xx_pcie_establish_link()
171 dw_pcie_cfg_write(pp->dbi_base, PCI_DEVICE_ID, 2, 0xCD80); in spear13xx_pcie_establish_link()
178 dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_LNKCAP, 4, in spear13xx_pcie_establish_link()
183 dw_pcie_cfg_write(pp->dbi_base, exp_cap_off + in spear13xx_pcie_establish_link()
187 dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_LNKCTL2, 4, in spear13xx_pcie_establish_link()
192 dw_pcie_cfg_write(pp->dbi_base, exp_cap_off + in spear13xx_pcie_establish_link()
309 struct resource *dbi_base; in spear13xx_pcie_probe() local
343 dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); in spear13xx_pcie_probe()
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| D | pci-keystone-dw.c | 335 writel(0, pp->dbi_base + PCI_BASE_ADDRESS_0); in ks_dw_pcie_setup_rc_app_regs()
336 writel(0, pp->dbi_base + PCI_BASE_ADDRESS_1); in ks_dw_pcie_setup_rc_app_regs()
381 return pp->dbi_base; in ks_pcie_cfg_setup()
434 writel(1, pp->dbi_base + PCI_BASE_ADDRESS_0); in ks_dw_pcie_v3_65_scan_bus()
435 writel(SZ_4K - 1, pp->dbi_base + PCI_BASE_ADDRESS_0); in ks_dw_pcie_v3_65_scan_bus()
443 writel(ks_pcie->app.start, pp->dbi_base + PCI_BASE_ADDRESS_0); in ks_dw_pcie_v3_65_scan_bus()
451 u32 val = readl(pp->dbi_base + DEBUG0); in ks_dw_pcie_link_up()
486 pp->dbi_base = devm_ioremap_resource(pp->dev, res); in ks_dw_pcie_host_init()
487 if (IS_ERR(pp->dbi_base)) in ks_dw_pcie_host_init()
488 return PTR_ERR(pp->dbi_base); in ks_dw_pcie_host_init()
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| D | pci-layerscape.c | 103 pp->dbi_base = pcie->dbi; in ls_add_pcie_port()
119 struct resource *dbi_base; in ls_pcie_probe() local
129 dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); in ls_pcie_probe()
130 pcie->dbi = devm_ioremap_resource(&pdev->dev, dbi_base); in ls_pcie_probe()
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| D | pcie-designware.h | 28 void __iomem *dbi_base; member
60 void __iomem *dbi_base, u32 *val);
62 u32 val, void __iomem *dbi_base);
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| D | pci-keystone.c | 263 pp->dbi_base + PCI_IO_BASE); in ks_pcie_host_init()
266 writew(ks_pcie->device_id, pp->dbi_base + PCI_DEVICE_ID); in ks_pcie_host_init()
269 val = readl(pp->dbi_base + PCIE_CAP_BASE + PCI_EXP_DEVCTL); in ks_pcie_host_init()
273 writel(val, pp->dbi_base + PCIE_CAP_BASE + PCI_EXP_DEVCTL); in ks_pcie_host_init()
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| D | pcie-designware.c | 112 pp->ops->readl_rc(pp, pp->dbi_base + reg, val); in dw_pcie_readl_rc()
114 *val = readl(pp->dbi_base + reg); in dw_pcie_readl_rc()
120 pp->ops->writel_rc(pp, val, pp->dbi_base + reg); in dw_pcie_writel_rc()
122 writel(val, pp->dbi_base + reg); in dw_pcie_writel_rc()
133 ret = dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where, in dw_pcie_rd_own_conf()
147 ret = dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3), where, in dw_pcie_wr_own_conf()
440 if (!pp->dbi_base) { in dw_pcie_host_init()
441 pp->dbi_base = devm_ioremap(pp->dev, pp->cfg.start, in dw_pcie_host_init()
443 if (!pp->dbi_base) { in dw_pcie_host_init()
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| D | pci-exynos.c | 440 void __iomem *dbi_base, u32 *val) in exynos_pcie_readl_rc() argument
443 *val = readl(dbi_base); in exynos_pcie_readl_rc()
448 u32 val, void __iomem *dbi_base) in exynos_pcie_writel_rc() argument
451 writel(val, dbi_base); in exynos_pcie_writel_rc()
461 ret = dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where, size, val); in exynos_pcie_rd_own_conf()
472 ret = dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3), in exynos_pcie_wr_own_conf()
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| D | pci-dra7xx.c | 307 pp->dbi_base = devm_ioremap(dev, res->start, resource_size(res)); in dra7xx_add_pcie_port()
308 if (!pp->dbi_base) in dra7xx_add_pcie_port()
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