80 static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val)  in pcie_phy_poll_ack()  argument
87 		val = readl(dbi_base + PCIE_PHY_STAT);  in pcie_phy_poll_ack()
100 static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr)  in pcie_phy_wait_ack()  argument
106 	writel(val, dbi_base + PCIE_PHY_CTRL);  in pcie_phy_wait_ack()
109 	writel(val, dbi_base + PCIE_PHY_CTRL);  in pcie_phy_wait_ack()
111 	ret = pcie_phy_poll_ack(dbi_base, 1);  in pcie_phy_wait_ack()
116 	writel(val, dbi_base + PCIE_PHY_CTRL);  in pcie_phy_wait_ack()
118 	ret = pcie_phy_poll_ack(dbi_base, 0);  in pcie_phy_wait_ack()
126 static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data)  in pcie_phy_read()  argument
131 	ret = pcie_phy_wait_ack(dbi_base, addr);  in pcie_phy_read()
137 	writel(phy_ctl, dbi_base + PCIE_PHY_CTRL);  in pcie_phy_read()
139 	ret = pcie_phy_poll_ack(dbi_base, 1);  in pcie_phy_read()
143 	val = readl(dbi_base + PCIE_PHY_STAT);  in pcie_phy_read()
147 	writel(0x00, dbi_base + PCIE_PHY_CTRL);  in pcie_phy_read()
149 	ret = pcie_phy_poll_ack(dbi_base, 0);  in pcie_phy_read()
156 static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)  in pcie_phy_write()  argument
163 	ret = pcie_phy_wait_ack(dbi_base, addr);  in pcie_phy_write()
168 	writel(var, dbi_base + PCIE_PHY_CTRL);  in pcie_phy_write()
172 	writel(var, dbi_base + PCIE_PHY_CTRL);  in pcie_phy_write()
174 	ret = pcie_phy_poll_ack(dbi_base, 1);  in pcie_phy_write()
180 	writel(var, dbi_base + PCIE_PHY_CTRL);  in pcie_phy_write()
183 	ret = pcie_phy_poll_ack(dbi_base, 0);  in pcie_phy_write()
189 	writel(var, dbi_base + PCIE_PHY_CTRL);  in pcie_phy_write()
192 	ret = pcie_phy_poll_ack(dbi_base, 1);  in pcie_phy_write()
198 	writel(var, dbi_base + PCIE_PHY_CTRL);  in pcie_phy_write()
201 	ret = pcie_phy_poll_ack(dbi_base, 0);  in pcie_phy_write()
205 	writel(0x0, dbi_base + PCIE_PHY_CTRL);  in pcie_phy_write()
238 		val = readl(pp->dbi_base + PCIE_PL_PFLR);  in imx6_pcie_assert_core_reset()
241 		writel(val, pp->dbi_base + PCIE_PL_PFLR);  in imx6_pcie_assert_core_reset()
347 			readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),  in imx6_pcie_wait_for_link()
348 			readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));  in imx6_pcie_wait_for_link()
373 	tmp = readl(pp->dbi_base + PCIE_RC_LCR);  in imx6_pcie_start_link()
376 	writel(tmp, pp->dbi_base + PCIE_RC_LCR);  in imx6_pcie_start_link()
387 	tmp = readl(pp->dbi_base + PCIE_RC_LCR);  in imx6_pcie_start_link()
390 	writel(tmp, pp->dbi_base + PCIE_RC_LCR);  in imx6_pcie_start_link()
396 	tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);  in imx6_pcie_start_link()
398 	writel(tmp, pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);  in imx6_pcie_start_link()
402 		tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);  in imx6_pcie_start_link()
418 		tmp = readl(pp->dbi_base + 0x80);  in imx6_pcie_start_link()
445 	pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &temp);  in imx6_pcie_reset_phy()
448 	pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, temp);  in imx6_pcie_reset_phy()
452 	pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &temp);  in imx6_pcie_reset_phy()
455 	pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, temp);  in imx6_pcie_reset_phy()
480 		rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1);  in imx6_pcie_link_up()
501 	pcie_phy_read(pp->dbi_base, PCIE_PHY_RX_ASIC_OUT, &rx_valid);  in imx6_pcie_link_up()
502 	debug_r0 = readl(pp->dbi_base + PCIE_PHY_DEBUG_R0);  in imx6_pcie_link_up()
562 	struct resource *dbi_base;  in imx6_pcie_probe()  local
576 	dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);  in imx6_pcie_probe()
577 	pp->dbi_base = devm_ioremap_resource(&pdev->dev, dbi_base);  in imx6_pcie_probe()
578 	if (IS_ERR(pp->dbi_base))  in imx6_pcie_probe()
579 		return PTR_ERR(pp->dbi_base);  in imx6_pcie_probe()