1/*
2 * PCIe host controller driver for Texas Instruments Keystone SoCs
3 *
4 * Copyright (C) 2013-2014 Texas Instruments., Ltd.
5 *		http://www.ti.com
6 *
7 * Author: Murali Karicheri <m-karicheri2@ti.com>
8 * Implementation based on pci-exynos.c and pcie-designware.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/irqchip/chained_irq.h>
16#include <linux/clk.h>
17#include <linux/delay.h>
18#include <linux/irqdomain.h>
19#include <linux/module.h>
20#include <linux/msi.h>
21#include <linux/of_irq.h>
22#include <linux/of.h>
23#include <linux/of_pci.h>
24#include <linux/platform_device.h>
25#include <linux/phy/phy.h>
26#include <linux/resource.h>
27#include <linux/signal.h>
28
29#include "pcie-designware.h"
30#include "pci-keystone.h"
31
32#define DRIVER_NAME	"keystone-pcie"
33
34/* driver specific constants */
35#define MAX_MSI_HOST_IRQS		8
36#define MAX_LEGACY_HOST_IRQS		4
37
38/* DEV_STAT_CTRL */
39#define PCIE_CAP_BASE		0x70
40
41/* PCIE controller device IDs */
42#define PCIE_RC_K2HK		0xb008
43#define PCIE_RC_K2E		0xb009
44#define PCIE_RC_K2L		0xb00a
45
46#define to_keystone_pcie(x)	container_of(x, struct keystone_pcie, pp)
47
48static void quirk_limit_mrrs(struct pci_dev *dev)
49{
50	struct pci_bus *bus = dev->bus;
51	struct pci_dev *bridge = bus->self;
52	static const struct pci_device_id rc_pci_devids[] = {
53		{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2HK),
54		 .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
55		{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2E),
56		 .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
57		{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2L),
58		 .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
59		{ 0, },
60	};
61
62	if (pci_is_root_bus(bus))
63		return;
64
65	/* look for the host bridge */
66	while (!pci_is_root_bus(bus)) {
67		bridge = bus->self;
68		bus = bus->parent;
69	}
70
71	if (bridge) {
72		/*
73		 * Keystone PCI controller has a h/w limitation of
74		 * 256 bytes maximum read request size.  It can't handle
75		 * anything higher than this.  So force this limit on
76		 * all downstream devices.
77		 */
78		if (pci_match_id(rc_pci_devids, bridge)) {
79			if (pcie_get_readrq(dev) > 256) {
80				dev_info(&dev->dev, "limiting MRRS to 256\n");
81				pcie_set_readrq(dev, 256);
82			}
83		}
84	}
85}
86DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, quirk_limit_mrrs);
87
88static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie)
89{
90	struct pcie_port *pp = &ks_pcie->pp;
91	int count = 200;
92
93	dw_pcie_setup_rc(pp);
94
95	if (dw_pcie_link_up(pp)) {
96		dev_err(pp->dev, "Link already up\n");
97		return 0;
98	}
99
100	ks_dw_pcie_initiate_link_train(ks_pcie);
101	/* check if the link is up or not */
102	while (!dw_pcie_link_up(pp)) {
103		usleep_range(100, 1000);
104		if (--count) {
105			ks_dw_pcie_initiate_link_train(ks_pcie);
106			continue;
107		}
108		dev_err(pp->dev, "phy link never came up\n");
109		return -EINVAL;
110	}
111
112	return 0;
113}
114
115static void ks_pcie_msi_irq_handler(unsigned int irq, struct irq_desc *desc)
116{
117	struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc);
118	u32 offset = irq - ks_pcie->msi_host_irqs[0];
119	struct pcie_port *pp = &ks_pcie->pp;
120	struct irq_chip *chip = irq_desc_get_chip(desc);
121
122	dev_dbg(pp->dev, "%s, irq %d\n", __func__, irq);
123
124	/*
125	 * The chained irq handler installation would have replaced normal
126	 * interrupt driver handler so we need to take care of mask/unmask and
127	 * ack operation.
128	 */
129	chained_irq_enter(chip, desc);
130	ks_dw_pcie_handle_msi_irq(ks_pcie, offset);
131	chained_irq_exit(chip, desc);
132}
133
134/**
135 * ks_pcie_legacy_irq_handler() - Handle legacy interrupt
136 * @irq: IRQ line for legacy interrupts
137 * @desc: Pointer to irq descriptor
138 *
139 * Traverse through pending legacy interrupts and invoke handler for each. Also
140 * takes care of interrupt controller level mask/ack operation.
141 */
142static void ks_pcie_legacy_irq_handler(unsigned int irq, struct irq_desc *desc)
143{
144	struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc);
145	struct pcie_port *pp = &ks_pcie->pp;
146	u32 irq_offset = irq - ks_pcie->legacy_host_irqs[0];
147	struct irq_chip *chip = irq_desc_get_chip(desc);
148
149	dev_dbg(pp->dev, ": Handling legacy irq %d\n", irq);
150
151	/*
152	 * The chained irq handler installation would have replaced normal
153	 * interrupt driver handler so we need to take care of mask/unmask and
154	 * ack operation.
155	 */
156	chained_irq_enter(chip, desc);
157	ks_dw_pcie_handle_legacy_irq(ks_pcie, irq_offset);
158	chained_irq_exit(chip, desc);
159}
160
161static int ks_pcie_get_irq_controller_info(struct keystone_pcie *ks_pcie,
162					   char *controller, int *num_irqs)
163{
164	int temp, max_host_irqs, legacy = 1, *host_irqs, ret = -EINVAL;
165	struct device *dev = ks_pcie->pp.dev;
166	struct device_node *np_pcie = dev->of_node, **np_temp;
167
168	if (!strcmp(controller, "msi-interrupt-controller"))
169		legacy = 0;
170
171	if (legacy) {
172		np_temp = &ks_pcie->legacy_intc_np;
173		max_host_irqs = MAX_LEGACY_HOST_IRQS;
174		host_irqs = &ks_pcie->legacy_host_irqs[0];
175	} else {
176		np_temp = &ks_pcie->msi_intc_np;
177		max_host_irqs = MAX_MSI_HOST_IRQS;
178		host_irqs =  &ks_pcie->msi_host_irqs[0];
179	}
180
181	/* interrupt controller is in a child node */
182	*np_temp = of_find_node_by_name(np_pcie, controller);
183	if (!(*np_temp)) {
184		dev_err(dev, "Node for %s is absent\n", controller);
185		goto out;
186	}
187	temp = of_irq_count(*np_temp);
188	if (!temp)
189		goto out;
190	if (temp > max_host_irqs)
191		dev_warn(dev, "Too many %s interrupts defined %u\n",
192			(legacy ? "legacy" : "MSI"), temp);
193
194	/*
195	 * support upto max_host_irqs. In dt from index 0 to 3 (legacy) or 0 to
196	 * 7 (MSI)
197	 */
198	for (temp = 0; temp < max_host_irqs; temp++) {
199		host_irqs[temp] = irq_of_parse_and_map(*np_temp, temp);
200		if (!host_irqs[temp])
201			break;
202	}
203	if (temp) {
204		*num_irqs = temp;
205		ret = 0;
206	}
207out:
208	return ret;
209}
210
211static void ks_pcie_setup_interrupts(struct keystone_pcie *ks_pcie)
212{
213	int i;
214
215	/* Legacy IRQ */
216	for (i = 0; i < ks_pcie->num_legacy_host_irqs; i++) {
217		irq_set_handler_data(ks_pcie->legacy_host_irqs[i], ks_pcie);
218		irq_set_chained_handler(ks_pcie->legacy_host_irqs[i],
219					ks_pcie_legacy_irq_handler);
220	}
221	ks_dw_pcie_enable_legacy_irqs(ks_pcie);
222
223	/* MSI IRQ */
224	if (IS_ENABLED(CONFIG_PCI_MSI)) {
225		for (i = 0; i < ks_pcie->num_msi_host_irqs; i++) {
226			irq_set_chained_handler(ks_pcie->msi_host_irqs[i],
227						ks_pcie_msi_irq_handler);
228			irq_set_handler_data(ks_pcie->msi_host_irqs[i],
229					     ks_pcie);
230		}
231	}
232}
233
234/*
235 * When a PCI device does not exist during config cycles, keystone host gets a
236 * bus error instead of returning 0xffffffff. This handler always returns 0
237 * for this kind of faults.
238 */
239static int keystone_pcie_fault(unsigned long addr, unsigned int fsr,
240				struct pt_regs *regs)
241{
242	unsigned long instr = *(unsigned long *) instruction_pointer(regs);
243
244	if ((instr & 0x0e100090) == 0x00100090) {
245		int reg = (instr >> 12) & 15;
246
247		regs->uregs[reg] = -1;
248		regs->ARM_pc += 4;
249	}
250
251	return 0;
252}
253
254static void __init ks_pcie_host_init(struct pcie_port *pp)
255{
256	struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
257	u32 val;
258
259	ks_pcie_establish_link(ks_pcie);
260	ks_dw_pcie_setup_rc_app_regs(ks_pcie);
261	ks_pcie_setup_interrupts(ks_pcie);
262	writew(PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8),
263			pp->dbi_base + PCI_IO_BASE);
264
265	/* update the Vendor ID */
266	writew(ks_pcie->device_id, pp->dbi_base + PCI_DEVICE_ID);
267
268	/* update the DEV_STAT_CTRL to publish right mrrs */
269	val = readl(pp->dbi_base + PCIE_CAP_BASE + PCI_EXP_DEVCTL);
270	val &= ~PCI_EXP_DEVCTL_READRQ;
271	/* set the mrrs to 256 bytes */
272	val |= BIT(12);
273	writel(val, pp->dbi_base + PCIE_CAP_BASE + PCI_EXP_DEVCTL);
274
275	/*
276	 * PCIe access errors that result into OCP errors are caught by ARM as
277	 * "External aborts"
278	 */
279	hook_fault_code(17, keystone_pcie_fault, SIGBUS, 0,
280			"Asynchronous external abort");
281}
282
283static struct pcie_host_ops keystone_pcie_host_ops = {
284	.rd_other_conf = ks_dw_pcie_rd_other_conf,
285	.wr_other_conf = ks_dw_pcie_wr_other_conf,
286	.link_up = ks_dw_pcie_link_up,
287	.host_init = ks_pcie_host_init,
288	.msi_set_irq = ks_dw_pcie_msi_set_irq,
289	.msi_clear_irq = ks_dw_pcie_msi_clear_irq,
290	.get_msi_addr = ks_dw_pcie_get_msi_addr,
291	.msi_host_init = ks_dw_pcie_msi_host_init,
292	.scan_bus = ks_dw_pcie_v3_65_scan_bus,
293};
294
295static int __init ks_add_pcie_port(struct keystone_pcie *ks_pcie,
296			 struct platform_device *pdev)
297{
298	struct pcie_port *pp = &ks_pcie->pp;
299	int ret;
300
301	ret = ks_pcie_get_irq_controller_info(ks_pcie,
302					"legacy-interrupt-controller",
303					&ks_pcie->num_legacy_host_irqs);
304	if (ret)
305		return ret;
306
307	if (IS_ENABLED(CONFIG_PCI_MSI)) {
308		ret = ks_pcie_get_irq_controller_info(ks_pcie,
309						"msi-interrupt-controller",
310						&ks_pcie->num_msi_host_irqs);
311		if (ret)
312			return ret;
313	}
314
315	pp->root_bus_nr = -1;
316	pp->ops = &keystone_pcie_host_ops;
317	ret = ks_dw_pcie_host_init(ks_pcie, ks_pcie->msi_intc_np);
318	if (ret) {
319		dev_err(&pdev->dev, "failed to initialize host\n");
320		return ret;
321	}
322
323	return ret;
324}
325
326static const struct of_device_id ks_pcie_of_match[] = {
327	{
328		.type = "pci",
329		.compatible = "ti,keystone-pcie",
330	},
331	{ },
332};
333MODULE_DEVICE_TABLE(of, ks_pcie_of_match);
334
335static int __exit ks_pcie_remove(struct platform_device *pdev)
336{
337	struct keystone_pcie *ks_pcie = platform_get_drvdata(pdev);
338
339	clk_disable_unprepare(ks_pcie->clk);
340
341	return 0;
342}
343
344static int __init ks_pcie_probe(struct platform_device *pdev)
345{
346	struct device *dev = &pdev->dev;
347	struct keystone_pcie *ks_pcie;
348	struct pcie_port *pp;
349	struct resource *res;
350	void __iomem *reg_p;
351	struct phy *phy;
352	int ret = 0;
353
354	ks_pcie = devm_kzalloc(&pdev->dev, sizeof(*ks_pcie),
355				GFP_KERNEL);
356	if (!ks_pcie)
357		return -ENOMEM;
358
359	pp = &ks_pcie->pp;
360
361	/* initialize SerDes Phy if present */
362	phy = devm_phy_get(dev, "pcie-phy");
363	if (!IS_ERR_OR_NULL(phy)) {
364		ret = phy_init(phy);
365		if (ret < 0)
366			return ret;
367	}
368
369	/* index 2 is to read PCI DEVICE_ID */
370	res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
371	reg_p = devm_ioremap_resource(dev, res);
372	if (IS_ERR(reg_p))
373		return PTR_ERR(reg_p);
374	ks_pcie->device_id = readl(reg_p) >> 16;
375	devm_iounmap(dev, reg_p);
376	devm_release_mem_region(dev, res->start, resource_size(res));
377
378	pp->dev = dev;
379	platform_set_drvdata(pdev, ks_pcie);
380	ks_pcie->clk = devm_clk_get(dev, "pcie");
381	if (IS_ERR(ks_pcie->clk)) {
382		dev_err(dev, "Failed to get pcie rc clock\n");
383		return PTR_ERR(ks_pcie->clk);
384	}
385	ret = clk_prepare_enable(ks_pcie->clk);
386	if (ret)
387		return ret;
388
389	ret = ks_add_pcie_port(ks_pcie, pdev);
390	if (ret < 0)
391		goto fail_clk;
392
393	return 0;
394fail_clk:
395	clk_disable_unprepare(ks_pcie->clk);
396
397	return ret;
398}
399
400static struct platform_driver ks_pcie_driver __refdata = {
401	.probe  = ks_pcie_probe,
402	.remove = __exit_p(ks_pcie_remove),
403	.driver = {
404		.name	= "keystone-pcie",
405		.of_match_table = of_match_ptr(ks_pcie_of_match),
406	},
407};
408
409module_platform_driver(ks_pcie_driver);
410
411MODULE_AUTHOR("Murali Karicheri <m-karicheri2@ti.com>");
412MODULE_DESCRIPTION("Keystone PCIe host controller driver");
413MODULE_LICENSE("GPL v2");
414