| /linux-4.1.27/drivers/pinctrl/qcom/ |
| D | pinctrl-msm.c | 160 val = readl(pctrl->regs + g->ctl_reg); in msm_pinmux_set_mux()
163 writel(val, pctrl->regs + g->ctl_reg); in msm_pinmux_set_mux()
236 val = readl(pctrl->regs + g->ctl_reg); in msm_config_group_get()
357 val = readl(pctrl->regs + g->ctl_reg); in msm_config_group_set()
360 writel(val, pctrl->regs + g->ctl_reg); in msm_config_group_set()
391 val = readl(pctrl->regs + g->ctl_reg); in msm_gpio_direction_input()
393 writel(val, pctrl->regs + g->ctl_reg); in msm_gpio_direction_input()
418 val = readl(pctrl->regs + g->ctl_reg); in msm_gpio_direction_output()
420 writel(val, pctrl->regs + g->ctl_reg); in msm_gpio_direction_output()
487 u32 ctl_reg; in msm_gpio_dbg_show_one() local
[all …]
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| D | pinctrl-msm.h | 73 u32 ctl_reg; member
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| D | pinctrl-ipq8064.c | 199 .ctl_reg = 0x1000 + 0x10 * id, \
226 .ctl_reg = ctl, \
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| D | pinctrl-apq8064.c | 246 .ctl_reg = 0x1000 + 0x10 * id, \
273 .ctl_reg = ctl, \
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| D | pinctrl-msm8916.c | 322 .ctl_reg = 0x1000 * id, \
348 .ctl_reg = ctl, \
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| D | pinctrl-apq8084.c | 359 .ctl_reg = 0x1000 + 0x10 * id, \
386 .ctl_reg = ctl, \
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| D | pinctrl-msm8x74.c | 355 .ctl_reg = 0x1000 + 0x10 * id, \
381 .ctl_reg = ctl, \
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| D | pinctrl-msm8960.c | 372 .ctl_reg = 0x1000 + 0x10 * id, \
399 .ctl_reg = ctl, \
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| /linux-4.1.27/drivers/spi/ |
| D | spi-bfin-sport.c | 101 u16 ctl_reg; member
258 bfin_write(&drv_data->regs->tcr1, chip->ctl_reg); in bfin_sport_spi_restore_state()
262 bfin_write(&drv_data->regs->rcr1, chip->ctl_reg & ~(ITCLK | ITFS)); in bfin_sport_spi_restore_state()
524 drv_data->cur_chip->ctl_reg); in bfin_sport_spi_pump_messages()
592 if (chip_info->ctl_reg || chip_info->enable_dma) { in bfin_sport_spi_setup()
607 chip->ctl_reg &= ~TCKFE; in bfin_sport_spi_setup()
609 chip->ctl_reg |= TCKFE; in bfin_sport_spi_setup()
612 chip->ctl_reg |= TLSBIT; in bfin_sport_spi_setup()
614 chip->ctl_reg &= ~TLSBIT; in bfin_sport_spi_setup()
617 chip->ctl_reg |= ITCLK | ITFS | TFSR | LATFS | LTFS; in bfin_sport_spi_setup()
[all …]
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| D | spi-bfin5xx.c | 113 u16 ctl_reg; member
214 bfin_write(&drv_data->regs->ctl, chip->ctl_reg); in bfin_spi_restore_state()
916 drv_data->cur_chip->ctl_reg); in bfin_spi_pump_messages()
1012 if (chip_info->ctl_reg & ~bfin_ctl_reg) { in bfin_spi_setup()
1019 chip->ctl_reg = chip_info->ctl_reg; in bfin_spi_setup()
1025 chip->ctl_reg &= bfin_ctl_reg; in bfin_spi_setup()
1030 chip->ctl_reg |= BIT_CTL_CPOL; in bfin_spi_setup()
1032 chip->ctl_reg |= BIT_CTL_CPHA; in bfin_spi_setup()
1034 chip->ctl_reg |= BIT_CTL_LSBF; in bfin_spi_setup()
1036 chip->ctl_reg |= BIT_CTL_MASTER; in bfin_spi_setup()
[all …]
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| D | spi-adi-v3.c | 656 u32 ctl_reg = SPI_CTL_ODM | SPI_CTL_PSSE; in adi_spi_setup() local
667 if (chip_info->control & ~ctl_reg) { in adi_spi_setup()
700 chip->control &= ctl_reg; in adi_spi_setup()
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| /linux-4.1.27/drivers/scsi/csiostor/ |
| D | csio_mb.c | 1158 uint32_t ctl_reg = PF_REG(hw->pfn, CIM_PF_MAILBOX_CTRL_A); in csio_mb_debug_cmd_handler() local
1170 MBOWNER_V(CSIO_MBOWNER_FW), ctl_reg); in csio_mb_debug_cmd_handler()
1172 csio_rd_reg32(hw, ctl_reg); in csio_mb_debug_cmd_handler()
1192 uint32_t ctl_reg = PF_REG(hw->pfn, CIM_PF_MAILBOX_CTRL_A); in csio_mb_issue() local
1229 owner = MBOWNER_G(csio_rd_reg32(hw, ctl_reg)); in csio_mb_issue()
1234 owner = MBOWNER_G(csio_rd_reg32(hw, ctl_reg)); in csio_mb_issue()
1277 MBOWNER_V(CSIO_MBOWNER_FW), ctl_reg); in csio_mb_issue()
1280 ctl_reg); in csio_mb_issue()
1283 csio_rd_reg32(hw, ctl_reg); in csio_mb_issue()
1298 ctl = csio_rd_reg32(hw, ctl_reg); in csio_mb_issue()
[all …]
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| /linux-4.1.27/drivers/gpu/drm/i915/ |
| D | intel_lvds.c | 218 u32 ctl_reg, stat_reg; in intel_enable_lvds() local
221 ctl_reg = PCH_PP_CONTROL; in intel_enable_lvds()
224 ctl_reg = PP_CONTROL; in intel_enable_lvds()
230 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON); in intel_enable_lvds()
245 u32 ctl_reg, stat_reg; in intel_disable_lvds() local
248 ctl_reg = PCH_PP_CONTROL; in intel_disable_lvds()
251 ctl_reg = PP_CONTROL; in intel_disable_lvds()
257 I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON); in intel_disable_lvds()
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| D | intel_psr.c | 82 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config->cpu_transcoder); in intel_psr_write_vsc() local
90 I915_WRITE(ctl_reg, 0); in intel_psr_write_vsc()
91 POSTING_READ(ctl_reg); in intel_psr_write_vsc()
100 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW); in intel_psr_write_vsc()
101 POSTING_READ(ctl_reg); in intel_psr_write_vsc()
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| D | intel_hdmi.c | 341 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); in hsw_write_infoframe() local
344 u32 val = I915_READ(ctl_reg); in hsw_write_infoframe()
353 I915_WRITE(ctl_reg, val); in hsw_write_infoframe()
366 I915_WRITE(ctl_reg, val); in hsw_write_infoframe()
367 POSTING_READ(ctl_reg); in hsw_write_infoframe()
375 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); in hsw_infoframe_enabled() local
376 u32 val = I915_READ(ctl_reg); in hsw_infoframe_enabled()
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| /linux-4.1.27/drivers/misc/ |
| D | phantom.c | 61 u32 ctl_reg; member
120 r.value |= dev->ctl_reg & PHN_CTL_AMP; in phantom_ioctl()
121 dev->ctl_reg = r.value; in phantom_ioctl()
310 dev->ctl_reg ^= PHN_CTL_AMP; in phantom_isr()
311 iowrite32(dev->ctl_reg, dev->iaddr + PHN_CONTROL); in phantom_isr()
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| /linux-4.1.27/arch/blackfin/include/asm/ |
| D | bfin5xx_spi.h | 78 u16 ctl_reg; member
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| /linux-4.1.27/drivers/net/ethernet/ |
| D | dnet.c | 178 u32 mode_reg, ctl_reg; in dnet_handle_link_change() local
185 ctl_reg = dnet_readw_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG); in dnet_handle_link_change()
190 ctl_reg &= in dnet_handle_link_change()
193 ctl_reg |= in dnet_handle_link_change()
238 dnet_writew_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG, ctl_reg); in dnet_handle_link_change()
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| /linux-4.1.27/drivers/scsi/lpfc/ |
| D | lpfc_debugfs.c | 3112 void __iomem *ctl_reg; in lpfc_idiag_ctlacc_write() local
3148 ctl_reg = phba->sli4_hba.conf_regs_memmap_p + in lpfc_idiag_ctlacc_write()
3152 ctl_reg = phba->sli4_hba.conf_regs_memmap_p + in lpfc_idiag_ctlacc_write()
3156 ctl_reg = phba->sli4_hba.conf_regs_memmap_p + in lpfc_idiag_ctlacc_write()
3160 ctl_reg = phba->sli4_hba.conf_regs_memmap_p + in lpfc_idiag_ctlacc_write()
3164 ctl_reg = phba->sli4_hba.conf_regs_memmap_p + in lpfc_idiag_ctlacc_write()
3168 ctl_reg = phba->sli4_hba.conf_regs_memmap_p + in lpfc_idiag_ctlacc_write()
3178 reg_val = readl(ctl_reg); in lpfc_idiag_ctlacc_write()
3182 reg_val = readl(ctl_reg); in lpfc_idiag_ctlacc_write()
3185 writel(reg_val, ctl_reg); in lpfc_idiag_ctlacc_write()
[all …]
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| /linux-4.1.27/sound/soc/davinci/ |
| D | davinci-mcasp.c | 144 static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val) in mcasp_set_ctl_reg() argument
148 mcasp_set_bits(mcasp, ctl_reg, val); in mcasp_set_ctl_reg()
153 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val) in mcasp_set_ctl_reg()
157 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val)) in mcasp_set_ctl_reg()
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| /linux-4.1.27/drivers/net/ethernet/chelsio/cxgb4/ |
| D | t4_hw.c | 269 u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL_A); in t4_wr_mbox_meat() local
281 v = MBOWNER_G(t4_read_reg(adap, ctl_reg)); in t4_wr_mbox_meat()
283 v = MBOWNER_G(t4_read_reg(adap, ctl_reg)); in t4_wr_mbox_meat()
291 t4_write_reg(adap, ctl_reg, MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW)); in t4_wr_mbox_meat()
292 t4_read_reg(adap, ctl_reg); /* flush write */ in t4_wr_mbox_meat()
306 v = t4_read_reg(adap, ctl_reg); in t4_wr_mbox_meat()
309 t4_write_reg(adap, ctl_reg, 0); in t4_wr_mbox_meat()
323 t4_write_reg(adap, ctl_reg, 0); in t4_wr_mbox_meat()
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