1/*
2 * Blackfin On-Chip SPI Driver
3 *
4 * Copyright 2004-2008 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef _SPI_CHANNEL_H_
10#define _SPI_CHANNEL_H_
11
12#define MIN_SPI_BAUD_VAL	2
13
14#define BIT_CTL_ENABLE      0x4000
15#define BIT_CTL_OPENDRAIN   0x2000
16#define BIT_CTL_MASTER      0x1000
17#define BIT_CTL_CPOL        0x0800
18#define BIT_CTL_CPHA        0x0400
19#define BIT_CTL_LSBF        0x0200
20#define BIT_CTL_WORDSIZE    0x0100
21#define BIT_CTL_EMISO       0x0020
22#define BIT_CTL_PSSE        0x0010
23#define BIT_CTL_GM          0x0008
24#define BIT_CTL_SZ          0x0004
25#define BIT_CTL_RXMOD       0x0000
26#define BIT_CTL_TXMOD       0x0001
27#define BIT_CTL_TIMOD_DMA_TX 0x0003
28#define BIT_CTL_TIMOD_DMA_RX 0x0002
29#define BIT_CTL_SENDOPT     0x0004
30#define BIT_CTL_TIMOD       0x0003
31
32#define BIT_STAT_SPIF       0x0001
33#define BIT_STAT_MODF       0x0002
34#define BIT_STAT_TXE        0x0004
35#define BIT_STAT_TXS        0x0008
36#define BIT_STAT_RBSY       0x0010
37#define BIT_STAT_RXS        0x0020
38#define BIT_STAT_TXCOL      0x0040
39#define BIT_STAT_CLR        0xFFFF
40
41#define BIT_STU_SENDOVER    0x0001
42#define BIT_STU_RECVFULL    0x0020
43
44/*
45 * All Blackfin system MMRs are padded to 32bits even if the register
46 * itself is only 16bits.  So use a helper macro to streamline this.
47 */
48#define __BFP(m) u16 m; u16 __pad_##m
49
50/*
51 * bfin spi registers layout
52 */
53struct bfin_spi_regs {
54	__BFP(ctl);
55	__BFP(flg);
56	__BFP(stat);
57	__BFP(tdbr);
58	__BFP(rdbr);
59	__BFP(baud);
60	__BFP(shadow);
61};
62
63#undef __BFP
64
65#define MAX_CTRL_CS          8  /* cs in spi controller */
66
67/* device.platform_data for SSP controller devices */
68struct bfin5xx_spi_master {
69	u16 num_chipselect;
70	u8 enable_dma;
71	u16 pin_req[7];
72};
73
74/* spi_board_info.controller_data for SPI slave devices,
75 * copied to spi_device.platform_data ... mostly for dma tuning
76 */
77struct bfin5xx_spi_chip {
78	u16 ctl_reg;
79	u8 enable_dma;
80	u16 cs_chg_udelay; /* Some devices require 16-bit delays */
81	/* Value to send if no TX value is supplied, usually 0x0 or 0xFFFF */
82	u16 idle_tx_val;
83	u8 pio_interrupt; /* Enable spi data irq */
84};
85
86#endif /* _SPI_CHANNEL_H_ */
87