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Searched refs:control_reg (Results 1 – 31 of 31) sorted by relevance

/linux-4.1.27/sound/pci/echoaudio/
Dechoaudio_3g.c143 static u32 set_spdif_bits(struct echoaudio *chip, u32 control_reg, u32 rate) in set_spdif_bits() argument
145 control_reg &= E3G_SPDIF_FORMAT_CLEAR_MASK; in set_spdif_bits()
149 control_reg |= E3G_SPDIF_SAMPLE_RATE0 | E3G_SPDIF_SAMPLE_RATE1; in set_spdif_bits()
153 control_reg |= E3G_SPDIF_SAMPLE_RATE0; in set_spdif_bits()
156 control_reg |= E3G_SPDIF_SAMPLE_RATE1; in set_spdif_bits()
161 control_reg |= E3G_SPDIF_PRO_MODE; in set_spdif_bits()
164 control_reg |= E3G_SPDIF_NOT_AUDIO; in set_spdif_bits()
166 control_reg |= E3G_SPDIF_24_BIT | E3G_SPDIF_TWO_CHANNEL | in set_spdif_bits()
169 return control_reg; in set_spdif_bits()
177 u32 control_reg; in set_professional_spdif() local
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Dgina24_dsp.c124 u32 control_reg; in load_asic() local
154 control_reg = GML_CONVERTER_ENABLE | GML_48KHZ; in load_asic()
155 err = write_control_reg(chip, control_reg, TRUE); in load_asic()
164 u32 control_reg, clock; in set_sample_rate() local
182 control_reg = le32_to_cpu(chip->comm_page->control_register); in set_sample_rate()
183 control_reg &= GML_CLOCK_CLEAR_MASK & GML_SPDIF_RATE_CLEAR_MASK; in set_sample_rate()
198 if (control_reg & GML_SPDIF_PRO_MODE) in set_sample_rate()
223 control_reg |= clock; in set_sample_rate()
229 return write_control_reg(chip, control_reg, FALSE); in set_sample_rate()
236 u32 control_reg, clocks_from_dsp; in set_input_clock() local
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Dmona_dsp.c117 u32 control_reg; in load_asic() local
150 control_reg = GML_CONVERTER_ENABLE | GML_48KHZ; in load_asic()
151 err = write_control_reg(chip, control_reg, TRUE); in load_asic()
198 u32 control_reg, clock; in set_sample_rate() local
244 control_reg = le32_to_cpu(chip->comm_page->control_register); in set_sample_rate()
245 control_reg &= GML_CLOCK_CLEAR_MASK; in set_sample_rate()
246 control_reg &= GML_SPDIF_RATE_CLEAR_MASK; in set_sample_rate()
261 if (control_reg & GML_SPDIF_PRO_MODE) in set_sample_rate()
286 control_reg |= clock; in set_sample_rate()
293 return write_control_reg(chip, control_reg, force_write); in set_sample_rate()
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Dlayla24_dsp.c159 u32 control_reg, clock, base_rate; in set_sample_rate() local
176 control_reg = le32_to_cpu(chip->comm_page->control_register); in set_sample_rate()
177 control_reg &= GML_CLOCK_CLEAR_MASK & GML_SPDIF_RATE_CLEAR_MASK; in set_sample_rate()
194 if (control_reg & GML_SPDIF_PRO_MODE) in set_sample_rate()
219 control_reg |= GML_DOUBLE_SPEED_MODE; in set_sample_rate()
237 control_reg |= clock; in set_sample_rate()
242 "set_sample_rate: %d clock %d\n", rate, control_reg); in set_sample_rate()
244 return write_control_reg(chip, control_reg, FALSE); in set_sample_rate()
251 u32 control_reg, clocks_from_dsp; in set_input_clock() local
254 control_reg = le32_to_cpu(chip->comm_page->control_register) & in set_input_clock()
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Dechoaudio_gml.c156 u32 control_reg; in set_professional_spdif() local
160 control_reg = le32_to_cpu(chip->comm_page->control_register); in set_professional_spdif()
161 control_reg &= GML_SPDIF_FORMAT_CLEAR_MASK; in set_professional_spdif()
164 control_reg |= GML_SPDIF_TWO_CHANNEL | GML_SPDIF_24_BIT | in set_professional_spdif()
168 control_reg |= GML_SPDIF_PRO_MODE; in set_professional_spdif()
172 control_reg |= GML_SPDIF_SAMPLE_RATE0 | in set_professional_spdif()
176 control_reg |= GML_SPDIF_SAMPLE_RATE0; in set_professional_spdif()
179 control_reg |= GML_SPDIF_SAMPLE_RATE1; in set_professional_spdif()
186 control_reg |= GML_SPDIF_SAMPLE_RATE0 | in set_professional_spdif()
190 control_reg |= GML_SPDIF_SAMPLE_RATE1; in set_professional_spdif()
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Dindigodj_dsp.c92 u32 control_reg; in set_sample_rate() local
96 control_reg = MIA_96000; in set_sample_rate()
99 control_reg = MIA_88200; in set_sample_rate()
102 control_reg = MIA_48000; in set_sample_rate()
105 control_reg = MIA_44100; in set_sample_rate()
108 control_reg = MIA_32000; in set_sample_rate()
117 if (control_reg != le32_to_cpu(chip->comm_page->control_register)) { in set_sample_rate()
122 chip->comm_page->control_register = cpu_to_le32(control_reg); in set_sample_rate()
Dindigo_dsp.c92 u32 control_reg; in set_sample_rate() local
96 control_reg = MIA_96000; in set_sample_rate()
99 control_reg = MIA_88200; in set_sample_rate()
102 control_reg = MIA_48000; in set_sample_rate()
105 control_reg = MIA_44100; in set_sample_rate()
108 control_reg = MIA_32000; in set_sample_rate()
117 if (control_reg != le32_to_cpu(chip->comm_page->control_register)) { in set_sample_rate()
122 chip->comm_page->control_register = cpu_to_le32(control_reg); in set_sample_rate()
Dmia_dsp.c109 u32 control_reg; in set_sample_rate() local
113 control_reg = MIA_96000; in set_sample_rate()
116 control_reg = MIA_88200; in set_sample_rate()
119 control_reg = MIA_48000; in set_sample_rate()
122 control_reg = MIA_44100; in set_sample_rate()
125 control_reg = MIA_32000; in set_sample_rate()
135 control_reg |= MIA_SPDIF; in set_sample_rate()
138 if (control_reg != le32_to_cpu(chip->comm_page->control_register)) { in set_sample_rate()
143 chip->comm_page->control_register = cpu_to_le32(control_reg); in set_sample_rate()
Dindigo_express_dsp.c31 u32 clock, control_reg, old_control_reg; in set_sample_rate() local
37 control_reg = old_control_reg & ~INDIGO_EXPRESS_CLOCK_MASK; in set_sample_rate()
62 control_reg |= clock; in set_sample_rate()
63 if (control_reg != old_control_reg) { in set_sample_rate()
66 chip->comm_page->control_register = cpu_to_le32(control_reg); in set_sample_rate()
Decho3g_dsp.c120 u32 control_reg = le32_to_cpu(chip->comm_page->control_register); in set_phantom_power() local
123 control_reg |= E3G_PHANTOM_POWER; in set_phantom_power()
125 control_reg &= ~E3G_PHANTOM_POWER; in set_phantom_power()
128 return write_control_reg(chip, control_reg, in set_phantom_power()
/linux-4.1.27/drivers/scsi/pcmcia/
Dnsp_message.c15 unsigned char data_reg, control_reg; in nsp_message_in() local
33 control_reg = nsp_index_read(base, SCSIBUSCTRL); in nsp_message_in()
34 control_reg |= SCSI_ACK; in nsp_message_in()
35 nsp_index_write(base, SCSIBUSCTRL, control_reg); in nsp_message_in()
41 control_reg = nsp_index_read(base, SCSIBUSCTRL); in nsp_message_in()
42 control_reg &= ~SCSI_ACK; in nsp_message_in()
43 nsp_index_write(base, SCSIBUSCTRL, control_reg); in nsp_message_in()
/linux-4.1.27/drivers/clk/
Dclk-palmas.c36 unsigned int control_reg; member
69 cinfo->clk_desc->control_reg, in palmas_clks_prepare()
74 cinfo->clk_desc->control_reg, ret); in palmas_clks_prepare()
94 cinfo->clk_desc->control_reg, in palmas_clks_unprepare()
98 cinfo->clk_desc->control_reg, ret); in palmas_clks_unprepare()
111 cinfo->clk_desc->control_reg, &val); in palmas_clks_is_prepared()
114 cinfo->clk_desc->control_reg, ret); in palmas_clks_is_prepared()
140 .control_reg = PALMAS_CLK32KG_CTRL,
156 .control_reg = PALMAS_CLK32KGAUDIO_CTRL,
213 cinfo->clk_desc->control_reg, in palmas_clks_init_configure()
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/linux-4.1.27/drivers/clk/ti/
Dapll.c60 v = ti_clk_ll_ops->clk_readl(ad->control_reg); in dra7_apll_enable()
63 ti_clk_ll_ops->clk_writel(v, ad->control_reg); in dra7_apll_enable()
99 v = ti_clk_ll_ops->clk_readl(ad->control_reg); in dra7_apll_disable()
102 ti_clk_ll_ops->clk_writel(v, ad->control_reg); in dra7_apll_disable()
113 v = ti_clk_ll_ops->clk_readl(ad->control_reg); in dra7_apll_is_enabled()
203 ad->control_reg = ti_clk_get_reg_addr(node, 0); in of_dra7_apll_setup()
206 if (IS_ERR(ad->control_reg) || IS_ERR(ad->idlest_reg)) in of_dra7_apll_setup()
232 v = ti_clk_ll_ops->clk_readl(ad->control_reg); in omap2_apll_is_enabled()
258 v = ti_clk_ll_ops->clk_readl(ad->control_reg); in omap2_apll_enable()
261 ti_clk_ll_ops->clk_writel(v, ad->control_reg); in omap2_apll_enable()
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Ddpll.c233 dd->control_reg = _get_reg(dpll->module, dpll->control_reg); in ti_clk_register_dpll()
378 dd->control_reg = ti_clk_get_reg_addr(node, 0); in of_ti_dpll_setup()
399 if (IS_ERR(dd->control_reg) || IS_ERR(dd->mult_div1_reg)) in of_ti_dpll_setup()
Dclock.h133 u16 control_reg; member
Dclk-3xxx-legacy.c127 .control_reg = 0xd00,
298 .control_reg = 0xd00,
500 .control_reg = 0xd04,
1265 .control_reg = 0x904,
2149 .control_reg = 0x4,
2510 .control_reg = 0xd00,
/linux-4.1.27/drivers/tty/serial/
Dpmac_zilog.h54 volatile u8 __iomem *control_reg; member
87 writeb(reg, port->control_reg); in read_zsreg()
88 return readb(port->control_reg); in read_zsreg()
94 writeb(reg, port->control_reg); in write_zsreg()
95 writeb(value, port->control_reg); in write_zsreg()
110 (void)readb(port->control_reg); in zssync()
Dpmac_zilog.c1431 uap->control_reg = uap->port.membase; in pmz_init_port()
1432 uap->data_reg = uap->control_reg + 0x10; in pmz_init_port()
1550 iounmap(uap->control_reg); in pmz_dispose_port()
1736 uap->control_reg = uap->port.membase; in pmz_init_port()
1737 uap->data_reg = uap->control_reg + 4; in pmz_init_port()
/linux-4.1.27/arch/mips/cavium-octeon/executive/
Dcvmx-helper-sgmii.c143 union cvmx_pcsx_mrx_control_reg control_reg; in __cvmx_helper_sgmii_hardware_init_link() local
153 control_reg.u64 = in __cvmx_helper_sgmii_hardware_init_link()
156 control_reg.s.reset = 1; in __cvmx_helper_sgmii_hardware_init_link()
158 control_reg.u64); in __cvmx_helper_sgmii_hardware_init_link()
173 control_reg.s.rst_an = 1; in __cvmx_helper_sgmii_hardware_init_link()
174 control_reg.s.an_en = 1; in __cvmx_helper_sgmii_hardware_init_link()
175 control_reg.s.pwr_dn = 0; in __cvmx_helper_sgmii_hardware_init_link()
177 control_reg.u64); in __cvmx_helper_sgmii_hardware_init_link()
/linux-4.1.27/drivers/watchdog/
Dts72xx_wdt.c58 void __iomem *control_reg; member
166 __raw_writeb((u8)wdt->regval, wdt->control_reg); in ts72xx_wdt_start()
178 __raw_writeb(0, wdt->control_reg); in ts72xx_wdt_stop()
401 wdt->control_reg = devm_ioremap_resource(&pdev->dev, r1); in ts72xx_wdt_probe()
402 if (IS_ERR(wdt->control_reg)) in ts72xx_wdt_probe()
403 return PTR_ERR(wdt->control_reg); in ts72xx_wdt_probe()
/linux-4.1.27/drivers/power/
Dds2780_battery.c366 u8 *control_reg) in ds2780_get_control_register() argument
368 return ds2780_read8(dev_info, control_reg, DS2780_CONTROL_REG); in ds2780_get_control_register()
372 u8 control_reg) in ds2780_set_control_register() argument
376 ret = ds2780_write(dev_info, &control_reg, in ds2780_set_control_register()
457 u8 control_reg; in ds2780_get_pmod_enabled() local
462 ret = ds2780_get_control_register(dev_info, &control_reg); in ds2780_get_pmod_enabled()
467 !!(control_reg & DS2780_CONTROL_REG_PMOD)); in ds2780_get_pmod_enabled()
476 u8 control_reg, new_setting; in ds2780_set_pmod_enabled() local
481 ret = ds2780_get_control_register(dev_info, &control_reg); in ds2780_set_pmod_enabled()
495 control_reg |= DS2780_CONTROL_REG_PMOD; in ds2780_set_pmod_enabled()
[all …]
Dds2781_battery.c368 u8 *control_reg) in ds2781_get_control_register() argument
370 return ds2781_read8(dev_info, control_reg, DS2781_CONTROL); in ds2781_get_control_register()
374 u8 control_reg) in ds2781_set_control_register() argument
378 ret = ds2781_write(dev_info, &control_reg, in ds2781_set_control_register()
459 u8 control_reg; in ds2781_get_pmod_enabled() local
464 ret = ds2781_get_control_register(dev_info, &control_reg); in ds2781_get_pmod_enabled()
469 !!(control_reg & DS2781_CONTROL_PMOD)); in ds2781_get_pmod_enabled()
478 u8 control_reg, new_setting; in ds2781_set_pmod_enabled() local
483 ret = ds2781_get_control_register(dev_info, &control_reg); in ds2781_set_pmod_enabled()
497 control_reg |= DS2781_CONTROL_PMOD; in ds2781_set_pmod_enabled()
[all …]
/linux-4.1.27/drivers/regulator/
Das3722-regulator.c69 u32 control_reg; member
100 .control_reg = AS3722_SD0_CONTROL_REG,
112 .control_reg = AS3722_SD1_CONTROL_REG,
125 .control_reg = AS3722_SD23_CONTROL_REG,
139 .control_reg = AS3722_SD23_CONTROL_REG,
153 .control_reg = AS3722_SD4_CONTROL_REG,
167 .control_reg = AS3722_SD5_CONTROL_REG,
180 .control_reg = AS3722_SD6_CONTROL_REG,
470 if (!as3722_reg_lookup[id].control_reg) in as3722_sd_get_mode()
473 ret = as3722_read(as3722, as3722_reg_lookup[id].control_reg, &val); in as3722_sd_get_mode()
[all …]
Danatop-regulator.c42 u32 control_reg; member
213 &sreg->control_reg); in anatop_regulator_probe()
262 rdesc->vsel_reg = sreg->control_reg; in anatop_regulator_probe()
273 if (sreg->control_reg && sreg->delay_bit_width) { in anatop_regulator_probe()
Dti-abb-regulator.c105 void __iomem *control_reg; member
280 ti_abb_rmw(regs->opp_sel_mask, info->opp_sel, abb->control_reg); in ti_abb_set_opp()
291 ti_abb_rmw(regs->opp_change_mask, 1, abb->control_reg); in ti_abb_set_opp()
735 abb->control_reg = abb->base + abb->regs->control_off; in ti_abb_probe()
740 abb->control_reg = devm_ioremap_resource(dev, res); in ti_abb_probe()
741 if (IS_ERR(abb->control_reg)) in ti_abb_probe()
742 return PTR_ERR(abb->control_reg); in ti_abb_probe()
/linux-4.1.27/arch/arm/mach-omap2/
Ddpll3xxx.c50 v = omap2_clk_readl(clk, dd->control_reg); in _omap3_dpll_write_clken()
53 omap2_clk_writel(v, clk, dd->control_reg); in _omap3_dpll_write_clken()
311 v = omap2_clk_readl(clk, dd->control_reg); in omap3_noncore_dpll_program()
314 omap2_clk_writel(v, clk, dd->control_reg); in omap3_noncore_dpll_program()
349 v = omap2_clk_readl(clk, dd->control_reg); in omap3_noncore_dpll_program()
365 omap2_clk_writel(v, clk, dd->control_reg); in omap3_noncore_dpll_program()
756 v = omap2_clk_readl(pclk, dd->control_reg) & dd->enable_mask; in omap3_clkoutx2_recalc()
796 v = omap2_clk_readl(pclk, dd->control_reg) & dd->enable_mask; in omap3_clkoutx2_round_rate()
Dclkt_dpll.c214 v = omap2_clk_readl(clk, dd->control_reg); in omap2_init_dpll_parent()
250 v = omap2_clk_readl(clk, dd->control_reg); in omap2_get_dpll_rate()
Ddpll44xx.c130 v = omap2_clk_readl(clk, dd->control_reg); in omap4_dpll_regm4xen_recalc()
/linux-4.1.27/arch/powerpc/sysdev/qe_lib/
Dqe_ic.c432 u32 temp, control_reg = QEIC_CICNR, shift = 0; in qe_ic_set_high_priority() local
452 control_reg = QEIC_CRICR; in qe_ic_set_high_priority()
456 control_reg = QEIC_CRICR; in qe_ic_set_high_priority()
463 temp = qe_ic_read(qe_ic->regs, control_reg); in qe_ic_set_high_priority()
466 qe_ic_write(qe_ic->regs, control_reg, temp); in qe_ic_set_high_priority()
/linux-4.1.27/include/linux/clk/
Dti.h74 void __iomem *control_reg; member
/linux-4.1.27/drivers/net/ethernet/ti/
Dcpsw.c1196 u32 control_reg; in cpsw_init_host_port() local
1206 control_reg = readl(&priv->regs->control); in cpsw_init_host_port()
1207 control_reg |= CPSW_VLAN_AWARE; in cpsw_init_host_port()
1208 writel(control_reg, &priv->regs->control); in cpsw_init_host_port()