143 static u32 set_spdif_bits(struct echoaudio *chip, u32 control_reg, u32 rate)  in set_spdif_bits()  argument
145 	control_reg &= E3G_SPDIF_FORMAT_CLEAR_MASK;  in set_spdif_bits()
149 		control_reg |= E3G_SPDIF_SAMPLE_RATE0 | E3G_SPDIF_SAMPLE_RATE1;  in set_spdif_bits()
153 			control_reg |= E3G_SPDIF_SAMPLE_RATE0;  in set_spdif_bits()
156 		control_reg |= E3G_SPDIF_SAMPLE_RATE1;  in set_spdif_bits()
161 		control_reg |= E3G_SPDIF_PRO_MODE;  in set_spdif_bits()
164 		control_reg |= E3G_SPDIF_NOT_AUDIO;  in set_spdif_bits()
166 	control_reg |= E3G_SPDIF_24_BIT | E3G_SPDIF_TWO_CHANNEL |  in set_spdif_bits()
169 	return control_reg;  in set_spdif_bits()
177 	u32 control_reg;  in set_professional_spdif()  local
179 	control_reg = le32_to_cpu(chip->comm_page->control_register);  in set_professional_spdif()
181 	control_reg = set_spdif_bits(chip, control_reg, chip->sample_rate);  in set_professional_spdif()
182 	return write_control_reg(chip, control_reg, get_frq_reg(chip), 0);  in set_professional_spdif()
258 	u32 control_reg, clock, base_rate, frq_reg;  in set_sample_rate()  local
276 	control_reg = le32_to_cpu(chip->comm_page->control_register);  in set_sample_rate()
277 	control_reg &= E3G_CLOCK_CLEAR_MASK;  in set_sample_rate()
302 	control_reg |= clock;  in set_sample_rate()
303 	control_reg = set_spdif_bits(chip, control_reg, rate);  in set_sample_rate()
318 		"SetSampleRate: %d clock %x\n", rate, control_reg);  in set_sample_rate()
321 	return write_control_reg(chip, control_reg, frq_reg, 0);  in set_sample_rate()
329 	u32 control_reg, clocks_from_dsp;  in set_input_clock()  local
333 	control_reg = le32_to_cpu(chip->comm_page->control_register) &  in set_input_clock()
344 		control_reg |= E3G_SPDIF_CLOCK;  in set_input_clock()
346 			control_reg |= E3G_DOUBLE_SPEED_MODE;  in set_input_clock()
348 			control_reg &= ~E3G_DOUBLE_SPEED_MODE;  in set_input_clock()
353 		control_reg |= E3G_ADAT_CLOCK;  in set_input_clock()
354 		control_reg &= ~E3G_DOUBLE_SPEED_MODE;  in set_input_clock()
357 		control_reg |= E3G_WORD_CLOCK;  in set_input_clock()
359 			control_reg |= E3G_DOUBLE_SPEED_MODE;  in set_input_clock()
361 			control_reg &= ~E3G_DOUBLE_SPEED_MODE;  in set_input_clock()
370 	return write_control_reg(chip, control_reg, get_frq_reg(chip), 1);  in set_input_clock()
377 	u32 control_reg;  in dsp_set_digital_mode()  local
406 	control_reg = le32_to_cpu(chip->comm_page->control_register);  in dsp_set_digital_mode()
407 	control_reg &= E3G_DIGITAL_MODE_CLEAR_MASK;  in dsp_set_digital_mode()
412 		control_reg |= E3G_SPDIF_OPTICAL_MODE;  in dsp_set_digital_mode()
418 		control_reg |= E3G_ADAT_MODE;  in dsp_set_digital_mode()
419 		control_reg &= ~E3G_DOUBLE_SPEED_MODE;	/* @@ useless */  in dsp_set_digital_mode()
423 	err = write_control_reg(chip, control_reg, get_frq_reg(chip), 1);  in dsp_set_digital_mode()