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Searched refs:clk_csr (Results 1 – 11 of 11) sorted by relevance

/linux-4.1.27/include/linux/
Dsxgbe_platform.h47 int clk_csr; member
Dstmmac.h103 int clk_csr; member
/linux-4.1.27/drivers/net/ethernet/stmicro/stmmac/
Dstmmac_pci.c76 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ in stmmac_default_data()
110 plat->clk_csr = 2; in quark_default_data()
Dstmmac_mdio.c76 regValue |= MII_BUSY | ((priv->clk_csr & 0xF) << 2); in stmmac_mdio_read()
112 value |= MII_BUSY | ((priv->clk_csr & 0xF) << 2); in stmmac_mdio_write()
Dstmmac.h102 int clk_csr; member
Dstmmac_main.c176 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { in stmmac_clk_csr_set()
178 priv->clk_csr = STMMAC_CSR_20_35M; in stmmac_clk_csr_set()
180 priv->clk_csr = STMMAC_CSR_35_60M; in stmmac_clk_csr_set()
182 priv->clk_csr = STMMAC_CSR_60_100M; in stmmac_clk_csr_set()
184 priv->clk_csr = STMMAC_CSR_100_150M; in stmmac_clk_csr_set()
186 priv->clk_csr = STMMAC_CSR_150_250M; in stmmac_clk_csr_set()
188 priv->clk_csr = STMMAC_CSR_250_300M; in stmmac_clk_csr_set()
2853 if (!priv->plat->clk_csr) { in stmmac_dvr_probe()
2932 if (!priv->plat->clk_csr) in stmmac_dvr_probe()
2935 priv->clk_csr = priv->plat->clk_csr; in stmmac_dvr_probe()
/linux-4.1.27/drivers/net/ethernet/samsung/sxgbe/
Dsxgbe_main.c177 priv->clk_csr = SXGBE_CSR_100_150M; in sxgbe_clk_csr_set()
179 priv->clk_csr = SXGBE_CSR_150_250M; in sxgbe_clk_csr_set()
181 priv->clk_csr = SXGBE_CSR_250_300M; in sxgbe_clk_csr_set()
183 priv->clk_csr = SXGBE_CSR_300_350M; in sxgbe_clk_csr_set()
185 priv->clk_csr = SXGBE_CSR_350_400M; in sxgbe_clk_csr_set()
187 priv->clk_csr = SXGBE_CSR_400_500M; in sxgbe_clk_csr_set()
2191 if (!priv->plat->clk_csr) in sxgbe_drv_probe()
2194 priv->clk_csr = priv->plat->clk_csr; in sxgbe_drv_probe()
Dsxgbe_mdio.c51 ((sp->clk_csr & 0x7) << 19) | SXGBE_MII_BUSY; in sxgbe_mdio_ctrl_data()
Dsxgbe_common.h494 int clk_csr; member
/linux-4.1.27/drivers/crypto/qat/qat_common/
Dqat_hal.c471 unsigned int clk_csr; in qat_hal_clr_reset() local
487 clk_csr = GET_GLB_CSR(handle, ICP_GLOBAL_CLK_ENABLE); in qat_hal_clr_reset()
488 clk_csr |= handle->hal_handle->ae_mask << 0; in qat_hal_clr_reset()
489 clk_csr |= handle->hal_handle->slice_mask << 20; in qat_hal_clr_reset()
490 SET_GLB_CSR(handle, ICP_GLOBAL_CLK_ENABLE, clk_csr); in qat_hal_clr_reset()
/linux-4.1.27/Documentation/networking/
Dstmmac.txt124 int clk_csr;
160 o clk_csr: fixed CSR Clock range selection.