Searched refs:cik (Results 1 – 5 of 5) sorted by relevance
2325 u32 num_rbs = rdev->config.cik.max_backends_per_se * in cik_tiling_mode_table_init()2326 rdev->config.cik.max_shader_engines; in cik_tiling_mode_table_init()2328 switch (rdev->config.cik.mem_row_size_in_kb) { in cik_tiling_mode_table_init()2341 num_pipe_configs = rdev->config.cik.max_tile_pipes; in cik_tiling_mode_table_init()2472 rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden; in cik_tiling_mode_table_init()2565 rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden; in cik_tiling_mode_table_init()2695 rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden; in cik_tiling_mode_table_init()2788 rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden; in cik_tiling_mode_table_init()2919 rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden; in cik_tiling_mode_table_init()3049 rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden; in cik_tiling_mode_table_init()[all …]
279 *value = rdev->config.cik.tile_config; in radeon_info_ioctl()333 *value = rdev->config.cik.max_backends_per_se * in radeon_info_ioctl()334 rdev->config.cik.max_shader_engines; in radeon_info_ioctl()353 *value = rdev->config.cik.max_tile_pipes; in radeon_info_ioctl()373 *value = rdev->config.cik.backend_map; in radeon_info_ioctl()402 *value = rdev->config.cik.max_cu_per_sh; in radeon_info_ioctl()428 *value = rdev->config.cik.max_shader_engines; in radeon_info_ioctl()440 *value = rdev->config.cik.max_sh_per_se; in radeon_info_ioctl()475 value = rdev->config.cik.tile_mode_array; in radeon_info_ioctl()487 value = rdev->config.cik.macrotile_mode_array; in radeon_info_ioctl()[all …]
79 si_blit_shaders.o radeon_prime.o cik.o cik_blit_shaders.o \
1285 num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3; in dce4_crtc_do_set_base()1341 u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f; in dce4_crtc_do_set_base()
804 struct cik_irq_stat_regs cik; member2204 struct cik_asic cik; member