2325 	u32 num_rbs = rdev->config.cik.max_backends_per_se *  in cik_tiling_mode_table_init()
2326 		rdev->config.cik.max_shader_engines;  in cik_tiling_mode_table_init()
2328 	switch (rdev->config.cik.mem_row_size_in_kb) {  in cik_tiling_mode_table_init()
2341 	num_pipe_configs = rdev->config.cik.max_tile_pipes;  in cik_tiling_mode_table_init()
2472 			rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;  in cik_tiling_mode_table_init()
2565 			rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;  in cik_tiling_mode_table_init()
2695 			rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;  in cik_tiling_mode_table_init()
2788 			rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;  in cik_tiling_mode_table_init()
2919 				rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;  in cik_tiling_mode_table_init()
3049 				rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;  in cik_tiling_mode_table_init()
3143 			rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;  in cik_tiling_mode_table_init()
3273 			rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;  in cik_tiling_mode_table_init()
3366 			rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;  in cik_tiling_mode_table_init()
3490 	rdev->config.cik.backend_enable_mask = enabled_rbs;  in cik_setup_rb()
3541 		rdev->config.cik.max_shader_engines = 2;  in cik_gpu_init()
3542 		rdev->config.cik.max_tile_pipes = 4;  in cik_gpu_init()
3543 		rdev->config.cik.max_cu_per_sh = 7;  in cik_gpu_init()
3544 		rdev->config.cik.max_sh_per_se = 1;  in cik_gpu_init()
3545 		rdev->config.cik.max_backends_per_se = 2;  in cik_gpu_init()
3546 		rdev->config.cik.max_texture_channel_caches = 4;  in cik_gpu_init()
3547 		rdev->config.cik.max_gprs = 256;  in cik_gpu_init()
3548 		rdev->config.cik.max_gs_threads = 32;  in cik_gpu_init()
3549 		rdev->config.cik.max_hw_contexts = 8;  in cik_gpu_init()
3551 		rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;  in cik_gpu_init()
3552 		rdev->config.cik.sc_prim_fifo_size_backend = 0x100;  in cik_gpu_init()
3553 		rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;  in cik_gpu_init()
3554 		rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;  in cik_gpu_init()
3558 		rdev->config.cik.max_shader_engines = 4;  in cik_gpu_init()
3559 		rdev->config.cik.max_tile_pipes = 16;  in cik_gpu_init()
3560 		rdev->config.cik.max_cu_per_sh = 11;  in cik_gpu_init()
3561 		rdev->config.cik.max_sh_per_se = 1;  in cik_gpu_init()
3562 		rdev->config.cik.max_backends_per_se = 4;  in cik_gpu_init()
3563 		rdev->config.cik.max_texture_channel_caches = 16;  in cik_gpu_init()
3564 		rdev->config.cik.max_gprs = 256;  in cik_gpu_init()
3565 		rdev->config.cik.max_gs_threads = 32;  in cik_gpu_init()
3566 		rdev->config.cik.max_hw_contexts = 8;  in cik_gpu_init()
3568 		rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;  in cik_gpu_init()
3569 		rdev->config.cik.sc_prim_fifo_size_backend = 0x100;  in cik_gpu_init()
3570 		rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;  in cik_gpu_init()
3571 		rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;  in cik_gpu_init()
3575 		rdev->config.cik.max_shader_engines = 1;  in cik_gpu_init()
3576 		rdev->config.cik.max_tile_pipes = 4;  in cik_gpu_init()
3584 			rdev->config.cik.max_cu_per_sh = 8;  in cik_gpu_init()
3585 			rdev->config.cik.max_backends_per_se = 2;  in cik_gpu_init()
3591 			rdev->config.cik.max_cu_per_sh = 6;  in cik_gpu_init()
3592 			rdev->config.cik.max_backends_per_se = 2;  in cik_gpu_init()
3600 			rdev->config.cik.max_cu_per_sh = 4;  in cik_gpu_init()
3601 			rdev->config.cik.max_backends_per_se = 1;  in cik_gpu_init()
3603 			rdev->config.cik.max_cu_per_sh = 3;  in cik_gpu_init()
3604 			rdev->config.cik.max_backends_per_se = 1;  in cik_gpu_init()
3606 		rdev->config.cik.max_sh_per_se = 1;  in cik_gpu_init()
3607 		rdev->config.cik.max_texture_channel_caches = 4;  in cik_gpu_init()
3608 		rdev->config.cik.max_gprs = 256;  in cik_gpu_init()
3609 		rdev->config.cik.max_gs_threads = 16;  in cik_gpu_init()
3610 		rdev->config.cik.max_hw_contexts = 8;  in cik_gpu_init()
3612 		rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;  in cik_gpu_init()
3613 		rdev->config.cik.sc_prim_fifo_size_backend = 0x100;  in cik_gpu_init()
3614 		rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;  in cik_gpu_init()
3615 		rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;  in cik_gpu_init()
3621 		rdev->config.cik.max_shader_engines = 1;  in cik_gpu_init()
3622 		rdev->config.cik.max_tile_pipes = 2;  in cik_gpu_init()
3623 		rdev->config.cik.max_cu_per_sh = 2;  in cik_gpu_init()
3624 		rdev->config.cik.max_sh_per_se = 1;  in cik_gpu_init()
3625 		rdev->config.cik.max_backends_per_se = 1;  in cik_gpu_init()
3626 		rdev->config.cik.max_texture_channel_caches = 2;  in cik_gpu_init()
3627 		rdev->config.cik.max_gprs = 256;  in cik_gpu_init()
3628 		rdev->config.cik.max_gs_threads = 16;  in cik_gpu_init()
3629 		rdev->config.cik.max_hw_contexts = 8;  in cik_gpu_init()
3631 		rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;  in cik_gpu_init()
3632 		rdev->config.cik.sc_prim_fifo_size_backend = 0x100;  in cik_gpu_init()
3633 		rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;  in cik_gpu_init()
3634 		rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;  in cik_gpu_init()
3657 	rdev->config.cik.num_tile_pipes = rdev->config.cik.max_tile_pipes;  in cik_gpu_init()
3658 	rdev->config.cik.mem_max_burst_length_bytes = 256;  in cik_gpu_init()
3660 	rdev->config.cik.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;  in cik_gpu_init()
3661 	if (rdev->config.cik.mem_row_size_in_kb > 4)  in cik_gpu_init()
3662 		rdev->config.cik.mem_row_size_in_kb = 4;  in cik_gpu_init()
3664 	rdev->config.cik.shader_engine_tile_size = 32;  in cik_gpu_init()
3665 	rdev->config.cik.num_gpus = 1;  in cik_gpu_init()
3666 	rdev->config.cik.multi_gpu_tile_size = 64;  in cik_gpu_init()
3670 	switch (rdev->config.cik.mem_row_size_in_kb) {  in cik_gpu_init()
3690 	rdev->config.cik.tile_config = 0;  in cik_gpu_init()
3691 	switch (rdev->config.cik.num_tile_pipes) {  in cik_gpu_init()
3693 		rdev->config.cik.tile_config |= (0 << 0);  in cik_gpu_init()
3696 		rdev->config.cik.tile_config |= (1 << 0);  in cik_gpu_init()
3699 		rdev->config.cik.tile_config |= (2 << 0);  in cik_gpu_init()
3704 		rdev->config.cik.tile_config |= (3 << 0);  in cik_gpu_init()
3707 	rdev->config.cik.tile_config |=  in cik_gpu_init()
3709 	rdev->config.cik.tile_config |=  in cik_gpu_init()
3711 	rdev->config.cik.tile_config |=  in cik_gpu_init()
3725 	cik_setup_rb(rdev, rdev->config.cik.max_shader_engines,  in cik_gpu_init()
3726 		     rdev->config.cik.max_sh_per_se,  in cik_gpu_init()
3727 		     rdev->config.cik.max_backends_per_se);  in cik_gpu_init()
3729 	rdev->config.cik.active_cus = 0;  in cik_gpu_init()
3730 	for (i = 0; i < rdev->config.cik.max_shader_engines; i++) {  in cik_gpu_init()
3731 		for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) {  in cik_gpu_init()
3732 			rdev->config.cik.active_cus +=  in cik_gpu_init()
3772 	WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.cik.sc_prim_fifo_size_frontend) |  in cik_gpu_init()
3773 				 SC_BACKEND_PRIM_FIFO_SIZE(rdev->config.cik.sc_prim_fifo_size_backend) |  in cik_gpu_init()
3774 				 SC_HIZ_TILE_FIFO_SIZE(rdev->config.cik.sc_hiz_tile_fifo_size) |  in cik_gpu_init()
3775 				 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cik.sc_earlyz_tile_fifo_size)));  in cik_gpu_init()
4371 	WREG32(CP_MAX_CONTEXT, rdev->config.cik.max_hw_contexts - 1);  in cik_cp_gfx_start()
6199 	for (i = 0; i < rdev->config.cik.max_shader_engines; i++) {  in cik_wait_for_rlc_serdes()
6200 		for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) {  in cik_wait_for_rlc_serdes()
6963 	for (i = 0; i < rdev->config.cik.max_cu_per_sh; i ++) {  in cik_get_cu_active_bitmap()
6977 	for (i = 0; i < rdev->config.cik.max_shader_engines; i++) {  in cik_init_ao_cu_mask()
6978 		for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) {  in cik_init_ao_cu_mask()
6982 			for (k = 0; k < rdev->config.cik.max_cu_per_sh; k ++) {  in cik_init_ao_cu_mask()
7644 	rdev->irq.stat_regs.cik.disp_int = RREG32(DISP_INTERRUPT_STATUS);  in cik_irq_ack()
7645 	rdev->irq.stat_regs.cik.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);  in cik_irq_ack()
7646 	rdev->irq.stat_regs.cik.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);  in cik_irq_ack()
7647 	rdev->irq.stat_regs.cik.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);  in cik_irq_ack()
7648 	rdev->irq.stat_regs.cik.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);  in cik_irq_ack()
7649 	rdev->irq.stat_regs.cik.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);  in cik_irq_ack()
7650 	rdev->irq.stat_regs.cik.disp_int_cont6 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE6);  in cik_irq_ack()
7652 	rdev->irq.stat_regs.cik.d1grph_int = RREG32(GRPH_INT_STATUS +  in cik_irq_ack()
7654 	rdev->irq.stat_regs.cik.d2grph_int = RREG32(GRPH_INT_STATUS +  in cik_irq_ack()
7657 		rdev->irq.stat_regs.cik.d3grph_int = RREG32(GRPH_INT_STATUS +  in cik_irq_ack()
7659 		rdev->irq.stat_regs.cik.d4grph_int = RREG32(GRPH_INT_STATUS +  in cik_irq_ack()
7663 		rdev->irq.stat_regs.cik.d5grph_int = RREG32(GRPH_INT_STATUS +  in cik_irq_ack()
7665 		rdev->irq.stat_regs.cik.d6grph_int = RREG32(GRPH_INT_STATUS +  in cik_irq_ack()
7669 	if (rdev->irq.stat_regs.cik.d1grph_int & GRPH_PFLIP_INT_OCCURRED)  in cik_irq_ack()
7672 	if (rdev->irq.stat_regs.cik.d2grph_int & GRPH_PFLIP_INT_OCCURRED)  in cik_irq_ack()
7675 	if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VBLANK_INTERRUPT)  in cik_irq_ack()
7677 	if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VLINE_INTERRUPT)  in cik_irq_ack()
7679 	if (rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VBLANK_INTERRUPT)  in cik_irq_ack()
7681 	if (rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VLINE_INTERRUPT)  in cik_irq_ack()
7685 		if (rdev->irq.stat_regs.cik.d3grph_int & GRPH_PFLIP_INT_OCCURRED)  in cik_irq_ack()
7688 		if (rdev->irq.stat_regs.cik.d4grph_int & GRPH_PFLIP_INT_OCCURRED)  in cik_irq_ack()
7691 		if (rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)  in cik_irq_ack()
7693 		if (rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)  in cik_irq_ack()
7695 		if (rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)  in cik_irq_ack()
7697 		if (rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)  in cik_irq_ack()
7702 		if (rdev->irq.stat_regs.cik.d5grph_int & GRPH_PFLIP_INT_OCCURRED)  in cik_irq_ack()
7705 		if (rdev->irq.stat_regs.cik.d6grph_int & GRPH_PFLIP_INT_OCCURRED)  in cik_irq_ack()
7708 		if (rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)  in cik_irq_ack()
7710 		if (rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)  in cik_irq_ack()
7712 		if (rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)  in cik_irq_ack()
7714 		if (rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)  in cik_irq_ack()
7718 	if (rdev->irq.stat_regs.cik.disp_int & DC_HPD1_INTERRUPT) {  in cik_irq_ack()
7723 	if (rdev->irq.stat_regs.cik.disp_int_cont & DC_HPD2_INTERRUPT) {  in cik_irq_ack()
7728 	if (rdev->irq.stat_regs.cik.disp_int_cont2 & DC_HPD3_INTERRUPT) {  in cik_irq_ack()
7733 	if (rdev->irq.stat_regs.cik.disp_int_cont3 & DC_HPD4_INTERRUPT) {  in cik_irq_ack()
7738 	if (rdev->irq.stat_regs.cik.disp_int_cont4 & DC_HPD5_INTERRUPT) {  in cik_irq_ack()
7743 	if (rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_INTERRUPT) {  in cik_irq_ack()
7748 	if (rdev->irq.stat_regs.cik.disp_int & DC_HPD1_RX_INTERRUPT) {  in cik_irq_ack()
7753 	if (rdev->irq.stat_regs.cik.disp_int_cont & DC_HPD2_RX_INTERRUPT) {  in cik_irq_ack()
7758 	if (rdev->irq.stat_regs.cik.disp_int_cont2 & DC_HPD3_RX_INTERRUPT) {  in cik_irq_ack()
7763 	if (rdev->irq.stat_regs.cik.disp_int_cont3 & DC_HPD4_RX_INTERRUPT) {  in cik_irq_ack()
7768 	if (rdev->irq.stat_regs.cik.disp_int_cont4 & DC_HPD5_RX_INTERRUPT) {  in cik_irq_ack()
7773 	if (rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_RX_INTERRUPT) {  in cik_irq_ack()
7942 				if (!(rdev->irq.stat_regs.cik.disp_int & LB_D1_VBLANK_INTERRUPT))  in cik_irq_process()
7952 				rdev->irq.stat_regs.cik.disp_int &= ~LB_D1_VBLANK_INTERRUPT;  in cik_irq_process()
7957 				if (!(rdev->irq.stat_regs.cik.disp_int & LB_D1_VLINE_INTERRUPT))  in cik_irq_process()
7960 				rdev->irq.stat_regs.cik.disp_int &= ~LB_D1_VLINE_INTERRUPT;  in cik_irq_process()
7972 				if (!(rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VBLANK_INTERRUPT))  in cik_irq_process()
7982 				rdev->irq.stat_regs.cik.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;  in cik_irq_process()
7987 				if (!(rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VLINE_INTERRUPT))  in cik_irq_process()
7990 				rdev->irq.stat_regs.cik.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;  in cik_irq_process()
8002 				if (!(rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT))  in cik_irq_process()
8012 				rdev->irq.stat_regs.cik.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;  in cik_irq_process()
8017 				if (!(rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VLINE_INTERRUPT))  in cik_irq_process()
8020 				rdev->irq.stat_regs.cik.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;  in cik_irq_process()
8032 				if (!(rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT))  in cik_irq_process()
8042 				rdev->irq.stat_regs.cik.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;  in cik_irq_process()
8047 				if (!(rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VLINE_INTERRUPT))  in cik_irq_process()
8050 				rdev->irq.stat_regs.cik.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;  in cik_irq_process()
8062 				if (!(rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT))  in cik_irq_process()
8072 				rdev->irq.stat_regs.cik.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;  in cik_irq_process()
8077 				if (!(rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VLINE_INTERRUPT))  in cik_irq_process()
8080 				rdev->irq.stat_regs.cik.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;  in cik_irq_process()
8092 				if (!(rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT))  in cik_irq_process()
8102 				rdev->irq.stat_regs.cik.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;  in cik_irq_process()
8107 				if (!(rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VLINE_INTERRUPT))  in cik_irq_process()
8110 				rdev->irq.stat_regs.cik.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;  in cik_irq_process()
8132 				if (!(rdev->irq.stat_regs.cik.disp_int & DC_HPD1_INTERRUPT))  in cik_irq_process()
8135 				rdev->irq.stat_regs.cik.disp_int &= ~DC_HPD1_INTERRUPT;  in cik_irq_process()
8141 				if (!(rdev->irq.stat_regs.cik.disp_int_cont & DC_HPD2_INTERRUPT))  in cik_irq_process()
8144 				rdev->irq.stat_regs.cik.disp_int_cont &= ~DC_HPD2_INTERRUPT;  in cik_irq_process()
8150 				if (!(rdev->irq.stat_regs.cik.disp_int_cont2 & DC_HPD3_INTERRUPT))  in cik_irq_process()
8153 				rdev->irq.stat_regs.cik.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;  in cik_irq_process()
8159 				if (!(rdev->irq.stat_regs.cik.disp_int_cont3 & DC_HPD4_INTERRUPT))  in cik_irq_process()
8162 				rdev->irq.stat_regs.cik.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;  in cik_irq_process()
8168 				if (!(rdev->irq.stat_regs.cik.disp_int_cont4 & DC_HPD5_INTERRUPT))  in cik_irq_process()
8171 				rdev->irq.stat_regs.cik.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;  in cik_irq_process()
8177 				if (!(rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_INTERRUPT))  in cik_irq_process()
8180 				rdev->irq.stat_regs.cik.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;  in cik_irq_process()
8186 				if (!(rdev->irq.stat_regs.cik.disp_int & DC_HPD1_RX_INTERRUPT))  in cik_irq_process()
8189 				rdev->irq.stat_regs.cik.disp_int &= ~DC_HPD1_RX_INTERRUPT;  in cik_irq_process()
8195 				if (!(rdev->irq.stat_regs.cik.disp_int_cont & DC_HPD2_RX_INTERRUPT))  in cik_irq_process()
8198 				rdev->irq.stat_regs.cik.disp_int_cont &= ~DC_HPD2_RX_INTERRUPT;  in cik_irq_process()
8204 				if (!(rdev->irq.stat_regs.cik.disp_int_cont2 & DC_HPD3_RX_INTERRUPT))  in cik_irq_process()
8207 				rdev->irq.stat_regs.cik.disp_int_cont2 &= ~DC_HPD3_RX_INTERRUPT;  in cik_irq_process()
8213 				if (!(rdev->irq.stat_regs.cik.disp_int_cont3 & DC_HPD4_RX_INTERRUPT))  in cik_irq_process()
8216 				rdev->irq.stat_regs.cik.disp_int_cont3 &= ~DC_HPD4_RX_INTERRUPT;  in cik_irq_process()
8222 				if (!(rdev->irq.stat_regs.cik.disp_int_cont4 & DC_HPD5_RX_INTERRUPT))  in cik_irq_process()
8225 				rdev->irq.stat_regs.cik.disp_int_cont4 &= ~DC_HPD5_RX_INTERRUPT;  in cik_irq_process()
8231 				if (!(rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_RX_INTERRUPT))  in cik_irq_process()
8234 				rdev->irq.stat_regs.cik.disp_int_cont5 &= ~DC_HPD6_RX_INTERRUPT;  in cik_irq_process()