1/* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28#include <drm/drmP.h> 29#include "radeon.h" 30#include <drm/radeon_drm.h> 31#include "radeon_asic.h" 32 33#include <linux/vga_switcheroo.h> 34#include <linux/slab.h> 35#include <linux/pm_runtime.h> 36 37#include "radeon_kfd.h" 38 39#if defined(CONFIG_VGA_SWITCHEROO) 40bool radeon_has_atpx(void); 41#else 42static inline bool radeon_has_atpx(void) { return false; } 43#endif 44 45/** 46 * radeon_driver_unload_kms - Main unload function for KMS. 47 * 48 * @dev: drm dev pointer 49 * 50 * This is the main unload function for KMS (all asics). 51 * It calls radeon_modeset_fini() to tear down the 52 * displays, and radeon_device_fini() to tear down 53 * the rest of the device (CP, writeback, etc.). 54 * Returns 0 on success. 55 */ 56int radeon_driver_unload_kms(struct drm_device *dev) 57{ 58 struct radeon_device *rdev = dev->dev_private; 59 60 if (rdev == NULL) 61 return 0; 62 63 if (rdev->rmmio == NULL) 64 goto done_free; 65 66 pm_runtime_get_sync(dev->dev); 67 68 radeon_kfd_device_fini(rdev); 69 70 radeon_acpi_fini(rdev); 71 72 radeon_modeset_fini(rdev); 73 radeon_device_fini(rdev); 74 75done_free: 76 kfree(rdev); 77 dev->dev_private = NULL; 78 return 0; 79} 80 81/** 82 * radeon_driver_load_kms - Main load function for KMS. 83 * 84 * @dev: drm dev pointer 85 * @flags: device flags 86 * 87 * This is the main load function for KMS (all asics). 88 * It calls radeon_device_init() to set up the non-display 89 * parts of the chip (asic init, CP, writeback, etc.), and 90 * radeon_modeset_init() to set up the display parts 91 * (crtcs, encoders, hotplug detect, etc.). 92 * Returns 0 on success, error on failure. 93 */ 94int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) 95{ 96 struct radeon_device *rdev; 97 int r, acpi_status; 98 99 rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL); 100 if (rdev == NULL) { 101 return -ENOMEM; 102 } 103 dev->dev_private = (void *)rdev; 104 105 /* update BUS flag */ 106 if (drm_pci_device_is_agp(dev)) { 107 flags |= RADEON_IS_AGP; 108 } else if (pci_is_pcie(dev->pdev)) { 109 flags |= RADEON_IS_PCIE; 110 } else { 111 flags |= RADEON_IS_PCI; 112 } 113 114 if ((radeon_runtime_pm != 0) && 115 radeon_has_atpx() && 116 ((flags & RADEON_IS_IGP) == 0)) 117 flags |= RADEON_IS_PX; 118 119 /* radeon_device_init should report only fatal error 120 * like memory allocation failure or iomapping failure, 121 * or memory manager initialization failure, it must 122 * properly initialize the GPU MC controller and permit 123 * VRAM allocation 124 */ 125 r = radeon_device_init(rdev, dev, dev->pdev, flags); 126 if (r) { 127 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); 128 goto out; 129 } 130 131 /* Again modeset_init should fail only on fatal error 132 * otherwise it should provide enough functionalities 133 * for shadowfb to run 134 */ 135 r = radeon_modeset_init(rdev); 136 if (r) 137 dev_err(&dev->pdev->dev, "Fatal error during modeset init\n"); 138 139 /* Call ACPI methods: require modeset init 140 * but failure is not fatal 141 */ 142 if (!r) { 143 acpi_status = radeon_acpi_init(rdev); 144 if (acpi_status) 145 dev_dbg(&dev->pdev->dev, 146 "Error during ACPI methods call\n"); 147 } 148 149 radeon_kfd_device_probe(rdev); 150 radeon_kfd_device_init(rdev); 151 152 if (radeon_is_px(dev)) { 153 pm_runtime_use_autosuspend(dev->dev); 154 pm_runtime_set_autosuspend_delay(dev->dev, 5000); 155 pm_runtime_set_active(dev->dev); 156 pm_runtime_allow(dev->dev); 157 pm_runtime_mark_last_busy(dev->dev); 158 pm_runtime_put_autosuspend(dev->dev); 159 } 160 161out: 162 if (r) 163 radeon_driver_unload_kms(dev); 164 165 166 return r; 167} 168 169/** 170 * radeon_set_filp_rights - Set filp right. 171 * 172 * @dev: drm dev pointer 173 * @owner: drm file 174 * @applier: drm file 175 * @value: value 176 * 177 * Sets the filp rights for the device (all asics). 178 */ 179static void radeon_set_filp_rights(struct drm_device *dev, 180 struct drm_file **owner, 181 struct drm_file *applier, 182 uint32_t *value) 183{ 184 mutex_lock(&dev->struct_mutex); 185 if (*value == 1) { 186 /* wants rights */ 187 if (!*owner) 188 *owner = applier; 189 } else if (*value == 0) { 190 /* revokes rights */ 191 if (*owner == applier) 192 *owner = NULL; 193 } 194 *value = *owner == applier ? 1 : 0; 195 mutex_unlock(&dev->struct_mutex); 196} 197 198/* 199 * Userspace get information ioctl 200 */ 201/** 202 * radeon_info_ioctl - answer a device specific request. 203 * 204 * @rdev: radeon device pointer 205 * @data: request object 206 * @filp: drm filp 207 * 208 * This function is used to pass device specific parameters to the userspace 209 * drivers. Examples include: pci device id, pipeline parms, tiling params, 210 * etc. (all asics). 211 * Returns 0 on success, -EINVAL on failure. 212 */ 213static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 214{ 215 struct radeon_device *rdev = dev->dev_private; 216 struct drm_radeon_info *info = data; 217 struct radeon_mode_info *minfo = &rdev->mode_info; 218 uint32_t *value, value_tmp, *value_ptr, value_size; 219 uint64_t value64; 220 struct drm_crtc *crtc; 221 int i, found; 222 223 value_ptr = (uint32_t *)((unsigned long)info->value); 224 value = &value_tmp; 225 value_size = sizeof(uint32_t); 226 227 switch (info->request) { 228 case RADEON_INFO_DEVICE_ID: 229 *value = dev->pdev->device; 230 break; 231 case RADEON_INFO_NUM_GB_PIPES: 232 *value = rdev->num_gb_pipes; 233 break; 234 case RADEON_INFO_NUM_Z_PIPES: 235 *value = rdev->num_z_pipes; 236 break; 237 case RADEON_INFO_ACCEL_WORKING: 238 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */ 239 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) 240 *value = false; 241 else 242 *value = rdev->accel_working; 243 break; 244 case RADEON_INFO_CRTC_FROM_ID: 245 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 246 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 247 return -EFAULT; 248 } 249 for (i = 0, found = 0; i < rdev->num_crtc; i++) { 250 crtc = (struct drm_crtc *)minfo->crtcs[i]; 251 if (crtc && crtc->base.id == *value) { 252 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 253 *value = radeon_crtc->crtc_id; 254 found = 1; 255 break; 256 } 257 } 258 if (!found) { 259 DRM_DEBUG_KMS("unknown crtc id %d\n", *value); 260 return -EINVAL; 261 } 262 break; 263 case RADEON_INFO_ACCEL_WORKING2: 264 if (rdev->family == CHIP_HAWAII) { 265 if (rdev->accel_working) { 266 if (rdev->new_fw) 267 *value = 3; 268 else 269 *value = 2; 270 } else { 271 *value = 0; 272 } 273 } else { 274 *value = rdev->accel_working; 275 } 276 break; 277 case RADEON_INFO_TILING_CONFIG: 278 if (rdev->family >= CHIP_BONAIRE) 279 *value = rdev->config.cik.tile_config; 280 else if (rdev->family >= CHIP_TAHITI) 281 *value = rdev->config.si.tile_config; 282 else if (rdev->family >= CHIP_CAYMAN) 283 *value = rdev->config.cayman.tile_config; 284 else if (rdev->family >= CHIP_CEDAR) 285 *value = rdev->config.evergreen.tile_config; 286 else if (rdev->family >= CHIP_RV770) 287 *value = rdev->config.rv770.tile_config; 288 else if (rdev->family >= CHIP_R600) 289 *value = rdev->config.r600.tile_config; 290 else { 291 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n"); 292 return -EINVAL; 293 } 294 break; 295 case RADEON_INFO_WANT_HYPERZ: 296 /* The "value" here is both an input and output parameter. 297 * If the input value is 1, filp requests hyper-z access. 298 * If the input value is 0, filp revokes its hyper-z access. 299 * 300 * When returning, the value is 1 if filp owns hyper-z access, 301 * 0 otherwise. */ 302 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 303 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 304 return -EFAULT; 305 } 306 if (*value >= 2) { 307 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value); 308 return -EINVAL; 309 } 310 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value); 311 break; 312 case RADEON_INFO_WANT_CMASK: 313 /* The same logic as Hyper-Z. */ 314 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 315 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 316 return -EFAULT; 317 } 318 if (*value >= 2) { 319 DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value); 320 return -EINVAL; 321 } 322 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value); 323 break; 324 case RADEON_INFO_CLOCK_CRYSTAL_FREQ: 325 /* return clock value in KHz */ 326 if (rdev->asic->get_xclk) 327 *value = radeon_get_xclk(rdev) * 10; 328 else 329 *value = rdev->clock.spll.reference_freq * 10; 330 break; 331 case RADEON_INFO_NUM_BACKENDS: 332 if (rdev->family >= CHIP_BONAIRE) 333 *value = rdev->config.cik.max_backends_per_se * 334 rdev->config.cik.max_shader_engines; 335 else if (rdev->family >= CHIP_TAHITI) 336 *value = rdev->config.si.max_backends_per_se * 337 rdev->config.si.max_shader_engines; 338 else if (rdev->family >= CHIP_CAYMAN) 339 *value = rdev->config.cayman.max_backends_per_se * 340 rdev->config.cayman.max_shader_engines; 341 else if (rdev->family >= CHIP_CEDAR) 342 *value = rdev->config.evergreen.max_backends; 343 else if (rdev->family >= CHIP_RV770) 344 *value = rdev->config.rv770.max_backends; 345 else if (rdev->family >= CHIP_R600) 346 *value = rdev->config.r600.max_backends; 347 else { 348 return -EINVAL; 349 } 350 break; 351 case RADEON_INFO_NUM_TILE_PIPES: 352 if (rdev->family >= CHIP_BONAIRE) 353 *value = rdev->config.cik.max_tile_pipes; 354 else if (rdev->family >= CHIP_TAHITI) 355 *value = rdev->config.si.max_tile_pipes; 356 else if (rdev->family >= CHIP_CAYMAN) 357 *value = rdev->config.cayman.max_tile_pipes; 358 else if (rdev->family >= CHIP_CEDAR) 359 *value = rdev->config.evergreen.max_tile_pipes; 360 else if (rdev->family >= CHIP_RV770) 361 *value = rdev->config.rv770.max_tile_pipes; 362 else if (rdev->family >= CHIP_R600) 363 *value = rdev->config.r600.max_tile_pipes; 364 else { 365 return -EINVAL; 366 } 367 break; 368 case RADEON_INFO_FUSION_GART_WORKING: 369 *value = 1; 370 break; 371 case RADEON_INFO_BACKEND_MAP: 372 if (rdev->family >= CHIP_BONAIRE) 373 *value = rdev->config.cik.backend_map; 374 else if (rdev->family >= CHIP_TAHITI) 375 *value = rdev->config.si.backend_map; 376 else if (rdev->family >= CHIP_CAYMAN) 377 *value = rdev->config.cayman.backend_map; 378 else if (rdev->family >= CHIP_CEDAR) 379 *value = rdev->config.evergreen.backend_map; 380 else if (rdev->family >= CHIP_RV770) 381 *value = rdev->config.rv770.backend_map; 382 else if (rdev->family >= CHIP_R600) 383 *value = rdev->config.r600.backend_map; 384 else { 385 return -EINVAL; 386 } 387 break; 388 case RADEON_INFO_VA_START: 389 /* this is where we report if vm is supported or not */ 390 if (rdev->family < CHIP_CAYMAN) 391 return -EINVAL; 392 *value = RADEON_VA_RESERVED_SIZE; 393 break; 394 case RADEON_INFO_IB_VM_MAX_SIZE: 395 /* this is where we report if vm is supported or not */ 396 if (rdev->family < CHIP_CAYMAN) 397 return -EINVAL; 398 *value = RADEON_IB_VM_MAX_SIZE; 399 break; 400 case RADEON_INFO_MAX_PIPES: 401 if (rdev->family >= CHIP_BONAIRE) 402 *value = rdev->config.cik.max_cu_per_sh; 403 else if (rdev->family >= CHIP_TAHITI) 404 *value = rdev->config.si.max_cu_per_sh; 405 else if (rdev->family >= CHIP_CAYMAN) 406 *value = rdev->config.cayman.max_pipes_per_simd; 407 else if (rdev->family >= CHIP_CEDAR) 408 *value = rdev->config.evergreen.max_pipes; 409 else if (rdev->family >= CHIP_RV770) 410 *value = rdev->config.rv770.max_pipes; 411 else if (rdev->family >= CHIP_R600) 412 *value = rdev->config.r600.max_pipes; 413 else { 414 return -EINVAL; 415 } 416 break; 417 case RADEON_INFO_TIMESTAMP: 418 if (rdev->family < CHIP_R600) { 419 DRM_DEBUG_KMS("timestamp is r6xx+ only!\n"); 420 return -EINVAL; 421 } 422 value = (uint32_t*)&value64; 423 value_size = sizeof(uint64_t); 424 value64 = radeon_get_gpu_clock_counter(rdev); 425 break; 426 case RADEON_INFO_MAX_SE: 427 if (rdev->family >= CHIP_BONAIRE) 428 *value = rdev->config.cik.max_shader_engines; 429 else if (rdev->family >= CHIP_TAHITI) 430 *value = rdev->config.si.max_shader_engines; 431 else if (rdev->family >= CHIP_CAYMAN) 432 *value = rdev->config.cayman.max_shader_engines; 433 else if (rdev->family >= CHIP_CEDAR) 434 *value = rdev->config.evergreen.num_ses; 435 else 436 *value = 1; 437 break; 438 case RADEON_INFO_MAX_SH_PER_SE: 439 if (rdev->family >= CHIP_BONAIRE) 440 *value = rdev->config.cik.max_sh_per_se; 441 else if (rdev->family >= CHIP_TAHITI) 442 *value = rdev->config.si.max_sh_per_se; 443 else 444 return -EINVAL; 445 break; 446 case RADEON_INFO_FASTFB_WORKING: 447 *value = rdev->fastfb_working; 448 break; 449 case RADEON_INFO_RING_WORKING: 450 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 451 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 452 return -EFAULT; 453 } 454 switch (*value) { 455 case RADEON_CS_RING_GFX: 456 case RADEON_CS_RING_COMPUTE: 457 *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready; 458 break; 459 case RADEON_CS_RING_DMA: 460 *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready; 461 *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready; 462 break; 463 case RADEON_CS_RING_UVD: 464 *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready; 465 break; 466 case RADEON_CS_RING_VCE: 467 *value = rdev->ring[TN_RING_TYPE_VCE1_INDEX].ready; 468 break; 469 default: 470 return -EINVAL; 471 } 472 break; 473 case RADEON_INFO_SI_TILE_MODE_ARRAY: 474 if (rdev->family >= CHIP_BONAIRE) { 475 value = rdev->config.cik.tile_mode_array; 476 value_size = sizeof(uint32_t)*32; 477 } else if (rdev->family >= CHIP_TAHITI) { 478 value = rdev->config.si.tile_mode_array; 479 value_size = sizeof(uint32_t)*32; 480 } else { 481 DRM_DEBUG_KMS("tile mode array is si+ only!\n"); 482 return -EINVAL; 483 } 484 break; 485 case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY: 486 if (rdev->family >= CHIP_BONAIRE) { 487 value = rdev->config.cik.macrotile_mode_array; 488 value_size = sizeof(uint32_t)*16; 489 } else { 490 DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n"); 491 return -EINVAL; 492 } 493 break; 494 case RADEON_INFO_SI_CP_DMA_COMPUTE: 495 *value = 1; 496 break; 497 case RADEON_INFO_SI_BACKEND_ENABLED_MASK: 498 if (rdev->family >= CHIP_BONAIRE) { 499 *value = rdev->config.cik.backend_enable_mask; 500 } else if (rdev->family >= CHIP_TAHITI) { 501 *value = rdev->config.si.backend_enable_mask; 502 } else { 503 DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n"); 504 } 505 break; 506 case RADEON_INFO_MAX_SCLK: 507 if ((rdev->pm.pm_method == PM_METHOD_DPM) && 508 rdev->pm.dpm_enabled) 509 *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10; 510 else 511 *value = rdev->pm.default_sclk * 10; 512 break; 513 case RADEON_INFO_VCE_FW_VERSION: 514 *value = rdev->vce.fw_version; 515 break; 516 case RADEON_INFO_VCE_FB_VERSION: 517 *value = rdev->vce.fb_version; 518 break; 519 case RADEON_INFO_NUM_BYTES_MOVED: 520 value = (uint32_t*)&value64; 521 value_size = sizeof(uint64_t); 522 value64 = atomic64_read(&rdev->num_bytes_moved); 523 break; 524 case RADEON_INFO_VRAM_USAGE: 525 value = (uint32_t*)&value64; 526 value_size = sizeof(uint64_t); 527 value64 = atomic64_read(&rdev->vram_usage); 528 break; 529 case RADEON_INFO_GTT_USAGE: 530 value = (uint32_t*)&value64; 531 value_size = sizeof(uint64_t); 532 value64 = atomic64_read(&rdev->gtt_usage); 533 break; 534 case RADEON_INFO_ACTIVE_CU_COUNT: 535 if (rdev->family >= CHIP_BONAIRE) 536 *value = rdev->config.cik.active_cus; 537 else if (rdev->family >= CHIP_TAHITI) 538 *value = rdev->config.si.active_cus; 539 else if (rdev->family >= CHIP_CAYMAN) 540 *value = rdev->config.cayman.active_simds; 541 else if (rdev->family >= CHIP_CEDAR) 542 *value = rdev->config.evergreen.active_simds; 543 else if (rdev->family >= CHIP_RV770) 544 *value = rdev->config.rv770.active_simds; 545 else if (rdev->family >= CHIP_R600) 546 *value = rdev->config.r600.active_simds; 547 else 548 *value = 1; 549 break; 550 case RADEON_INFO_CURRENT_GPU_TEMP: 551 /* get temperature in millidegrees C */ 552 if (rdev->asic->pm.get_temperature) 553 *value = radeon_get_temperature(rdev); 554 else 555 *value = 0; 556 break; 557 case RADEON_INFO_CURRENT_GPU_SCLK: 558 /* get sclk in Mhz */ 559 if (rdev->pm.dpm_enabled) 560 *value = radeon_dpm_get_current_sclk(rdev) / 100; 561 else 562 *value = rdev->pm.current_sclk / 100; 563 break; 564 case RADEON_INFO_CURRENT_GPU_MCLK: 565 /* get mclk in Mhz */ 566 if (rdev->pm.dpm_enabled) 567 *value = radeon_dpm_get_current_mclk(rdev) / 100; 568 else 569 *value = rdev->pm.current_mclk / 100; 570 break; 571 case RADEON_INFO_READ_REG: 572 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) { 573 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 574 return -EFAULT; 575 } 576 if (radeon_get_allowed_info_register(rdev, *value, value)) 577 return -EINVAL; 578 break; 579 case RADEON_INFO_VA_UNMAP_WORKING: 580 *value = true; 581 break; 582 default: 583 DRM_DEBUG_KMS("Invalid request %d\n", info->request); 584 return -EINVAL; 585 } 586 if (copy_to_user(value_ptr, (char*)value, value_size)) { 587 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__); 588 return -EFAULT; 589 } 590 return 0; 591} 592 593 594/* 595 * Outdated mess for old drm with Xorg being in charge (void function now). 596 */ 597/** 598 * radeon_driver_firstopen_kms - drm callback for last close 599 * 600 * @dev: drm dev pointer 601 * 602 * Switch vga switcheroo state after last close (all asics). 603 */ 604void radeon_driver_lastclose_kms(struct drm_device *dev) 605{ 606 vga_switcheroo_process_delayed_switch(); 607} 608 609/** 610 * radeon_driver_open_kms - drm callback for open 611 * 612 * @dev: drm dev pointer 613 * @file_priv: drm file 614 * 615 * On device open, init vm on cayman+ (all asics). 616 * Returns 0 on success, error on failure. 617 */ 618int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 619{ 620 struct radeon_device *rdev = dev->dev_private; 621 int r; 622 623 file_priv->driver_priv = NULL; 624 625 r = pm_runtime_get_sync(dev->dev); 626 if (r < 0) 627 return r; 628 629 /* new gpu have virtual address space support */ 630 if (rdev->family >= CHIP_CAYMAN) { 631 struct radeon_fpriv *fpriv; 632 struct radeon_vm *vm; 633 int r; 634 635 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 636 if (unlikely(!fpriv)) { 637 return -ENOMEM; 638 } 639 640 if (rdev->accel_working) { 641 vm = &fpriv->vm; 642 r = radeon_vm_init(rdev, vm); 643 if (r) { 644 kfree(fpriv); 645 return r; 646 } 647 648 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); 649 if (r) { 650 radeon_vm_fini(rdev, vm); 651 kfree(fpriv); 652 return r; 653 } 654 655 /* map the ib pool buffer read only into 656 * virtual address space */ 657 vm->ib_bo_va = radeon_vm_bo_add(rdev, vm, 658 rdev->ring_tmp_bo.bo); 659 r = radeon_vm_bo_set_addr(rdev, vm->ib_bo_va, 660 RADEON_VA_IB_OFFSET, 661 RADEON_VM_PAGE_READABLE | 662 RADEON_VM_PAGE_SNOOPED); 663 if (r) { 664 radeon_vm_fini(rdev, vm); 665 kfree(fpriv); 666 return r; 667 } 668 } 669 file_priv->driver_priv = fpriv; 670 } 671 672 pm_runtime_mark_last_busy(dev->dev); 673 pm_runtime_put_autosuspend(dev->dev); 674 return 0; 675} 676 677/** 678 * radeon_driver_postclose_kms - drm callback for post close 679 * 680 * @dev: drm dev pointer 681 * @file_priv: drm file 682 * 683 * On device post close, tear down vm on cayman+ (all asics). 684 */ 685void radeon_driver_postclose_kms(struct drm_device *dev, 686 struct drm_file *file_priv) 687{ 688 struct radeon_device *rdev = dev->dev_private; 689 690 /* new gpu have virtual address space support */ 691 if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) { 692 struct radeon_fpriv *fpriv = file_priv->driver_priv; 693 struct radeon_vm *vm = &fpriv->vm; 694 int r; 695 696 if (rdev->accel_working) { 697 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); 698 if (!r) { 699 if (vm->ib_bo_va) 700 radeon_vm_bo_rmv(rdev, vm->ib_bo_va); 701 radeon_bo_unreserve(rdev->ring_tmp_bo.bo); 702 } 703 radeon_vm_fini(rdev, vm); 704 } 705 706 kfree(fpriv); 707 file_priv->driver_priv = NULL; 708 } 709} 710 711/** 712 * radeon_driver_preclose_kms - drm callback for pre close 713 * 714 * @dev: drm dev pointer 715 * @file_priv: drm file 716 * 717 * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx 718 * (all asics). 719 */ 720void radeon_driver_preclose_kms(struct drm_device *dev, 721 struct drm_file *file_priv) 722{ 723 struct radeon_device *rdev = dev->dev_private; 724 if (rdev->hyperz_filp == file_priv) 725 rdev->hyperz_filp = NULL; 726 if (rdev->cmask_filp == file_priv) 727 rdev->cmask_filp = NULL; 728 radeon_uvd_free_handles(rdev, file_priv); 729 radeon_vce_free_handles(rdev, file_priv); 730} 731 732/* 733 * VBlank related functions. 734 */ 735/** 736 * radeon_get_vblank_counter_kms - get frame count 737 * 738 * @dev: drm dev pointer 739 * @crtc: crtc to get the frame count from 740 * 741 * Gets the frame count on the requested crtc (all asics). 742 * Returns frame count on success, -EINVAL on failure. 743 */ 744u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc) 745{ 746 struct radeon_device *rdev = dev->dev_private; 747 748 if (crtc < 0 || crtc >= rdev->num_crtc) { 749 DRM_ERROR("Invalid crtc %d\n", crtc); 750 return -EINVAL; 751 } 752 753 return radeon_get_vblank_counter(rdev, crtc); 754} 755 756/** 757 * radeon_enable_vblank_kms - enable vblank interrupt 758 * 759 * @dev: drm dev pointer 760 * @crtc: crtc to enable vblank interrupt for 761 * 762 * Enable the interrupt on the requested crtc (all asics). 763 * Returns 0 on success, -EINVAL on failure. 764 */ 765int radeon_enable_vblank_kms(struct drm_device *dev, int crtc) 766{ 767 struct radeon_device *rdev = dev->dev_private; 768 unsigned long irqflags; 769 int r; 770 771 if (crtc < 0 || crtc >= rdev->num_crtc) { 772 DRM_ERROR("Invalid crtc %d\n", crtc); 773 return -EINVAL; 774 } 775 776 spin_lock_irqsave(&rdev->irq.lock, irqflags); 777 rdev->irq.crtc_vblank_int[crtc] = true; 778 r = radeon_irq_set(rdev); 779 spin_unlock_irqrestore(&rdev->irq.lock, irqflags); 780 return r; 781} 782 783/** 784 * radeon_disable_vblank_kms - disable vblank interrupt 785 * 786 * @dev: drm dev pointer 787 * @crtc: crtc to disable vblank interrupt for 788 * 789 * Disable the interrupt on the requested crtc (all asics). 790 */ 791void radeon_disable_vblank_kms(struct drm_device *dev, int crtc) 792{ 793 struct radeon_device *rdev = dev->dev_private; 794 unsigned long irqflags; 795 796 if (crtc < 0 || crtc >= rdev->num_crtc) { 797 DRM_ERROR("Invalid crtc %d\n", crtc); 798 return; 799 } 800 801 spin_lock_irqsave(&rdev->irq.lock, irqflags); 802 rdev->irq.crtc_vblank_int[crtc] = false; 803 radeon_irq_set(rdev); 804 spin_unlock_irqrestore(&rdev->irq.lock, irqflags); 805} 806 807/** 808 * radeon_get_vblank_timestamp_kms - get vblank timestamp 809 * 810 * @dev: drm dev pointer 811 * @crtc: crtc to get the timestamp for 812 * @max_error: max error 813 * @vblank_time: time value 814 * @flags: flags passed to the driver 815 * 816 * Gets the timestamp on the requested crtc based on the 817 * scanout position. (all asics). 818 * Returns postive status flags on success, negative error on failure. 819 */ 820int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc, 821 int *max_error, 822 struct timeval *vblank_time, 823 unsigned flags) 824{ 825 struct drm_crtc *drmcrtc; 826 struct radeon_device *rdev = dev->dev_private; 827 828 if (crtc < 0 || crtc >= dev->num_crtcs) { 829 DRM_ERROR("Invalid crtc %d\n", crtc); 830 return -EINVAL; 831 } 832 833 /* Get associated drm_crtc: */ 834 drmcrtc = &rdev->mode_info.crtcs[crtc]->base; 835 if (!drmcrtc) 836 return -EINVAL; 837 838 /* Helper routine in DRM core does all the work: */ 839 return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error, 840 vblank_time, flags, 841 drmcrtc, &drmcrtc->hwmode); 842} 843 844#define KMS_INVALID_IOCTL(name) \ 845static int name(struct drm_device *dev, void *data, struct drm_file \ 846 *file_priv) \ 847{ \ 848 DRM_ERROR("invalid ioctl with kms %s\n", __func__); \ 849 return -EINVAL; \ 850} 851 852/* 853 * All these ioctls are invalid in kms world. 854 */ 855KMS_INVALID_IOCTL(radeon_cp_init_kms) 856KMS_INVALID_IOCTL(radeon_cp_start_kms) 857KMS_INVALID_IOCTL(radeon_cp_stop_kms) 858KMS_INVALID_IOCTL(radeon_cp_reset_kms) 859KMS_INVALID_IOCTL(radeon_cp_idle_kms) 860KMS_INVALID_IOCTL(radeon_cp_resume_kms) 861KMS_INVALID_IOCTL(radeon_engine_reset_kms) 862KMS_INVALID_IOCTL(radeon_fullscreen_kms) 863KMS_INVALID_IOCTL(radeon_cp_swap_kms) 864KMS_INVALID_IOCTL(radeon_cp_clear_kms) 865KMS_INVALID_IOCTL(radeon_cp_vertex_kms) 866KMS_INVALID_IOCTL(radeon_cp_indices_kms) 867KMS_INVALID_IOCTL(radeon_cp_texture_kms) 868KMS_INVALID_IOCTL(radeon_cp_stipple_kms) 869KMS_INVALID_IOCTL(radeon_cp_indirect_kms) 870KMS_INVALID_IOCTL(radeon_cp_vertex2_kms) 871KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms) 872KMS_INVALID_IOCTL(radeon_cp_getparam_kms) 873KMS_INVALID_IOCTL(radeon_cp_flip_kms) 874KMS_INVALID_IOCTL(radeon_mem_alloc_kms) 875KMS_INVALID_IOCTL(radeon_mem_free_kms) 876KMS_INVALID_IOCTL(radeon_mem_init_heap_kms) 877KMS_INVALID_IOCTL(radeon_irq_emit_kms) 878KMS_INVALID_IOCTL(radeon_irq_wait_kms) 879KMS_INVALID_IOCTL(radeon_cp_setparam_kms) 880KMS_INVALID_IOCTL(radeon_surface_alloc_kms) 881KMS_INVALID_IOCTL(radeon_surface_free_kms) 882 883 884const struct drm_ioctl_desc radeon_ioctls_kms[] = { 885 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 886 DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 887 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 888 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 889 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH), 890 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH), 891 DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH), 892 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH), 893 DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH), 894 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH), 895 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH), 896 DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH), 897 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH), 898 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH), 899 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 900 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH), 901 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH), 902 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH), 903 DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH), 904 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH), 905 DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free_kms, DRM_AUTH), 906 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 907 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH), 908 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH), 909 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH), 910 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH), 911 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH), 912 /* KMS */ 913 DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 914 DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 915 DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 916 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 917 DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED), 918 DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED), 919 DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 920 DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 921 DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 922 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 923 DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 924 DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 925 DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 926 DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 927 DRM_IOCTL_DEF_DRV(RADEON_GEM_USERPTR, radeon_gem_userptr_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 928}; 929int radeon_max_kms_ioctl = ARRAY_SIZE(radeon_ioctls_kms); 930