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Searched refs:_reg (Results 1 – 47 of 47) sorted by relevance

/linux-4.1.27/drivers/net/ethernet/amd/xgbe/
Dxgbe-common.h1042 #define XGMAC_IOREAD(_pdata, _reg) \ argument
1043 ioread32((_pdata)->xgmac_regs + _reg)
1045 #define XGMAC_IOREAD_BITS(_pdata, _reg, _field) \ argument
1046 GET_BITS(XGMAC_IOREAD((_pdata), _reg), \
1047 _reg##_##_field##_INDEX, \
1048 _reg##_##_field##_WIDTH)
1050 #define XGMAC_IOWRITE(_pdata, _reg, _val) \ argument
1051 iowrite32((_val), (_pdata)->xgmac_regs + _reg)
1053 #define XGMAC_IOWRITE_BITS(_pdata, _reg, _field, _val) \ argument
1055 u32 reg_val = XGMAC_IOREAD((_pdata), _reg); \
[all …]
/linux-4.1.27/drivers/regulator/
Dmc13xxx.h59 #define MC13xxx_DEFINE(prefix, _name, _reg, _vsel_reg, _voltages, _ops) \ argument
70 .reg = prefix ## _reg, \
71 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
77 #define MC13xxx_FIXED_DEFINE(prefix, _name, _reg, _voltages, _ops) \ argument
88 .reg = prefix ## _reg, \
89 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
92 #define MC13xxx_GPO_DEFINE(prefix, _name, _reg, _voltages, _ops) \ argument
103 .reg = prefix ## _reg, \
104 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
107 #define MC13xxx_DEFINE_SW(_name, _reg, _vsel_reg, _voltages, ops) \ argument
[all …]
Dmc13783-regulator.c247 #define MC13783_DEFINE_SW(_name, _reg, _vsel_reg, _voltages) \ argument
248 MC13783_DEFINE(REG, _name, _reg, _vsel_reg, _voltages)
249 #define MC13783_DEFINE_REGU(_name, _reg, _vsel_reg, _voltages) \ argument
250 MC13783_DEFINE(REG, _name, _reg, _vsel_reg, _voltages)
Dpcap-regulator.c107 #define VREG_INFO(_vreg, _reg, _en, _index, _stby, _lowpwr) \ argument
109 .reg = _reg, \
Dtps6524x-regulator.c372 #define __MK_FIELD(_reg, _mask, _shift) \ argument
373 { .reg = (_reg), .mask = (_mask), .shift = (_shift), }
Dda9063-regulator.c33 #define BFIELD(_reg, _mask) \ argument
34 REG_FIELD(_reg, __builtin_ffs((int)_mask) - 1, \
Dmax8998.c198 int *_reg, int *_shift, int *_mask) in max8998_get_voltage_register() argument
253 *_reg = reg; in max8998_get_voltage_register()
Dmax8997.c302 int *_reg, int *_shift, int *_mask) in max8997_get_voltage_register() argument
360 *_reg = reg; in max8997_get_voltage_register()
/linux-4.1.27/drivers/clk/pistachio/
Dclk.h22 #define GATE(_id, _name, _pname, _reg, _shift) \ argument
25 .reg = _reg, \
42 #define MUX(_id, _name, _pnames, _reg, _shift) \ argument
45 .reg = _reg, \
62 #define DIV(_id, _name, _pname, _reg, _width) \ argument
65 .reg = _reg, \
72 #define DIV_F(_id, _name, _pname, _reg, _width, _div_flags) \ argument
75 .reg = _reg, \
122 #define PLL(_id, _name, _pname, _type, _reg, _rates) \ argument
125 .reg_base = _reg, \
[all …]
/linux-4.1.27/arch/arm/mach-mmp/
Dclock.h31 #define APBC_CLK(_name, _reg, _fnclksel, _rate) \ argument
33 .clk_rst = APBC_##_reg, \
39 #define APBC_CLK_OPS(_name, _reg, _fnclksel, _rate, _ops) \ argument
41 .clk_rst = APBC_##_reg, \
47 #define APMU_CLK(_name, _reg, _eval, _rate) \ argument
49 .clk_rst = APMU_##_reg, \
55 #define APMU_CLK_OPS(_name, _reg, _eval, _rate, _ops) \ argument
57 .clk_rst = APMU_##_reg, \
/linux-4.1.27/drivers/reset/sti/
Dreset-stih416.c49 #define STIH416_SRST_CPU(_reg, _bit) \ argument
50 _SYSCFG_RST_CH_NO_ACK(stih416_cpu, _reg, _bit)
52 #define STIH416_SRST_FRONT(_reg, _bit) \ argument
53 _SYSCFG_RST_CH_NO_ACK(stih416_front, _reg, _bit)
55 #define STIH416_SRST_REAR(_reg, _bit) \ argument
56 _SYSCFG_RST_CH_NO_ACK(stih416_rear, _reg, _bit)
58 #define STIH416_SRST_LPM(_reg, _bit) \ argument
59 _SYSCFG_RST_CH_NO_ACK(stih416_lpm, _reg, _bit)
61 #define STIH416_SRST_SBC(_reg, _bit) \ argument
62 _SYSCFG_RST_CH_NO_ACK(stih416_sbc, _reg, _bit)
Dreset-stih415.c34 #define STIH415_SRST_REAR(_reg, _bit) \ argument
35 _SYSCFG_RST_CH_NO_ACK(stih415_rear, _reg, _bit)
37 #define STIH415_SRST_SBC(_reg, _bit) \ argument
38 _SYSCFG_RST_CH_NO_ACK(stih415_sbc, _reg, _bit)
40 #define STIH415_SRST_FRONT(_reg, _bit) \ argument
41 _SYSCFG_RST_CH_NO_ACK(stih415_front, _reg, _bit)
43 #define STIH415_SRST_LPM(_reg, _bit) \ argument
44 _SYSCFG_RST_CH_NO_ACK(stih415_lpm, _reg, _bit)
Dreset-stih407.c60 #define STIH407_SRST_CORE(_reg, _bit) \ argument
61 _SYSCFG_RST_CH_NO_ACK(stih407_core, _reg, _bit)
63 #define STIH407_SRST_SBC(_reg, _bit) \ argument
64 _SYSCFG_RST_CH_NO_ACK(stih407_sbc_reg, _reg, _bit)
66 #define STIH407_SRST_LPM(_reg, _bit) \ argument
67 _SYSCFG_RST_CH_NO_ACK(stih407_lpm, _reg, _bit)
/linux-4.1.27/drivers/media/tuners/
Dmc44s803_priv.h193 #define MC44S803_REG_SM(_val, _reg) \ argument
194 (((_val) << _reg##_S) & (_reg))
197 #define MC44S803_REG_MS(_val, _reg) \ argument
198 (((_val) & (_reg)) >> _reg##_S)
/linux-4.1.27/include/linux/
Dsh_clk.h154 #define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags) \ argument
157 .enable_reg = (void __iomem *)_reg, \
178 #define SH_CLK_DIV6_EXT(_reg, _flags, _parents, \ argument
181 .enable_reg = (void __iomem *)_reg, \
191 #define SH_CLK_DIV6(_parent, _reg, _flags) \ argument
194 .enable_reg = (void __iomem *)_reg, \
208 #define SH_CLK_FSIDIV(_reg, _parent) \ argument
210 .enable_reg = (void __iomem *)_reg, \
Dregmap.h483 #define REG_FIELD(_reg, _lsb, _msb) { \ argument
484 .reg = _reg, \
/linux-4.1.27/drivers/net/phy/
Damd-xgbe-phy.c263 #define XSIR0_IOREAD(_priv, _reg) \ argument
264 ioread16((_priv)->sir0_regs + _reg)
266 #define XSIR0_IOREAD_BITS(_priv, _reg, _field) \ argument
267 GET_BITS(XSIR0_IOREAD((_priv), _reg), \
268 _reg##_##_field##_INDEX, \
269 _reg##_##_field##_WIDTH)
271 #define XSIR0_IOWRITE(_priv, _reg, _val) \ argument
272 iowrite16((_val), (_priv)->sir0_regs + _reg)
274 #define XSIR0_IOWRITE_BITS(_priv, _reg, _field, _val) \ argument
276 u16 reg_val = XSIR0_IOREAD((_priv), _reg); \
[all …]
/linux-4.1.27/drivers/net/wireless/ath/ath5k/
Dath5k.h124 #define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) \ argument
125 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \
126 (((_val) << _flags##_S) & (_flags)), _reg)
128 #define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) \ argument
129 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & \
130 (_mask)) | (_flags), _reg)
132 #define AR5K_REG_ENABLE_BITS(ah, _reg, _flags) \ argument
133 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg)
135 #define AR5K_REG_DISABLE_BITS(ah, _reg, _flags) \ argument
136 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg)
[all …]
/linux-4.1.27/sound/soc/codecs/
Dadau1373.c600 #define DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(_name, _reg) \ argument
602 SOC_DAPM_SINGLE("Left DAC2 Switch", _reg, 7, 1, 0), \
603 SOC_DAPM_SINGLE("Right DAC2 Switch", _reg, 6, 1, 0), \
604 SOC_DAPM_SINGLE("Left DAC1 Switch", _reg, 5, 1, 0), \
605 SOC_DAPM_SINGLE("Right DAC1 Switch", _reg, 4, 1, 0), \
606 SOC_DAPM_SINGLE("Input 4 Bypass Switch", _reg, 3, 1, 0), \
607 SOC_DAPM_SINGLE("Input 3 Bypass Switch", _reg, 2, 1, 0), \
608 SOC_DAPM_SINGLE("Input 2 Bypass Switch", _reg, 1, 1, 0), \
609 SOC_DAPM_SINGLE("Input 1 Bypass Switch", _reg, 0, 1, 0), \
645 #define DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(_name, _reg) \ argument
[all …]
/linux-4.1.27/sound/soc/sh/rcar/
Ddma.c370 #define RDMA_SSI_I_N(addr, i) (addr ##_reg - 0x00300000 + (0x40 * i) + 0x8)
371 #define RDMA_SSI_O_N(addr, i) (addr ##_reg - 0x00300000 + (0x40 * i) + 0xc)
373 #define RDMA_SSIU_I_N(addr, i) (addr ##_reg - 0x00441000 + (0x1000 * i))
374 #define RDMA_SSIU_O_N(addr, i) (addr ##_reg - 0x00441000 + (0x1000 * i))
376 #define RDMA_SSIU_I_P(addr, i) (addr ##_reg - 0x00141000 + (0x1000 * i))
377 #define RDMA_SSIU_O_P(addr, i) (addr ##_reg - 0x00141000 + (0x1000 * i))
379 #define RDMA_SRC_I_N(addr, i) (addr ##_reg - 0x00500000 + (0x400 * i))
380 #define RDMA_SRC_O_N(addr, i) (addr ##_reg - 0x004fc000 + (0x400 * i))
382 #define RDMA_SRC_I_P(addr, i) (addr ##_reg - 0x00200000 + (0x400 * i))
383 #define RDMA_SRC_O_P(addr, i) (addr ##_reg - 0x001fc000 + (0x400 * i))
[all …]
/linux-4.1.27/drivers/net/ethernet/freescale/fs_enet/
Dmac-fec.c67 #define FW(_fecp, _reg, _v) __fs_out32(&(_fecp)->fec_ ## _reg, (_v)) argument
70 #define FR(_fecp, _reg) __fs_in32(&(_fecp)->fec_ ## _reg) argument
73 #define FS(_fecp, _reg, _v) FW(_fecp, _reg, FR(_fecp, _reg) | (_v)) argument
76 #define FC(_fecp, _reg, _v) FW(_fecp, _reg, FR(_fecp, _reg) & ~(_v)) argument
/linux-4.1.27/arch/mips/jz4740/
Dprom.c57 #define UART_REG(_reg) ((void __iomem *)CKSEG1ADDR(JZ4740_UART0_BASE_ADDR + (_reg << 2))) argument
/linux-4.1.27/drivers/media/i2c/smiapp/
Dsmiapp-quirk.h69 #define SMIAPP_MK_QUIRK_REG_8(_reg, _val) \ argument
71 .reg = (u16)_reg, \
/linux-4.1.27/drivers/net/wireless/ath/
Dhw.c24 #define REG_WRITE(_ah, _reg, _val) (common->ops->write)(_ah, _val, _reg) argument
Dkey.c26 #define REG_WRITE(_ah, _reg, _val) (common->ops->write)(_ah, _val, _reg) argument
/linux-4.1.27/arch/sh/kernel/cpu/sh4a/
Dclock-sh7366.c120 #define DIV4(_reg, _bit, _mask, _flags) \ argument
121 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
140 #define MSTP(_parent, _reg, _bit, _flags) \ argument
141 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
Dclock-sh7343.c117 #define DIV4(_reg, _bit, _mask, _flags) \ argument
118 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
137 #define MSTP(_parent, _reg, _bit, _flags) \ argument
138 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
Dclock-sh7722.c120 #define DIV4(_reg, _bit, _mask, _flags) \ argument
121 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
Dclock-sh7734.c72 #define DIV4(_reg, _bit, _mask, _flags) \ argument
73 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
Dclock-sh7723.c123 #define DIV4(_reg, _bit, _mask, _flags) \ argument
124 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
Dclock-sh7724.c162 #define DIV4(_reg, _bit, _mask, _flags) \ argument
163 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
/linux-4.1.27/arch/arm64/kvm/
Dregmap.c28 #define REG_OFFSET(_reg) \ argument
29 (offsetof(struct user_pt_regs, _reg) / sizeof(unsigned long))
/linux-4.1.27/arch/sh/kernel/cpu/sh2a/
Dclock-sh7264.c80 #define DIV4(_reg, _bit, _mask, _flags) \ argument
81 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
Dclock-sh7269.c108 #define DIV4(_reg, _bit, _mask, _flags) \ argument
109 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
/linux-4.1.27/drivers/mfd/
Dtps80031.c83 #define TPS80031_IRQ(_reg, _mask) \ argument
85 .reg_offset = (TPS80031_INT_MSK_LINE_##_reg) - \
126 #define PUPD_DATA(_reg, _pulldown_bit, _pullup_bit) \ argument
128 .reg = TPS80031_CFG_INPUT_PUPD##_reg, \
Drc5t583.c43 #define DEEPSLEEP_INIT(_id, _reg, _pos) \ argument
45 .reg_add = RC5T583_##_reg, \
Dtps6586x.c62 #define TPS6586X_IRQ(_reg, _mask) \ argument
64 .mask_reg = (_reg) - TPS6586X_INT_MASK1, \
/linux-4.1.27/drivers/staging/rtl8723au/include/
Dodm_interface.h44 #define ODM_REG(_name, _pDM_Odm) _cat(_name, _reg)
/linux-4.1.27/drivers/gpu/drm/msm/adreno/
Dadreno_gpu.h30 #define REG_ADRENO_DEFINE(_offset, _reg) [_offset] = (_reg) + 1 argument
/linux-4.1.27/drivers/net/wireless/ath/ath9k/
Dhw.h79 #define REG_WRITE(_ah, _reg, _val) \ argument
80 (_ah)->reg_ops.write((_ah), (_val), (_reg))
82 #define REG_READ(_ah, _reg) \ argument
83 (_ah)->reg_ops.read((_ah), (_reg))
88 #define REG_RMW(_ah, _reg, _set, _clr) \ argument
89 (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr))
Ddebug.c24 #define REG_WRITE_D(_ah, _reg, _val) \ argument
25 ath9k_hw_common(_ah)->ops->write((_ah), (_val), (_reg))
26 #define REG_READ_D(_ah, _reg) \ argument
27 ath9k_hw_common(_ah)->ops->read((_ah), (_reg))
/linux-4.1.27/arch/arm/kvm/
Demulate.c35 #define REG_OFFSET(_reg) \ argument
36 (offsetof(struct kvm_regs, _reg) / sizeof(u32))
/linux-4.1.27/drivers/misc/
Dad525x_dpot.c500 #define DPOT_DEVICE_SHOW(_name, _reg) static ssize_t \ argument
504 return sysfs_show_reg(dev, attr, buf, _reg); \
507 #define DPOT_DEVICE_SET(_name, _reg) static ssize_t \ argument
512 return sysfs_set_reg(dev, attr, buf, count, _reg); \
/linux-4.1.27/arch/arm/mach-shmobile/
Dclock-sh73a0.c222 #define DIV4(_reg, _bit, _mask, _flags) \ argument
223 SH_CLK_DIV4(&pll1_clk, _reg, _bit, _mask, _flags)
559 #define MSTP(_parent, _reg, _bit, _flags) \ argument
560 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
/linux-4.1.27/drivers/net/ethernet/micrel/
Dks8851.c150 #define MK_OP(_byteen, _reg) (BYTE_EN(_byteen) | (_reg) << (8+2) | (_reg) >> 6) argument
/linux-4.1.27/drivers/scsi/csiostor/
Dcsio_wr.c53 #define CSIO_SET_FLBUF_SIZE(_hw, _reg, _val) \ argument
54 csio_wr_reg32((_hw), (_val), SGE_FL_BUFFER_SIZE##_reg##_A)
/linux-4.1.27/arch/ia64/kernel/
Dhead.S64 #define SAVE_ONE_RR(num, _reg, _tmp) \ argument
66 mov _reg=rr[_tmp]