1/* 2 * AMD 10Gb Ethernet driver 3 * 4 * This file is available to you under your choice of the following two 5 * licenses: 6 * 7 * License 1: GPLv2 8 * 9 * Copyright (c) 2014 Advanced Micro Devices, Inc. 10 * 11 * This file is free software; you may copy, redistribute and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation, either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program. If not, see <http://www.gnu.org/licenses/>. 23 * 24 * This file incorporates work covered by the following copyright and 25 * permission notice: 26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 28 * Inc. unless otherwise expressly agreed to in writing between Synopsys 29 * and you. 30 * 31 * The Software IS NOT an item of Licensed Software or Licensed Product 32 * under any End User Software License Agreement or Agreement for Licensed 33 * Product with Synopsys or any supplement thereto. Permission is hereby 34 * granted, free of charge, to any person obtaining a copy of this software 35 * annotated with this license and the Software, to deal in the Software 36 * without restriction, including without limitation the rights to use, 37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 38 * of the Software, and to permit persons to whom the Software is furnished 39 * to do so, subject to the following conditions: 40 * 41 * The above copyright notice and this permission notice shall be included 42 * in all copies or substantial portions of the Software. 43 * 44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 54 * THE POSSIBILITY OF SUCH DAMAGE. 55 * 56 * 57 * License 2: Modified BSD 58 * 59 * Copyright (c) 2014 Advanced Micro Devices, Inc. 60 * All rights reserved. 61 * 62 * Redistribution and use in source and binary forms, with or without 63 * modification, are permitted provided that the following conditions are met: 64 * * Redistributions of source code must retain the above copyright 65 * notice, this list of conditions and the following disclaimer. 66 * * Redistributions in binary form must reproduce the above copyright 67 * notice, this list of conditions and the following disclaimer in the 68 * documentation and/or other materials provided with the distribution. 69 * * Neither the name of Advanced Micro Devices, Inc. nor the 70 * names of its contributors may be used to endorse or promote products 71 * derived from this software without specific prior written permission. 72 * 73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY 77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 83 * 84 * This file incorporates work covered by the following copyright and 85 * permission notice: 86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 88 * Inc. unless otherwise expressly agreed to in writing between Synopsys 89 * and you. 90 * 91 * The Software IS NOT an item of Licensed Software or Licensed Product 92 * under any End User Software License Agreement or Agreement for Licensed 93 * Product with Synopsys or any supplement thereto. Permission is hereby 94 * granted, free of charge, to any person obtaining a copy of this software 95 * annotated with this license and the Software, to deal in the Software 96 * without restriction, including without limitation the rights to use, 97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 98 * of the Software, and to permit persons to whom the Software is furnished 99 * to do so, subject to the following conditions: 100 * 101 * The above copyright notice and this permission notice shall be included 102 * in all copies or substantial portions of the Software. 103 * 104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 114 * THE POSSIBILITY OF SUCH DAMAGE. 115 */ 116 117#ifndef __XGBE_COMMON_H__ 118#define __XGBE_COMMON_H__ 119 120/* DMA register offsets */ 121#define DMA_MR 0x3000 122#define DMA_SBMR 0x3004 123#define DMA_ISR 0x3008 124#define DMA_AXIARCR 0x3010 125#define DMA_AXIAWCR 0x3018 126#define DMA_DSR0 0x3020 127#define DMA_DSR1 0x3024 128 129/* DMA register entry bit positions and sizes */ 130#define DMA_AXIARCR_DRC_INDEX 0 131#define DMA_AXIARCR_DRC_WIDTH 4 132#define DMA_AXIARCR_DRD_INDEX 4 133#define DMA_AXIARCR_DRD_WIDTH 2 134#define DMA_AXIARCR_TEC_INDEX 8 135#define DMA_AXIARCR_TEC_WIDTH 4 136#define DMA_AXIARCR_TED_INDEX 12 137#define DMA_AXIARCR_TED_WIDTH 2 138#define DMA_AXIARCR_THC_INDEX 16 139#define DMA_AXIARCR_THC_WIDTH 4 140#define DMA_AXIARCR_THD_INDEX 20 141#define DMA_AXIARCR_THD_WIDTH 2 142#define DMA_AXIAWCR_DWC_INDEX 0 143#define DMA_AXIAWCR_DWC_WIDTH 4 144#define DMA_AXIAWCR_DWD_INDEX 4 145#define DMA_AXIAWCR_DWD_WIDTH 2 146#define DMA_AXIAWCR_RPC_INDEX 8 147#define DMA_AXIAWCR_RPC_WIDTH 4 148#define DMA_AXIAWCR_RPD_INDEX 12 149#define DMA_AXIAWCR_RPD_WIDTH 2 150#define DMA_AXIAWCR_RHC_INDEX 16 151#define DMA_AXIAWCR_RHC_WIDTH 4 152#define DMA_AXIAWCR_RHD_INDEX 20 153#define DMA_AXIAWCR_RHD_WIDTH 2 154#define DMA_AXIAWCR_TDC_INDEX 24 155#define DMA_AXIAWCR_TDC_WIDTH 4 156#define DMA_AXIAWCR_TDD_INDEX 28 157#define DMA_AXIAWCR_TDD_WIDTH 2 158#define DMA_ISR_MACIS_INDEX 17 159#define DMA_ISR_MACIS_WIDTH 1 160#define DMA_ISR_MTLIS_INDEX 16 161#define DMA_ISR_MTLIS_WIDTH 1 162#define DMA_MR_SWR_INDEX 0 163#define DMA_MR_SWR_WIDTH 1 164#define DMA_SBMR_EAME_INDEX 11 165#define DMA_SBMR_EAME_WIDTH 1 166#define DMA_SBMR_BLEN_256_INDEX 7 167#define DMA_SBMR_BLEN_256_WIDTH 1 168#define DMA_SBMR_UNDEF_INDEX 0 169#define DMA_SBMR_UNDEF_WIDTH 1 170 171/* DMA register values */ 172#define DMA_DSR_RPS_WIDTH 4 173#define DMA_DSR_TPS_WIDTH 4 174#define DMA_DSR_Q_WIDTH (DMA_DSR_RPS_WIDTH + DMA_DSR_TPS_WIDTH) 175#define DMA_DSR0_RPS_START 8 176#define DMA_DSR0_TPS_START 12 177#define DMA_DSRX_FIRST_QUEUE 3 178#define DMA_DSRX_INC 4 179#define DMA_DSRX_QPR 4 180#define DMA_DSRX_RPS_START 0 181#define DMA_DSRX_TPS_START 4 182#define DMA_TPS_STOPPED 0x00 183#define DMA_TPS_SUSPENDED 0x06 184 185/* DMA channel register offsets 186 * Multiple channels can be active. The first channel has registers 187 * that begin at 0x3100. Each subsequent channel has registers that 188 * are accessed using an offset of 0x80 from the previous channel. 189 */ 190#define DMA_CH_BASE 0x3100 191#define DMA_CH_INC 0x80 192 193#define DMA_CH_CR 0x00 194#define DMA_CH_TCR 0x04 195#define DMA_CH_RCR 0x08 196#define DMA_CH_TDLR_HI 0x10 197#define DMA_CH_TDLR_LO 0x14 198#define DMA_CH_RDLR_HI 0x18 199#define DMA_CH_RDLR_LO 0x1c 200#define DMA_CH_TDTR_LO 0x24 201#define DMA_CH_RDTR_LO 0x2c 202#define DMA_CH_TDRLR 0x30 203#define DMA_CH_RDRLR 0x34 204#define DMA_CH_IER 0x38 205#define DMA_CH_RIWT 0x3c 206#define DMA_CH_CATDR_LO 0x44 207#define DMA_CH_CARDR_LO 0x4c 208#define DMA_CH_CATBR_HI 0x50 209#define DMA_CH_CATBR_LO 0x54 210#define DMA_CH_CARBR_HI 0x58 211#define DMA_CH_CARBR_LO 0x5c 212#define DMA_CH_SR 0x60 213 214/* DMA channel register entry bit positions and sizes */ 215#define DMA_CH_CR_PBLX8_INDEX 16 216#define DMA_CH_CR_PBLX8_WIDTH 1 217#define DMA_CH_CR_SPH_INDEX 24 218#define DMA_CH_CR_SPH_WIDTH 1 219#define DMA_CH_IER_AIE_INDEX 15 220#define DMA_CH_IER_AIE_WIDTH 1 221#define DMA_CH_IER_FBEE_INDEX 12 222#define DMA_CH_IER_FBEE_WIDTH 1 223#define DMA_CH_IER_NIE_INDEX 16 224#define DMA_CH_IER_NIE_WIDTH 1 225#define DMA_CH_IER_RBUE_INDEX 7 226#define DMA_CH_IER_RBUE_WIDTH 1 227#define DMA_CH_IER_RIE_INDEX 6 228#define DMA_CH_IER_RIE_WIDTH 1 229#define DMA_CH_IER_RSE_INDEX 8 230#define DMA_CH_IER_RSE_WIDTH 1 231#define DMA_CH_IER_TBUE_INDEX 2 232#define DMA_CH_IER_TBUE_WIDTH 1 233#define DMA_CH_IER_TIE_INDEX 0 234#define DMA_CH_IER_TIE_WIDTH 1 235#define DMA_CH_IER_TXSE_INDEX 1 236#define DMA_CH_IER_TXSE_WIDTH 1 237#define DMA_CH_RCR_PBL_INDEX 16 238#define DMA_CH_RCR_PBL_WIDTH 6 239#define DMA_CH_RCR_RBSZ_INDEX 1 240#define DMA_CH_RCR_RBSZ_WIDTH 14 241#define DMA_CH_RCR_SR_INDEX 0 242#define DMA_CH_RCR_SR_WIDTH 1 243#define DMA_CH_RIWT_RWT_INDEX 0 244#define DMA_CH_RIWT_RWT_WIDTH 8 245#define DMA_CH_SR_FBE_INDEX 12 246#define DMA_CH_SR_FBE_WIDTH 1 247#define DMA_CH_SR_RBU_INDEX 7 248#define DMA_CH_SR_RBU_WIDTH 1 249#define DMA_CH_SR_RI_INDEX 6 250#define DMA_CH_SR_RI_WIDTH 1 251#define DMA_CH_SR_RPS_INDEX 8 252#define DMA_CH_SR_RPS_WIDTH 1 253#define DMA_CH_SR_TBU_INDEX 2 254#define DMA_CH_SR_TBU_WIDTH 1 255#define DMA_CH_SR_TI_INDEX 0 256#define DMA_CH_SR_TI_WIDTH 1 257#define DMA_CH_SR_TPS_INDEX 1 258#define DMA_CH_SR_TPS_WIDTH 1 259#define DMA_CH_TCR_OSP_INDEX 4 260#define DMA_CH_TCR_OSP_WIDTH 1 261#define DMA_CH_TCR_PBL_INDEX 16 262#define DMA_CH_TCR_PBL_WIDTH 6 263#define DMA_CH_TCR_ST_INDEX 0 264#define DMA_CH_TCR_ST_WIDTH 1 265#define DMA_CH_TCR_TSE_INDEX 12 266#define DMA_CH_TCR_TSE_WIDTH 1 267 268/* DMA channel register values */ 269#define DMA_OSP_DISABLE 0x00 270#define DMA_OSP_ENABLE 0x01 271#define DMA_PBL_1 1 272#define DMA_PBL_2 2 273#define DMA_PBL_4 4 274#define DMA_PBL_8 8 275#define DMA_PBL_16 16 276#define DMA_PBL_32 32 277#define DMA_PBL_64 64 /* 8 x 8 */ 278#define DMA_PBL_128 128 /* 8 x 16 */ 279#define DMA_PBL_256 256 /* 8 x 32 */ 280#define DMA_PBL_X8_DISABLE 0x00 281#define DMA_PBL_X8_ENABLE 0x01 282 283/* MAC register offsets */ 284#define MAC_TCR 0x0000 285#define MAC_RCR 0x0004 286#define MAC_PFR 0x0008 287#define MAC_WTR 0x000c 288#define MAC_HTR0 0x0010 289#define MAC_VLANTR 0x0050 290#define MAC_VLANHTR 0x0058 291#define MAC_VLANIR 0x0060 292#define MAC_IVLANIR 0x0064 293#define MAC_RETMR 0x006c 294#define MAC_Q0TFCR 0x0070 295#define MAC_RFCR 0x0090 296#define MAC_RQC0R 0x00a0 297#define MAC_RQC1R 0x00a4 298#define MAC_RQC2R 0x00a8 299#define MAC_RQC3R 0x00ac 300#define MAC_ISR 0x00b0 301#define MAC_IER 0x00b4 302#define MAC_RTSR 0x00b8 303#define MAC_PMTCSR 0x00c0 304#define MAC_RWKPFR 0x00c4 305#define MAC_LPICSR 0x00d0 306#define MAC_LPITCR 0x00d4 307#define MAC_VR 0x0110 308#define MAC_DR 0x0114 309#define MAC_HWF0R 0x011c 310#define MAC_HWF1R 0x0120 311#define MAC_HWF2R 0x0124 312#define MAC_GPIOCR 0x0278 313#define MAC_GPIOSR 0x027c 314#define MAC_MACA0HR 0x0300 315#define MAC_MACA0LR 0x0304 316#define MAC_MACA1HR 0x0308 317#define MAC_MACA1LR 0x030c 318#define MAC_RSSCR 0x0c80 319#define MAC_RSSAR 0x0c88 320#define MAC_RSSDR 0x0c8c 321#define MAC_TSCR 0x0d00 322#define MAC_SSIR 0x0d04 323#define MAC_STSR 0x0d08 324#define MAC_STNR 0x0d0c 325#define MAC_STSUR 0x0d10 326#define MAC_STNUR 0x0d14 327#define MAC_TSAR 0x0d18 328#define MAC_TSSR 0x0d20 329#define MAC_TXSNR 0x0d30 330#define MAC_TXSSR 0x0d34 331 332#define MAC_QTFCR_INC 4 333#define MAC_MACA_INC 4 334#define MAC_HTR_INC 4 335 336#define MAC_RQC2_INC 4 337#define MAC_RQC2_Q_PER_REG 4 338 339/* MAC register entry bit positions and sizes */ 340#define MAC_HWF0R_ADDMACADRSEL_INDEX 18 341#define MAC_HWF0R_ADDMACADRSEL_WIDTH 5 342#define MAC_HWF0R_ARPOFFSEL_INDEX 9 343#define MAC_HWF0R_ARPOFFSEL_WIDTH 1 344#define MAC_HWF0R_EEESEL_INDEX 13 345#define MAC_HWF0R_EEESEL_WIDTH 1 346#define MAC_HWF0R_GMIISEL_INDEX 1 347#define MAC_HWF0R_GMIISEL_WIDTH 1 348#define MAC_HWF0R_MGKSEL_INDEX 7 349#define MAC_HWF0R_MGKSEL_WIDTH 1 350#define MAC_HWF0R_MMCSEL_INDEX 8 351#define MAC_HWF0R_MMCSEL_WIDTH 1 352#define MAC_HWF0R_RWKSEL_INDEX 6 353#define MAC_HWF0R_RWKSEL_WIDTH 1 354#define MAC_HWF0R_RXCOESEL_INDEX 16 355#define MAC_HWF0R_RXCOESEL_WIDTH 1 356#define MAC_HWF0R_SAVLANINS_INDEX 27 357#define MAC_HWF0R_SAVLANINS_WIDTH 1 358#define MAC_HWF0R_SMASEL_INDEX 5 359#define MAC_HWF0R_SMASEL_WIDTH 1 360#define MAC_HWF0R_TSSEL_INDEX 12 361#define MAC_HWF0R_TSSEL_WIDTH 1 362#define MAC_HWF0R_TSSTSSEL_INDEX 25 363#define MAC_HWF0R_TSSTSSEL_WIDTH 2 364#define MAC_HWF0R_TXCOESEL_INDEX 14 365#define MAC_HWF0R_TXCOESEL_WIDTH 1 366#define MAC_HWF0R_VLHASH_INDEX 4 367#define MAC_HWF0R_VLHASH_WIDTH 1 368#define MAC_HWF1R_ADDR64_INDEX 14 369#define MAC_HWF1R_ADDR64_WIDTH 2 370#define MAC_HWF1R_ADVTHWORD_INDEX 13 371#define MAC_HWF1R_ADVTHWORD_WIDTH 1 372#define MAC_HWF1R_DBGMEMA_INDEX 19 373#define MAC_HWF1R_DBGMEMA_WIDTH 1 374#define MAC_HWF1R_DCBEN_INDEX 16 375#define MAC_HWF1R_DCBEN_WIDTH 1 376#define MAC_HWF1R_HASHTBLSZ_INDEX 24 377#define MAC_HWF1R_HASHTBLSZ_WIDTH 3 378#define MAC_HWF1R_L3L4FNUM_INDEX 27 379#define MAC_HWF1R_L3L4FNUM_WIDTH 4 380#define MAC_HWF1R_NUMTC_INDEX 21 381#define MAC_HWF1R_NUMTC_WIDTH 3 382#define MAC_HWF1R_RSSEN_INDEX 20 383#define MAC_HWF1R_RSSEN_WIDTH 1 384#define MAC_HWF1R_RXFIFOSIZE_INDEX 0 385#define MAC_HWF1R_RXFIFOSIZE_WIDTH 5 386#define MAC_HWF1R_SPHEN_INDEX 17 387#define MAC_HWF1R_SPHEN_WIDTH 1 388#define MAC_HWF1R_TSOEN_INDEX 18 389#define MAC_HWF1R_TSOEN_WIDTH 1 390#define MAC_HWF1R_TXFIFOSIZE_INDEX 6 391#define MAC_HWF1R_TXFIFOSIZE_WIDTH 5 392#define MAC_HWF2R_AUXSNAPNUM_INDEX 28 393#define MAC_HWF2R_AUXSNAPNUM_WIDTH 3 394#define MAC_HWF2R_PPSOUTNUM_INDEX 24 395#define MAC_HWF2R_PPSOUTNUM_WIDTH 3 396#define MAC_HWF2R_RXCHCNT_INDEX 12 397#define MAC_HWF2R_RXCHCNT_WIDTH 4 398#define MAC_HWF2R_RXQCNT_INDEX 0 399#define MAC_HWF2R_RXQCNT_WIDTH 4 400#define MAC_HWF2R_TXCHCNT_INDEX 18 401#define MAC_HWF2R_TXCHCNT_WIDTH 4 402#define MAC_HWF2R_TXQCNT_INDEX 6 403#define MAC_HWF2R_TXQCNT_WIDTH 4 404#define MAC_IER_TSIE_INDEX 12 405#define MAC_IER_TSIE_WIDTH 1 406#define MAC_ISR_MMCRXIS_INDEX 9 407#define MAC_ISR_MMCRXIS_WIDTH 1 408#define MAC_ISR_MMCTXIS_INDEX 10 409#define MAC_ISR_MMCTXIS_WIDTH 1 410#define MAC_ISR_PMTIS_INDEX 4 411#define MAC_ISR_PMTIS_WIDTH 1 412#define MAC_ISR_TSIS_INDEX 12 413#define MAC_ISR_TSIS_WIDTH 1 414#define MAC_MACA1HR_AE_INDEX 31 415#define MAC_MACA1HR_AE_WIDTH 1 416#define MAC_PFR_HMC_INDEX 2 417#define MAC_PFR_HMC_WIDTH 1 418#define MAC_PFR_HPF_INDEX 10 419#define MAC_PFR_HPF_WIDTH 1 420#define MAC_PFR_HUC_INDEX 1 421#define MAC_PFR_HUC_WIDTH 1 422#define MAC_PFR_PM_INDEX 4 423#define MAC_PFR_PM_WIDTH 1 424#define MAC_PFR_PR_INDEX 0 425#define MAC_PFR_PR_WIDTH 1 426#define MAC_PFR_VTFE_INDEX 16 427#define MAC_PFR_VTFE_WIDTH 1 428#define MAC_PMTCSR_MGKPKTEN_INDEX 1 429#define MAC_PMTCSR_MGKPKTEN_WIDTH 1 430#define MAC_PMTCSR_PWRDWN_INDEX 0 431#define MAC_PMTCSR_PWRDWN_WIDTH 1 432#define MAC_PMTCSR_RWKFILTRST_INDEX 31 433#define MAC_PMTCSR_RWKFILTRST_WIDTH 1 434#define MAC_PMTCSR_RWKPKTEN_INDEX 2 435#define MAC_PMTCSR_RWKPKTEN_WIDTH 1 436#define MAC_Q0TFCR_PT_INDEX 16 437#define MAC_Q0TFCR_PT_WIDTH 16 438#define MAC_Q0TFCR_TFE_INDEX 1 439#define MAC_Q0TFCR_TFE_WIDTH 1 440#define MAC_RCR_ACS_INDEX 1 441#define MAC_RCR_ACS_WIDTH 1 442#define MAC_RCR_CST_INDEX 2 443#define MAC_RCR_CST_WIDTH 1 444#define MAC_RCR_DCRCC_INDEX 3 445#define MAC_RCR_DCRCC_WIDTH 1 446#define MAC_RCR_HDSMS_INDEX 12 447#define MAC_RCR_HDSMS_WIDTH 3 448#define MAC_RCR_IPC_INDEX 9 449#define MAC_RCR_IPC_WIDTH 1 450#define MAC_RCR_JE_INDEX 8 451#define MAC_RCR_JE_WIDTH 1 452#define MAC_RCR_LM_INDEX 10 453#define MAC_RCR_LM_WIDTH 1 454#define MAC_RCR_RE_INDEX 0 455#define MAC_RCR_RE_WIDTH 1 456#define MAC_RFCR_PFCE_INDEX 8 457#define MAC_RFCR_PFCE_WIDTH 1 458#define MAC_RFCR_RFE_INDEX 0 459#define MAC_RFCR_RFE_WIDTH 1 460#define MAC_RFCR_UP_INDEX 1 461#define MAC_RFCR_UP_WIDTH 1 462#define MAC_RQC0R_RXQ0EN_INDEX 0 463#define MAC_RQC0R_RXQ0EN_WIDTH 2 464#define MAC_RSSAR_ADDRT_INDEX 2 465#define MAC_RSSAR_ADDRT_WIDTH 1 466#define MAC_RSSAR_CT_INDEX 1 467#define MAC_RSSAR_CT_WIDTH 1 468#define MAC_RSSAR_OB_INDEX 0 469#define MAC_RSSAR_OB_WIDTH 1 470#define MAC_RSSAR_RSSIA_INDEX 8 471#define MAC_RSSAR_RSSIA_WIDTH 8 472#define MAC_RSSCR_IP2TE_INDEX 1 473#define MAC_RSSCR_IP2TE_WIDTH 1 474#define MAC_RSSCR_RSSE_INDEX 0 475#define MAC_RSSCR_RSSE_WIDTH 1 476#define MAC_RSSCR_TCP4TE_INDEX 2 477#define MAC_RSSCR_TCP4TE_WIDTH 1 478#define MAC_RSSCR_UDP4TE_INDEX 3 479#define MAC_RSSCR_UDP4TE_WIDTH 1 480#define MAC_RSSDR_DMCH_INDEX 0 481#define MAC_RSSDR_DMCH_WIDTH 4 482#define MAC_SSIR_SNSINC_INDEX 8 483#define MAC_SSIR_SNSINC_WIDTH 8 484#define MAC_SSIR_SSINC_INDEX 16 485#define MAC_SSIR_SSINC_WIDTH 8 486#define MAC_TCR_SS_INDEX 29 487#define MAC_TCR_SS_WIDTH 2 488#define MAC_TCR_TE_INDEX 0 489#define MAC_TCR_TE_WIDTH 1 490#define MAC_TSCR_AV8021ASMEN_INDEX 28 491#define MAC_TSCR_AV8021ASMEN_WIDTH 1 492#define MAC_TSCR_SNAPTYPSEL_INDEX 16 493#define MAC_TSCR_SNAPTYPSEL_WIDTH 2 494#define MAC_TSCR_TSADDREG_INDEX 5 495#define MAC_TSCR_TSADDREG_WIDTH 1 496#define MAC_TSCR_TSCFUPDT_INDEX 1 497#define MAC_TSCR_TSCFUPDT_WIDTH 1 498#define MAC_TSCR_TSCTRLSSR_INDEX 9 499#define MAC_TSCR_TSCTRLSSR_WIDTH 1 500#define MAC_TSCR_TSENA_INDEX 0 501#define MAC_TSCR_TSENA_WIDTH 1 502#define MAC_TSCR_TSENALL_INDEX 8 503#define MAC_TSCR_TSENALL_WIDTH 1 504#define MAC_TSCR_TSEVNTENA_INDEX 14 505#define MAC_TSCR_TSEVNTENA_WIDTH 1 506#define MAC_TSCR_TSINIT_INDEX 2 507#define MAC_TSCR_TSINIT_WIDTH 1 508#define MAC_TSCR_TSIPENA_INDEX 11 509#define MAC_TSCR_TSIPENA_WIDTH 1 510#define MAC_TSCR_TSIPV4ENA_INDEX 13 511#define MAC_TSCR_TSIPV4ENA_WIDTH 1 512#define MAC_TSCR_TSIPV6ENA_INDEX 12 513#define MAC_TSCR_TSIPV6ENA_WIDTH 1 514#define MAC_TSCR_TSMSTRENA_INDEX 15 515#define MAC_TSCR_TSMSTRENA_WIDTH 1 516#define MAC_TSCR_TSVER2ENA_INDEX 10 517#define MAC_TSCR_TSVER2ENA_WIDTH 1 518#define MAC_TSCR_TXTSSTSM_INDEX 24 519#define MAC_TSCR_TXTSSTSM_WIDTH 1 520#define MAC_TSSR_TXTSC_INDEX 15 521#define MAC_TSSR_TXTSC_WIDTH 1 522#define MAC_TXSNR_TXTSSTSMIS_INDEX 31 523#define MAC_TXSNR_TXTSSTSMIS_WIDTH 1 524#define MAC_VLANHTR_VLHT_INDEX 0 525#define MAC_VLANHTR_VLHT_WIDTH 16 526#define MAC_VLANIR_VLTI_INDEX 20 527#define MAC_VLANIR_VLTI_WIDTH 1 528#define MAC_VLANIR_CSVL_INDEX 19 529#define MAC_VLANIR_CSVL_WIDTH 1 530#define MAC_VLANTR_DOVLTC_INDEX 20 531#define MAC_VLANTR_DOVLTC_WIDTH 1 532#define MAC_VLANTR_ERSVLM_INDEX 19 533#define MAC_VLANTR_ERSVLM_WIDTH 1 534#define MAC_VLANTR_ESVL_INDEX 18 535#define MAC_VLANTR_ESVL_WIDTH 1 536#define MAC_VLANTR_ETV_INDEX 16 537#define MAC_VLANTR_ETV_WIDTH 1 538#define MAC_VLANTR_EVLS_INDEX 21 539#define MAC_VLANTR_EVLS_WIDTH 2 540#define MAC_VLANTR_EVLRXS_INDEX 24 541#define MAC_VLANTR_EVLRXS_WIDTH 1 542#define MAC_VLANTR_VL_INDEX 0 543#define MAC_VLANTR_VL_WIDTH 16 544#define MAC_VLANTR_VTHM_INDEX 25 545#define MAC_VLANTR_VTHM_WIDTH 1 546#define MAC_VLANTR_VTIM_INDEX 17 547#define MAC_VLANTR_VTIM_WIDTH 1 548#define MAC_VR_DEVID_INDEX 8 549#define MAC_VR_DEVID_WIDTH 8 550#define MAC_VR_SNPSVER_INDEX 0 551#define MAC_VR_SNPSVER_WIDTH 8 552#define MAC_VR_USERVER_INDEX 16 553#define MAC_VR_USERVER_WIDTH 8 554 555/* MMC register offsets */ 556#define MMC_CR 0x0800 557#define MMC_RISR 0x0804 558#define MMC_TISR 0x0808 559#define MMC_RIER 0x080c 560#define MMC_TIER 0x0810 561#define MMC_TXOCTETCOUNT_GB_LO 0x0814 562#define MMC_TXOCTETCOUNT_GB_HI 0x0818 563#define MMC_TXFRAMECOUNT_GB_LO 0x081c 564#define MMC_TXFRAMECOUNT_GB_HI 0x0820 565#define MMC_TXBROADCASTFRAMES_G_LO 0x0824 566#define MMC_TXBROADCASTFRAMES_G_HI 0x0828 567#define MMC_TXMULTICASTFRAMES_G_LO 0x082c 568#define MMC_TXMULTICASTFRAMES_G_HI 0x0830 569#define MMC_TX64OCTETS_GB_LO 0x0834 570#define MMC_TX64OCTETS_GB_HI 0x0838 571#define MMC_TX65TO127OCTETS_GB_LO 0x083c 572#define MMC_TX65TO127OCTETS_GB_HI 0x0840 573#define MMC_TX128TO255OCTETS_GB_LO 0x0844 574#define MMC_TX128TO255OCTETS_GB_HI 0x0848 575#define MMC_TX256TO511OCTETS_GB_LO 0x084c 576#define MMC_TX256TO511OCTETS_GB_HI 0x0850 577#define MMC_TX512TO1023OCTETS_GB_LO 0x0854 578#define MMC_TX512TO1023OCTETS_GB_HI 0x0858 579#define MMC_TX1024TOMAXOCTETS_GB_LO 0x085c 580#define MMC_TX1024TOMAXOCTETS_GB_HI 0x0860 581#define MMC_TXUNICASTFRAMES_GB_LO 0x0864 582#define MMC_TXUNICASTFRAMES_GB_HI 0x0868 583#define MMC_TXMULTICASTFRAMES_GB_LO 0x086c 584#define MMC_TXMULTICASTFRAMES_GB_HI 0x0870 585#define MMC_TXBROADCASTFRAMES_GB_LO 0x0874 586#define MMC_TXBROADCASTFRAMES_GB_HI 0x0878 587#define MMC_TXUNDERFLOWERROR_LO 0x087c 588#define MMC_TXUNDERFLOWERROR_HI 0x0880 589#define MMC_TXOCTETCOUNT_G_LO 0x0884 590#define MMC_TXOCTETCOUNT_G_HI 0x0888 591#define MMC_TXFRAMECOUNT_G_LO 0x088c 592#define MMC_TXFRAMECOUNT_G_HI 0x0890 593#define MMC_TXPAUSEFRAMES_LO 0x0894 594#define MMC_TXPAUSEFRAMES_HI 0x0898 595#define MMC_TXVLANFRAMES_G_LO 0x089c 596#define MMC_TXVLANFRAMES_G_HI 0x08a0 597#define MMC_RXFRAMECOUNT_GB_LO 0x0900 598#define MMC_RXFRAMECOUNT_GB_HI 0x0904 599#define MMC_RXOCTETCOUNT_GB_LO 0x0908 600#define MMC_RXOCTETCOUNT_GB_HI 0x090c 601#define MMC_RXOCTETCOUNT_G_LO 0x0910 602#define MMC_RXOCTETCOUNT_G_HI 0x0914 603#define MMC_RXBROADCASTFRAMES_G_LO 0x0918 604#define MMC_RXBROADCASTFRAMES_G_HI 0x091c 605#define MMC_RXMULTICASTFRAMES_G_LO 0x0920 606#define MMC_RXMULTICASTFRAMES_G_HI 0x0924 607#define MMC_RXCRCERROR_LO 0x0928 608#define MMC_RXCRCERROR_HI 0x092c 609#define MMC_RXRUNTERROR 0x0930 610#define MMC_RXJABBERERROR 0x0934 611#define MMC_RXUNDERSIZE_G 0x0938 612#define MMC_RXOVERSIZE_G 0x093c 613#define MMC_RX64OCTETS_GB_LO 0x0940 614#define MMC_RX64OCTETS_GB_HI 0x0944 615#define MMC_RX65TO127OCTETS_GB_LO 0x0948 616#define MMC_RX65TO127OCTETS_GB_HI 0x094c 617#define MMC_RX128TO255OCTETS_GB_LO 0x0950 618#define MMC_RX128TO255OCTETS_GB_HI 0x0954 619#define MMC_RX256TO511OCTETS_GB_LO 0x0958 620#define MMC_RX256TO511OCTETS_GB_HI 0x095c 621#define MMC_RX512TO1023OCTETS_GB_LO 0x0960 622#define MMC_RX512TO1023OCTETS_GB_HI 0x0964 623#define MMC_RX1024TOMAXOCTETS_GB_LO 0x0968 624#define MMC_RX1024TOMAXOCTETS_GB_HI 0x096c 625#define MMC_RXUNICASTFRAMES_G_LO 0x0970 626#define MMC_RXUNICASTFRAMES_G_HI 0x0974 627#define MMC_RXLENGTHERROR_LO 0x0978 628#define MMC_RXLENGTHERROR_HI 0x097c 629#define MMC_RXOUTOFRANGETYPE_LO 0x0980 630#define MMC_RXOUTOFRANGETYPE_HI 0x0984 631#define MMC_RXPAUSEFRAMES_LO 0x0988 632#define MMC_RXPAUSEFRAMES_HI 0x098c 633#define MMC_RXFIFOOVERFLOW_LO 0x0990 634#define MMC_RXFIFOOVERFLOW_HI 0x0994 635#define MMC_RXVLANFRAMES_GB_LO 0x0998 636#define MMC_RXVLANFRAMES_GB_HI 0x099c 637#define MMC_RXWATCHDOGERROR 0x09a0 638 639/* MMC register entry bit positions and sizes */ 640#define MMC_CR_CR_INDEX 0 641#define MMC_CR_CR_WIDTH 1 642#define MMC_CR_CSR_INDEX 1 643#define MMC_CR_CSR_WIDTH 1 644#define MMC_CR_ROR_INDEX 2 645#define MMC_CR_ROR_WIDTH 1 646#define MMC_CR_MCF_INDEX 3 647#define MMC_CR_MCF_WIDTH 1 648#define MMC_CR_MCT_INDEX 4 649#define MMC_CR_MCT_WIDTH 2 650#define MMC_RIER_ALL_INTERRUPTS_INDEX 0 651#define MMC_RIER_ALL_INTERRUPTS_WIDTH 23 652#define MMC_RISR_RXFRAMECOUNT_GB_INDEX 0 653#define MMC_RISR_RXFRAMECOUNT_GB_WIDTH 1 654#define MMC_RISR_RXOCTETCOUNT_GB_INDEX 1 655#define MMC_RISR_RXOCTETCOUNT_GB_WIDTH 1 656#define MMC_RISR_RXOCTETCOUNT_G_INDEX 2 657#define MMC_RISR_RXOCTETCOUNT_G_WIDTH 1 658#define MMC_RISR_RXBROADCASTFRAMES_G_INDEX 3 659#define MMC_RISR_RXBROADCASTFRAMES_G_WIDTH 1 660#define MMC_RISR_RXMULTICASTFRAMES_G_INDEX 4 661#define MMC_RISR_RXMULTICASTFRAMES_G_WIDTH 1 662#define MMC_RISR_RXCRCERROR_INDEX 5 663#define MMC_RISR_RXCRCERROR_WIDTH 1 664#define MMC_RISR_RXRUNTERROR_INDEX 6 665#define MMC_RISR_RXRUNTERROR_WIDTH 1 666#define MMC_RISR_RXJABBERERROR_INDEX 7 667#define MMC_RISR_RXJABBERERROR_WIDTH 1 668#define MMC_RISR_RXUNDERSIZE_G_INDEX 8 669#define MMC_RISR_RXUNDERSIZE_G_WIDTH 1 670#define MMC_RISR_RXOVERSIZE_G_INDEX 9 671#define MMC_RISR_RXOVERSIZE_G_WIDTH 1 672#define MMC_RISR_RX64OCTETS_GB_INDEX 10 673#define MMC_RISR_RX64OCTETS_GB_WIDTH 1 674#define MMC_RISR_RX65TO127OCTETS_GB_INDEX 11 675#define MMC_RISR_RX65TO127OCTETS_GB_WIDTH 1 676#define MMC_RISR_RX128TO255OCTETS_GB_INDEX 12 677#define MMC_RISR_RX128TO255OCTETS_GB_WIDTH 1 678#define MMC_RISR_RX256TO511OCTETS_GB_INDEX 13 679#define MMC_RISR_RX256TO511OCTETS_GB_WIDTH 1 680#define MMC_RISR_RX512TO1023OCTETS_GB_INDEX 14 681#define MMC_RISR_RX512TO1023OCTETS_GB_WIDTH 1 682#define MMC_RISR_RX1024TOMAXOCTETS_GB_INDEX 15 683#define MMC_RISR_RX1024TOMAXOCTETS_GB_WIDTH 1 684#define MMC_RISR_RXUNICASTFRAMES_G_INDEX 16 685#define MMC_RISR_RXUNICASTFRAMES_G_WIDTH 1 686#define MMC_RISR_RXLENGTHERROR_INDEX 17 687#define MMC_RISR_RXLENGTHERROR_WIDTH 1 688#define MMC_RISR_RXOUTOFRANGETYPE_INDEX 18 689#define MMC_RISR_RXOUTOFRANGETYPE_WIDTH 1 690#define MMC_RISR_RXPAUSEFRAMES_INDEX 19 691#define MMC_RISR_RXPAUSEFRAMES_WIDTH 1 692#define MMC_RISR_RXFIFOOVERFLOW_INDEX 20 693#define MMC_RISR_RXFIFOOVERFLOW_WIDTH 1 694#define MMC_RISR_RXVLANFRAMES_GB_INDEX 21 695#define MMC_RISR_RXVLANFRAMES_GB_WIDTH 1 696#define MMC_RISR_RXWATCHDOGERROR_INDEX 22 697#define MMC_RISR_RXWATCHDOGERROR_WIDTH 1 698#define MMC_TIER_ALL_INTERRUPTS_INDEX 0 699#define MMC_TIER_ALL_INTERRUPTS_WIDTH 18 700#define MMC_TISR_TXOCTETCOUNT_GB_INDEX 0 701#define MMC_TISR_TXOCTETCOUNT_GB_WIDTH 1 702#define MMC_TISR_TXFRAMECOUNT_GB_INDEX 1 703#define MMC_TISR_TXFRAMECOUNT_GB_WIDTH 1 704#define MMC_TISR_TXBROADCASTFRAMES_G_INDEX 2 705#define MMC_TISR_TXBROADCASTFRAMES_G_WIDTH 1 706#define MMC_TISR_TXMULTICASTFRAMES_G_INDEX 3 707#define MMC_TISR_TXMULTICASTFRAMES_G_WIDTH 1 708#define MMC_TISR_TX64OCTETS_GB_INDEX 4 709#define MMC_TISR_TX64OCTETS_GB_WIDTH 1 710#define MMC_TISR_TX65TO127OCTETS_GB_INDEX 5 711#define MMC_TISR_TX65TO127OCTETS_GB_WIDTH 1 712#define MMC_TISR_TX128TO255OCTETS_GB_INDEX 6 713#define MMC_TISR_TX128TO255OCTETS_GB_WIDTH 1 714#define MMC_TISR_TX256TO511OCTETS_GB_INDEX 7 715#define MMC_TISR_TX256TO511OCTETS_GB_WIDTH 1 716#define MMC_TISR_TX512TO1023OCTETS_GB_INDEX 8 717#define MMC_TISR_TX512TO1023OCTETS_GB_WIDTH 1 718#define MMC_TISR_TX1024TOMAXOCTETS_GB_INDEX 9 719#define MMC_TISR_TX1024TOMAXOCTETS_GB_WIDTH 1 720#define MMC_TISR_TXUNICASTFRAMES_GB_INDEX 10 721#define MMC_TISR_TXUNICASTFRAMES_GB_WIDTH 1 722#define MMC_TISR_TXMULTICASTFRAMES_GB_INDEX 11 723#define MMC_TISR_TXMULTICASTFRAMES_GB_WIDTH 1 724#define MMC_TISR_TXBROADCASTFRAMES_GB_INDEX 12 725#define MMC_TISR_TXBROADCASTFRAMES_GB_WIDTH 1 726#define MMC_TISR_TXUNDERFLOWERROR_INDEX 13 727#define MMC_TISR_TXUNDERFLOWERROR_WIDTH 1 728#define MMC_TISR_TXOCTETCOUNT_G_INDEX 14 729#define MMC_TISR_TXOCTETCOUNT_G_WIDTH 1 730#define MMC_TISR_TXFRAMECOUNT_G_INDEX 15 731#define MMC_TISR_TXFRAMECOUNT_G_WIDTH 1 732#define MMC_TISR_TXPAUSEFRAMES_INDEX 16 733#define MMC_TISR_TXPAUSEFRAMES_WIDTH 1 734#define MMC_TISR_TXVLANFRAMES_G_INDEX 17 735#define MMC_TISR_TXVLANFRAMES_G_WIDTH 1 736 737/* MTL register offsets */ 738#define MTL_OMR 0x1000 739#define MTL_FDCR 0x1008 740#define MTL_FDSR 0x100c 741#define MTL_FDDR 0x1010 742#define MTL_ISR 0x1020 743#define MTL_RQDCM0R 0x1030 744#define MTL_TCPM0R 0x1040 745#define MTL_TCPM1R 0x1044 746 747#define MTL_RQDCM_INC 4 748#define MTL_RQDCM_Q_PER_REG 4 749#define MTL_TCPM_INC 4 750#define MTL_TCPM_TC_PER_REG 4 751 752/* MTL register entry bit positions and sizes */ 753#define MTL_OMR_ETSALG_INDEX 5 754#define MTL_OMR_ETSALG_WIDTH 2 755#define MTL_OMR_RAA_INDEX 2 756#define MTL_OMR_RAA_WIDTH 1 757 758/* MTL queue register offsets 759 * Multiple queues can be active. The first queue has registers 760 * that begin at 0x1100. Each subsequent queue has registers that 761 * are accessed using an offset of 0x80 from the previous queue. 762 */ 763#define MTL_Q_BASE 0x1100 764#define MTL_Q_INC 0x80 765 766#define MTL_Q_TQOMR 0x00 767#define MTL_Q_TQUR 0x04 768#define MTL_Q_TQDR 0x08 769#define MTL_Q_RQOMR 0x40 770#define MTL_Q_RQMPOCR 0x44 771#define MTL_Q_RQDR 0x4c 772#define MTL_Q_RQFCR 0x50 773#define MTL_Q_IER 0x70 774#define MTL_Q_ISR 0x74 775 776/* MTL queue register entry bit positions and sizes */ 777#define MTL_Q_RQFCR_RFA_INDEX 1 778#define MTL_Q_RQFCR_RFA_WIDTH 6 779#define MTL_Q_RQFCR_RFD_INDEX 17 780#define MTL_Q_RQFCR_RFD_WIDTH 6 781#define MTL_Q_RQOMR_EHFC_INDEX 7 782#define MTL_Q_RQOMR_EHFC_WIDTH 1 783#define MTL_Q_RQOMR_RQS_INDEX 16 784#define MTL_Q_RQOMR_RQS_WIDTH 9 785#define MTL_Q_RQOMR_RSF_INDEX 5 786#define MTL_Q_RQOMR_RSF_WIDTH 1 787#define MTL_Q_RQOMR_RTC_INDEX 0 788#define MTL_Q_RQOMR_RTC_WIDTH 2 789#define MTL_Q_TQOMR_FTQ_INDEX 0 790#define MTL_Q_TQOMR_FTQ_WIDTH 1 791#define MTL_Q_TQOMR_Q2TCMAP_INDEX 8 792#define MTL_Q_TQOMR_Q2TCMAP_WIDTH 3 793#define MTL_Q_TQOMR_TQS_INDEX 16 794#define MTL_Q_TQOMR_TQS_WIDTH 10 795#define MTL_Q_TQOMR_TSF_INDEX 1 796#define MTL_Q_TQOMR_TSF_WIDTH 1 797#define MTL_Q_TQOMR_TTC_INDEX 4 798#define MTL_Q_TQOMR_TTC_WIDTH 3 799#define MTL_Q_TQOMR_TXQEN_INDEX 2 800#define MTL_Q_TQOMR_TXQEN_WIDTH 2 801 802/* MTL queue register value */ 803#define MTL_RSF_DISABLE 0x00 804#define MTL_RSF_ENABLE 0x01 805#define MTL_TSF_DISABLE 0x00 806#define MTL_TSF_ENABLE 0x01 807 808#define MTL_RX_THRESHOLD_64 0x00 809#define MTL_RX_THRESHOLD_96 0x02 810#define MTL_RX_THRESHOLD_128 0x03 811#define MTL_TX_THRESHOLD_32 0x01 812#define MTL_TX_THRESHOLD_64 0x00 813#define MTL_TX_THRESHOLD_96 0x02 814#define MTL_TX_THRESHOLD_128 0x03 815#define MTL_TX_THRESHOLD_192 0x04 816#define MTL_TX_THRESHOLD_256 0x05 817#define MTL_TX_THRESHOLD_384 0x06 818#define MTL_TX_THRESHOLD_512 0x07 819 820#define MTL_ETSALG_WRR 0x00 821#define MTL_ETSALG_WFQ 0x01 822#define MTL_ETSALG_DWRR 0x02 823#define MTL_RAA_SP 0x00 824#define MTL_RAA_WSP 0x01 825 826#define MTL_Q_DISABLED 0x00 827#define MTL_Q_ENABLED 0x02 828 829/* MTL traffic class register offsets 830 * Multiple traffic classes can be active. The first class has registers 831 * that begin at 0x1100. Each subsequent queue has registers that 832 * are accessed using an offset of 0x80 from the previous queue. 833 */ 834#define MTL_TC_BASE MTL_Q_BASE 835#define MTL_TC_INC MTL_Q_INC 836 837#define MTL_TC_ETSCR 0x10 838#define MTL_TC_ETSSR 0x14 839#define MTL_TC_QWR 0x18 840 841/* MTL traffic class register entry bit positions and sizes */ 842#define MTL_TC_ETSCR_TSA_INDEX 0 843#define MTL_TC_ETSCR_TSA_WIDTH 2 844#define MTL_TC_QWR_QW_INDEX 0 845#define MTL_TC_QWR_QW_WIDTH 21 846 847/* MTL traffic class register value */ 848#define MTL_TSA_SP 0x00 849#define MTL_TSA_ETS 0x02 850 851/* PCS MMD select register offset 852 * The MMD select register is used for accessing PCS registers 853 * when the underlying APB3 interface is using indirect addressing. 854 * Indirect addressing requires accessing registers in two phases, 855 * an address phase and a data phase. The address phases requires 856 * writing an address selection value to the MMD select regiesters. 857 */ 858#define PCS_MMD_SELECT 0xff 859 860/* Descriptor/Packet entry bit positions and sizes */ 861#define RX_PACKET_ERRORS_CRC_INDEX 2 862#define RX_PACKET_ERRORS_CRC_WIDTH 1 863#define RX_PACKET_ERRORS_FRAME_INDEX 3 864#define RX_PACKET_ERRORS_FRAME_WIDTH 1 865#define RX_PACKET_ERRORS_LENGTH_INDEX 0 866#define RX_PACKET_ERRORS_LENGTH_WIDTH 1 867#define RX_PACKET_ERRORS_OVERRUN_INDEX 1 868#define RX_PACKET_ERRORS_OVERRUN_WIDTH 1 869 870#define RX_PACKET_ATTRIBUTES_CSUM_DONE_INDEX 0 871#define RX_PACKET_ATTRIBUTES_CSUM_DONE_WIDTH 1 872#define RX_PACKET_ATTRIBUTES_VLAN_CTAG_INDEX 1 873#define RX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH 1 874#define RX_PACKET_ATTRIBUTES_INCOMPLETE_INDEX 2 875#define RX_PACKET_ATTRIBUTES_INCOMPLETE_WIDTH 1 876#define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_INDEX 3 877#define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_WIDTH 1 878#define RX_PACKET_ATTRIBUTES_CONTEXT_INDEX 4 879#define RX_PACKET_ATTRIBUTES_CONTEXT_WIDTH 1 880#define RX_PACKET_ATTRIBUTES_RX_TSTAMP_INDEX 5 881#define RX_PACKET_ATTRIBUTES_RX_TSTAMP_WIDTH 1 882#define RX_PACKET_ATTRIBUTES_RSS_HASH_INDEX 6 883#define RX_PACKET_ATTRIBUTES_RSS_HASH_WIDTH 1 884 885#define RX_NORMAL_DESC0_OVT_INDEX 0 886#define RX_NORMAL_DESC0_OVT_WIDTH 16 887#define RX_NORMAL_DESC2_HL_INDEX 0 888#define RX_NORMAL_DESC2_HL_WIDTH 10 889#define RX_NORMAL_DESC3_CDA_INDEX 27 890#define RX_NORMAL_DESC3_CDA_WIDTH 1 891#define RX_NORMAL_DESC3_CTXT_INDEX 30 892#define RX_NORMAL_DESC3_CTXT_WIDTH 1 893#define RX_NORMAL_DESC3_ES_INDEX 15 894#define RX_NORMAL_DESC3_ES_WIDTH 1 895#define RX_NORMAL_DESC3_ETLT_INDEX 16 896#define RX_NORMAL_DESC3_ETLT_WIDTH 4 897#define RX_NORMAL_DESC3_FD_INDEX 29 898#define RX_NORMAL_DESC3_FD_WIDTH 1 899#define RX_NORMAL_DESC3_INTE_INDEX 30 900#define RX_NORMAL_DESC3_INTE_WIDTH 1 901#define RX_NORMAL_DESC3_L34T_INDEX 20 902#define RX_NORMAL_DESC3_L34T_WIDTH 4 903#define RX_NORMAL_DESC3_LD_INDEX 28 904#define RX_NORMAL_DESC3_LD_WIDTH 1 905#define RX_NORMAL_DESC3_OWN_INDEX 31 906#define RX_NORMAL_DESC3_OWN_WIDTH 1 907#define RX_NORMAL_DESC3_PL_INDEX 0 908#define RX_NORMAL_DESC3_PL_WIDTH 14 909#define RX_NORMAL_DESC3_RSV_INDEX 26 910#define RX_NORMAL_DESC3_RSV_WIDTH 1 911 912#define RX_DESC3_L34T_IPV4_TCP 1 913#define RX_DESC3_L34T_IPV4_UDP 2 914#define RX_DESC3_L34T_IPV4_ICMP 3 915#define RX_DESC3_L34T_IPV6_TCP 9 916#define RX_DESC3_L34T_IPV6_UDP 10 917#define RX_DESC3_L34T_IPV6_ICMP 11 918 919#define RX_CONTEXT_DESC3_TSA_INDEX 4 920#define RX_CONTEXT_DESC3_TSA_WIDTH 1 921#define RX_CONTEXT_DESC3_TSD_INDEX 6 922#define RX_CONTEXT_DESC3_TSD_WIDTH 1 923 924#define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_INDEX 0 925#define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_WIDTH 1 926#define TX_PACKET_ATTRIBUTES_TSO_ENABLE_INDEX 1 927#define TX_PACKET_ATTRIBUTES_TSO_ENABLE_WIDTH 1 928#define TX_PACKET_ATTRIBUTES_VLAN_CTAG_INDEX 2 929#define TX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH 1 930#define TX_PACKET_ATTRIBUTES_PTP_INDEX 3 931#define TX_PACKET_ATTRIBUTES_PTP_WIDTH 1 932 933#define TX_CONTEXT_DESC2_MSS_INDEX 0 934#define TX_CONTEXT_DESC2_MSS_WIDTH 15 935#define TX_CONTEXT_DESC3_CTXT_INDEX 30 936#define TX_CONTEXT_DESC3_CTXT_WIDTH 1 937#define TX_CONTEXT_DESC3_TCMSSV_INDEX 26 938#define TX_CONTEXT_DESC3_TCMSSV_WIDTH 1 939#define TX_CONTEXT_DESC3_VLTV_INDEX 16 940#define TX_CONTEXT_DESC3_VLTV_WIDTH 1 941#define TX_CONTEXT_DESC3_VT_INDEX 0 942#define TX_CONTEXT_DESC3_VT_WIDTH 16 943 944#define TX_NORMAL_DESC2_HL_B1L_INDEX 0 945#define TX_NORMAL_DESC2_HL_B1L_WIDTH 14 946#define TX_NORMAL_DESC2_IC_INDEX 31 947#define TX_NORMAL_DESC2_IC_WIDTH 1 948#define TX_NORMAL_DESC2_TTSE_INDEX 30 949#define TX_NORMAL_DESC2_TTSE_WIDTH 1 950#define TX_NORMAL_DESC2_VTIR_INDEX 14 951#define TX_NORMAL_DESC2_VTIR_WIDTH 2 952#define TX_NORMAL_DESC3_CIC_INDEX 16 953#define TX_NORMAL_DESC3_CIC_WIDTH 2 954#define TX_NORMAL_DESC3_CPC_INDEX 26 955#define TX_NORMAL_DESC3_CPC_WIDTH 2 956#define TX_NORMAL_DESC3_CTXT_INDEX 30 957#define TX_NORMAL_DESC3_CTXT_WIDTH 1 958#define TX_NORMAL_DESC3_FD_INDEX 29 959#define TX_NORMAL_DESC3_FD_WIDTH 1 960#define TX_NORMAL_DESC3_FL_INDEX 0 961#define TX_NORMAL_DESC3_FL_WIDTH 15 962#define TX_NORMAL_DESC3_LD_INDEX 28 963#define TX_NORMAL_DESC3_LD_WIDTH 1 964#define TX_NORMAL_DESC3_OWN_INDEX 31 965#define TX_NORMAL_DESC3_OWN_WIDTH 1 966#define TX_NORMAL_DESC3_TCPHDRLEN_INDEX 19 967#define TX_NORMAL_DESC3_TCPHDRLEN_WIDTH 4 968#define TX_NORMAL_DESC3_TCPPL_INDEX 0 969#define TX_NORMAL_DESC3_TCPPL_WIDTH 18 970#define TX_NORMAL_DESC3_TSE_INDEX 18 971#define TX_NORMAL_DESC3_TSE_WIDTH 1 972 973#define TX_NORMAL_DESC2_VLAN_INSERT 0x2 974 975/* MDIO undefined or vendor specific registers */ 976#ifndef MDIO_AN_COMP_STAT 977#define MDIO_AN_COMP_STAT 0x0030 978#endif 979 980/* Bit setting and getting macros 981 * The get macro will extract the current bit field value from within 982 * the variable 983 * 984 * The set macro will clear the current bit field value within the 985 * variable and then set the bit field of the variable to the 986 * specified value 987 */ 988#define GET_BITS(_var, _index, _width) \ 989 (((_var) >> (_index)) & ((0x1 << (_width)) - 1)) 990 991#define SET_BITS(_var, _index, _width, _val) \ 992do { \ 993 (_var) &= ~(((0x1 << (_width)) - 1) << (_index)); \ 994 (_var) |= (((_val) & ((0x1 << (_width)) - 1)) << (_index)); \ 995} while (0) 996 997#define GET_BITS_LE(_var, _index, _width) \ 998 ((le32_to_cpu((_var)) >> (_index)) & ((0x1 << (_width)) - 1)) 999 1000#define SET_BITS_LE(_var, _index, _width, _val) \ 1001do { \ 1002 (_var) &= cpu_to_le32(~(((0x1 << (_width)) - 1) << (_index))); \ 1003 (_var) |= cpu_to_le32((((_val) & \ 1004 ((0x1 << (_width)) - 1)) << (_index))); \ 1005} while (0) 1006 1007/* Bit setting and getting macros based on register fields 1008 * The get macro uses the bit field definitions formed using the input 1009 * names to extract the current bit field value from within the 1010 * variable 1011 * 1012 * The set macro uses the bit field definitions formed using the input 1013 * names to set the bit field of the variable to the specified value 1014 */ 1015#define XGMAC_GET_BITS(_var, _prefix, _field) \ 1016 GET_BITS((_var), \ 1017 _prefix##_##_field##_INDEX, \ 1018 _prefix##_##_field##_WIDTH) 1019 1020#define XGMAC_SET_BITS(_var, _prefix, _field, _val) \ 1021 SET_BITS((_var), \ 1022 _prefix##_##_field##_INDEX, \ 1023 _prefix##_##_field##_WIDTH, (_val)) 1024 1025#define XGMAC_GET_BITS_LE(_var, _prefix, _field) \ 1026 GET_BITS_LE((_var), \ 1027 _prefix##_##_field##_INDEX, \ 1028 _prefix##_##_field##_WIDTH) 1029 1030#define XGMAC_SET_BITS_LE(_var, _prefix, _field, _val) \ 1031 SET_BITS_LE((_var), \ 1032 _prefix##_##_field##_INDEX, \ 1033 _prefix##_##_field##_WIDTH, (_val)) 1034 1035/* Macros for reading or writing registers 1036 * The ioread macros will get bit fields or full values using the 1037 * register definitions formed using the input names 1038 * 1039 * The iowrite macros will set bit fields or full values using the 1040 * register definitions formed using the input names 1041 */ 1042#define XGMAC_IOREAD(_pdata, _reg) \ 1043 ioread32((_pdata)->xgmac_regs + _reg) 1044 1045#define XGMAC_IOREAD_BITS(_pdata, _reg, _field) \ 1046 GET_BITS(XGMAC_IOREAD((_pdata), _reg), \ 1047 _reg##_##_field##_INDEX, \ 1048 _reg##_##_field##_WIDTH) 1049 1050#define XGMAC_IOWRITE(_pdata, _reg, _val) \ 1051 iowrite32((_val), (_pdata)->xgmac_regs + _reg) 1052 1053#define XGMAC_IOWRITE_BITS(_pdata, _reg, _field, _val) \ 1054do { \ 1055 u32 reg_val = XGMAC_IOREAD((_pdata), _reg); \ 1056 SET_BITS(reg_val, \ 1057 _reg##_##_field##_INDEX, \ 1058 _reg##_##_field##_WIDTH, (_val)); \ 1059 XGMAC_IOWRITE((_pdata), _reg, reg_val); \ 1060} while (0) 1061 1062/* Macros for reading or writing MTL queue or traffic class registers 1063 * Similar to the standard read and write macros except that the 1064 * base register value is calculated by the queue or traffic class number 1065 */ 1066#define XGMAC_MTL_IOREAD(_pdata, _n, _reg) \ 1067 ioread32((_pdata)->xgmac_regs + \ 1068 MTL_Q_BASE + ((_n) * MTL_Q_INC) + _reg) 1069 1070#define XGMAC_MTL_IOREAD_BITS(_pdata, _n, _reg, _field) \ 1071 GET_BITS(XGMAC_MTL_IOREAD((_pdata), (_n), _reg), \ 1072 _reg##_##_field##_INDEX, \ 1073 _reg##_##_field##_WIDTH) 1074 1075#define XGMAC_MTL_IOWRITE(_pdata, _n, _reg, _val) \ 1076 iowrite32((_val), (_pdata)->xgmac_regs + \ 1077 MTL_Q_BASE + ((_n) * MTL_Q_INC) + _reg) 1078 1079#define XGMAC_MTL_IOWRITE_BITS(_pdata, _n, _reg, _field, _val) \ 1080do { \ 1081 u32 reg_val = XGMAC_MTL_IOREAD((_pdata), (_n), _reg); \ 1082 SET_BITS(reg_val, \ 1083 _reg##_##_field##_INDEX, \ 1084 _reg##_##_field##_WIDTH, (_val)); \ 1085 XGMAC_MTL_IOWRITE((_pdata), (_n), _reg, reg_val); \ 1086} while (0) 1087 1088/* Macros for reading or writing DMA channel registers 1089 * Similar to the standard read and write macros except that the 1090 * base register value is obtained from the ring 1091 */ 1092#define XGMAC_DMA_IOREAD(_channel, _reg) \ 1093 ioread32((_channel)->dma_regs + _reg) 1094 1095#define XGMAC_DMA_IOREAD_BITS(_channel, _reg, _field) \ 1096 GET_BITS(XGMAC_DMA_IOREAD((_channel), _reg), \ 1097 _reg##_##_field##_INDEX, \ 1098 _reg##_##_field##_WIDTH) 1099 1100#define XGMAC_DMA_IOWRITE(_channel, _reg, _val) \ 1101 iowrite32((_val), (_channel)->dma_regs + _reg) 1102 1103#define XGMAC_DMA_IOWRITE_BITS(_channel, _reg, _field, _val) \ 1104do { \ 1105 u32 reg_val = XGMAC_DMA_IOREAD((_channel), _reg); \ 1106 SET_BITS(reg_val, \ 1107 _reg##_##_field##_INDEX, \ 1108 _reg##_##_field##_WIDTH, (_val)); \ 1109 XGMAC_DMA_IOWRITE((_channel), _reg, reg_val); \ 1110} while (0) 1111 1112/* Macros for building, reading or writing register values or bits 1113 * within the register values of XPCS registers. 1114 */ 1115#define XPCS_IOWRITE(_pdata, _off, _val) \ 1116 iowrite32(_val, (_pdata)->xpcs_regs + (_off)) 1117 1118#define XPCS_IOREAD(_pdata, _off) \ 1119 ioread32((_pdata)->xpcs_regs + (_off)) 1120 1121/* Macros for building, reading or writing register values or bits 1122 * using MDIO. Different from above because of the use of standardized 1123 * Linux include values. No shifting is performed with the bit 1124 * operations, everything works on mask values. 1125 */ 1126#define XMDIO_READ(_pdata, _mmd, _reg) \ 1127 ((_pdata)->hw_if.read_mmd_regs((_pdata), 0, \ 1128 MII_ADDR_C45 | (_mmd << 16) | ((_reg) & 0xffff))) 1129 1130#define XMDIO_READ_BITS(_pdata, _mmd, _reg, _mask) \ 1131 (XMDIO_READ((_pdata), _mmd, _reg) & _mask) 1132 1133#define XMDIO_WRITE(_pdata, _mmd, _reg, _val) \ 1134 ((_pdata)->hw_if.write_mmd_regs((_pdata), 0, \ 1135 MII_ADDR_C45 | (_mmd << 16) | ((_reg) & 0xffff), (_val))) 1136 1137#define XMDIO_WRITE_BITS(_pdata, _mmd, _reg, _mask, _val) \ 1138do { \ 1139 u32 mmd_val = XMDIO_READ((_pdata), _mmd, _reg); \ 1140 mmd_val &= ~_mask; \ 1141 mmd_val |= (_val); \ 1142 XMDIO_WRITE((_pdata), _mmd, _reg, mmd_val); \ 1143} while (0) 1144 1145#endif 1146