Searched refs:__clk_get_rate (Results 1 – 24 of 24) sorted by relevance
67 sdrcrate = __clk_get_rate(sdrc_ick_p); in omap3_core_dpll_m2_set_rate()68 clkrate = __clk_get_rate(hw->clk); in omap3_core_dpll_m2_set_rate()86 _mpurate = __clk_get_rate(arm_fck_p) / CYCLES_PER_MHZ; in omap3_core_dpll_m2_set_rate()
77 fint = __clk_get_rate(__clk_get_parent(clk->hw.clk)) / n; in _dpll_test_fint()255 return __clk_get_rate(dd->clk_bypass); in omap2_get_dpll_rate()263 dpll_clk = (long long) __clk_get_rate(dd->clk_ref) * dpll_mult; in omap2_get_dpll_rate()302 ref_rate = __clk_get_rate(dd->clk_ref); in omap2_dpll_round_rate()
94 fint = __clk_get_rate(clk->dpll_data->clk_ref) / n; in _omap3_dpll_compute_freqsel()246 clkinp = __clk_get_rate(__clk_get_parent(clk->hw.clk)); in _lookup_dco()272 clkinp = __clk_get_rate(__clk_get_parent(clk->hw.clk)); in _lookup_sddiv()432 if (__clk_get_rate(hw->clk) == __clk_get_rate(dd->clk_bypass)) { in omap3_noncore_dpll_enable()491 if (__clk_get_rate(dd->clk_bypass) == rate && in omap3_noncore_dpll_determine_rate()
96 fint = __clk_get_rate(dd->clk_ref) / (dd->last_rounded_n + 1); in omap4_dpll_lpmode_recalc()220 if (__clk_get_rate(dd->clk_bypass) == rate && in omap4_dpll_regm4xen_determine_rate()
242 parent_rate = __clk_get_rate(parent); in omap2_clksel_round_rate_div()432 __clk_get_rate(hw->clk)); in omap2_clksel_set_rate()
124 parent_rate = __clk_get_rate(parent); in _filter_clk_table()234 parent_rate = __clk_get_rate(parent); in mmp_clk_mix_determine_rate()249 parent_rate = __clk_get_rate(parent); in mmp_clk_mix_determine_rate()397 parent_rate = __clk_get_rate(parent); in mmp_clk_set_rate()412 parent_rate = __clk_get_rate(parent); in mmp_clk_set_rate()
47 rate = __clk_get_rate(clk); in mmp_clk_gate_enable()
89 *best_parent_rate = __clk_get_rate(parent); in clk_composite_determine_rate()100 parent_rate = __clk_get_rate(parent); in clk_composite_determine_rate()
665 unsigned long __clk_get_rate(struct clk *clk) in __clk_get_rate() function672 EXPORT_SYMBOL_GPL(__clk_get_rate);
272 drate = __clk_get_rate(hw->clk); in rockchip_rk3066_pll_init()305 prate = __clk_get_rate(parent); in rockchip_rk3066_pll_init()
1013 return __clk_get_rate(hw->clk); in kona_peri_clk_round_rate()1045 parent_rate = __clk_get_rate(current_parent); in kona_peri_clk_determine_rate()1060 parent_rate = __clk_get_rate(parent); in kona_peri_clk_determine_rate()1133 if (rate == __clk_get_rate(hw->clk)) in kona_peri_clk_set_rate()
50 #define __clk_get_rate(clk) (clk->rate) macro
67 parent_rate = __clk_get_rate(parent); in ar100_determine_rate()
101 parent_rate = __clk_get_rate(parent); in clk_factors_determine_rate()
140 parent_rate = __clk_get_rate(parent); in sun6i_ahb1_clk_determine_rate()
123 cur_rate = __clk_get_rate(hwclk->clk); in clk_cpu_on_set_rate()
76 parent_rate = __clk_get_rate(parent); in clk_programmable_determine_rate()
146 parent_rate = __clk_get_rate(parent); in clk_sam9x5_peripheral_autodiv()
637 return __clk_get_rate(hw->clk); in clk_pll_round_rate()1580 parent_rate = __clk_get_rate(parent); in tegra_clk_register_pllxc()1677 parent_rate = __clk_get_rate(parent); in tegra_clk_register_pllm()1718 parent_rate = __clk_get_rate(parent); in tegra_clk_register_pllc()1851 parent_rate = __clk_get_rate(parent); in tegra_clk_register_pllss()
90 __clk_get_rate(__clk_get_parent(__clk_get_parent(hw->clk))); in clk_pll_round_rate_index()
573 unsigned long __clk_get_rate(struct clk *clk);
211 rate = __clk_get_rate(p); in _freq_tbl_determine_rate()
436 rate = __clk_get_rate(p); in _freq_tbl_determine_rate()
182 return __clk_get_rate(parent_clk); in cpu_clk_recalc_rate()