Home
last modified time | relevance | path

Searched refs:_MASKED_BIT_ENABLE (Results 1 – 8 of 8) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/i915/
Dintel_pm.c323 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) : in intel_set_memory_cxsr()
327 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) : in intel_set_memory_cxsr()
5004 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | in cherryview_enable_rps()
5107 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN | in valleyview_enable_rps()
5889 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); in ironlake_init_clock_gating()
5960 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB)); in gen6_init_clock_gating()
6005 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL)); in gen6_init_clock_gating()
6013 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH)); in gen6_init_clock_gating()
6123 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); in broadwell_init_clock_gating()
6141 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE)); in haswell_init_clock_gating()
[all …]
Dintel_ringbuffer.c527 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | in intel_ring_setup_status_page()
541 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING)); in stop_ring()
787 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
1065 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); in init_render_ring()
1074 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); in init_render_ring()
1080 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); in init_render_ring()
1085 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | in init_render_ring()
1086 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); in init_render_ring()
1099 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); in init_render_ring()
2311 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); in gen6_bsd_ring_write_tail()
Dintel_lrc.c785 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING)); in intel_logical_ring_stop()
1147 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)); in gen8_init_common_ring()
1173 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); in gen8_init_render_ring()
1175 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); in gen8_init_render_ring()
1770 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH | in populate_lr_context()
Di915_gem_context.c540 intel_ring_emit(ring, _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE)); in mi_set_context()
Di915_gem_gtt.c1045 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); in gen8_ppgtt_enable()
1071 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); in gen7_ppgtt_enable()
1090 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); in gen6_ppgtt_enable()
Dintel_uncore.c1024 d->val_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL); in fw_domain_init()
Di915_gem.c4674 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); in i915_gem_init_swizzling()
4676 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); in i915_gem_init_swizzling()
4678 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); in i915_gem_init_swizzling()
Di915_reg.h46 #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); }) macro