Searched refs:STMP_OFFSET_REG_SET (Results 1 – 8 of 8) sorted by relevance
99 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); in mxs_spi_setup_transfer()319 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); in mxs_spi_txrx_pio()325 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); in mxs_spi_txrx_pio()335 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); in mxs_spi_txrx_pio()338 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); in mxs_spi_txrx_pio()347 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); in mxs_spi_txrx_pio()382 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); in mxs_spi_transfer_one()419 STMP_OFFSET_REG_SET); in mxs_spi_transfer_one()
15 #define STMP_OFFSET_REG_SET 0x4 macro
223 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET); in mxs_dma_reset_chan()248 mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_SET); in mxs_dma_reset_chan()293 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET); in mxs_dma_pause_chan()296 mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_SET); in mxs_dma_pause_chan()711 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET); in mxs_dma_init()713 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET); in mxs_dma_init()718 mxs_dma->base + HW_APBHX_CTRL1 + STMP_OFFSET_REG_SET); in mxs_dma_init()
56 writel(STMP_MODULE_SFTRST, reset_addr + STMP_OFFSET_REG_SET); in stmp_reset_block()
97 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_SET); in stmp3xxx_wdt_set_timeout()99 rtc_data->io + STMP3XXX_RTC_PERSISTENT1 + STMP_OFFSET_REG_SET); in stmp3xxx_wdt_set_timeout()
94 HW_TIMROT_TIMCTRLn(0) + STMP_OFFSET_REG_SET); in timrot_irq_enable()
526 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); in mxs_mmc_enable_sdio_irq()528 ssp->base + HW_SSP_CTRL1(ssp) + STMP_OFFSET_REG_SET); in mxs_mmc_enable_sdio_irq()
360 writel(val, lradc->base + reg + STMP_OFFSET_REG_SET); in mxs_lradc_reg_set()1206 const uint32_t st = state ? STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR; in mxs_lradc_configure_trigger()