Searched refs:RREG32_SMC (Results 1 – 10 of 10) sorted by relevance
116 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); in ci_start_smc()124 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); in ci_reset_smc()139 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in ci_stop_smc_clock()148 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in ci_start_smc_clock()157 u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in ci_is_smc_running()158 u32 pc_c = RREG32_SMC(SMC_PC_C); in ci_is_smc_running()197 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
115 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); in si_start_smc()131 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); in si_reset_smc()145 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in si_stop_smc_clock()154 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in si_start_smc_clock()163 u32 rst = RREG32_SMC(SMC_SYSCON_RESET_CNTL); in si_is_smc_running()164 u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in si_is_smc_running()202 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in si_wait_for_smc_inactive()
376 value = RREG32_SMC(GFX_POWER_GATING_CNTL); in trinity_gfx_powergating_initialize()504 if (RREG32_SMC(CC_SMU_TST_EFUSE1_MISC) & RB_BACKEND_DISABLE_MASK) in trinity_gfx_powergating_enable()505 WREG32_SMC(SMU_SCRATCH_A, (RREG32_SMC(SMU_SCRATCH_A) | 0x01)); in trinity_gfx_powergating_enable()520 value = RREG32_SMC(PM_I_CNTL_1); in trinity_gfx_dynamic_mgpg_enable()525 value = RREG32_SMC(SMU_S_PG_CNTL); in trinity_gfx_dynamic_mgpg_enable()530 value = RREG32_SMC(SMU_S_PG_CNTL); in trinity_gfx_dynamic_mgpg_enable()534 value = RREG32_SMC(PM_I_CNTL_1); in trinity_gfx_dynamic_mgpg_enable()594 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix); in trinity_set_divider_value()604 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_PG_CNTL + ix); in trinity_set_divider_value()616 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix); in trinity_set_ds_dividers()[all …]
581 data = RREG32_SMC(config_regs->offset); in ci_program_pt_config_registers()877 tmp = RREG32_SMC(CG_THERMAL_INT); in ci_thermal_set_temperature_range()885 tmp = RREG32_SMC(CG_THERMAL_CTRL); in ci_thermal_set_temperature_range()900 u32 thermal_int = RREG32_SMC(CG_THERMAL_INT); in ci_thermal_enable_alert()932 tmp = (RREG32_SMC(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT; in ci_fan_ctrl_set_static_mode()934 tmp = (RREG32_SMC(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT; in ci_fan_ctrl_set_static_mode()939 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TMIN_MASK; in ci_fan_ctrl_set_static_mode()943 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; in ci_fan_ctrl_set_static_mode()964 duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; in ci_thermal_setup_fan_table()1008 tmp = (RREG32_SMC(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT; in ci_thermal_setup_fan_table()[all …]
61 *enable_mask = RREG32_SMC(SMC_SYSCON_MSG_ARG_0); in kv_dpm_get_enable_mask()
298 data = RREG32_SMC(config_regs->offset); in kv_program_pt_config_registers()645 u32 tmp = RREG32_SMC(GENERAL_PWRMGT); in kv_start_dpm()660 u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL); in kv_start_am()670 u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL); in kv_reset_am()1176 thermal_int = RREG32_SMC(CG_THERMAL_INT_CTRL); in kv_enable_thermal_int()2440 nbdpmconfig1 = RREG32_SMC(NB_DPM_CONFIG_1); in kv_program_nbps_index_settings()2467 tmp = RREG32_SMC(CG_THERMAL_INT_CTRL); in kv_set_thermal_temperature_range()2804 (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) >> in kv_dpm_debugfs_print_current_performance_level()2813 tmp = (RREG32_SMC(SMU_VOLTAGE_STATUS) & SMU_VOLTAGE_CURRENT_LEVEL_MASK) >> in kv_dpm_debugfs_print_current_performance_level()2827 (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) >> in kv_dpm_get_current_sclk()
183 temp = (RREG32_SMC(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >> in ci_get_temp()202 temp = RREG32_SMC(0xC0300E0C); in kv_get_temp()1693 if (RREG32_SMC(GENERAL_PWRMGT) & GPU_COUNTER_CLK) in cik_get_xclk()1696 if (RREG32_SMC(CG_CLKPIN_CNTL) & XTALIN_DIVIDE) in cik_get_xclk()9698 tmp = RREG32_SMC(cntl_reg); in cik_set_uvd_clock()9704 if (RREG32_SMC(status_reg) & DCLK_STATUS) in cik_set_uvd_clock()9738 if (RREG32_SMC(CG_ECLK_STATUS) & ECLK_STATUS) in cik_set_vce_clocks()9745 tmp = RREG32_SMC(CG_ECLK_CNTL); in cik_set_vce_clocks()9751 if (RREG32_SMC(CG_ECLK_STATUS) & ECLK_STATUS) in cik_set_vce_clocks()10017 orig = data = RREG32_SMC(THM_CLK_CNTL); in cik_program_aspm()[all …]
862 u32 temp = RREG32_SMC(TN_CURRENT_GNB_TEMP) & 0x7ff; in tn_get_temp()
2554 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) macro
2748 data = RREG32_SMC(offset); in si_program_cac_config_registers()