376 	value = RREG32_SMC(GFX_POWER_GATING_CNTL);  in trinity_gfx_powergating_initialize()
504 		if (RREG32_SMC(CC_SMU_TST_EFUSE1_MISC) & RB_BACKEND_DISABLE_MASK)  in trinity_gfx_powergating_enable()
505 			WREG32_SMC(SMU_SCRATCH_A, (RREG32_SMC(SMU_SCRATCH_A) | 0x01));  in trinity_gfx_powergating_enable()
520 		value = RREG32_SMC(PM_I_CNTL_1);  in trinity_gfx_dynamic_mgpg_enable()
525 		value = RREG32_SMC(SMU_S_PG_CNTL);  in trinity_gfx_dynamic_mgpg_enable()
530 		value = RREG32_SMC(SMU_S_PG_CNTL);  in trinity_gfx_dynamic_mgpg_enable()
534 		value = RREG32_SMC(PM_I_CNTL_1);  in trinity_gfx_dynamic_mgpg_enable()
594 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);  in trinity_set_divider_value()
604 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_PG_CNTL + ix);  in trinity_set_divider_value()
616 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix);  in trinity_set_ds_dividers()
628 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix);  in trinity_set_ss_dividers()
641 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);  in trinity_set_vid()
646 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);  in trinity_set_vid()
658 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_3 + ix);  in trinity_set_allos_gnb_slow()
670 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_3 + ix);  in trinity_set_force_nbp_state()
682 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix);  in trinity_set_display_wm()
694 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix);  in trinity_set_vce_wm()
706 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_AT + ix);  in trinity_set_at()
737 	value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);  in trinity_power_level_enable_disable()
746 	if (RREG32_SMC(SMU_SCLK_DPM_CNTL) & SCLK_DPM_EN(1))  in trinity_dpm_enabled()
754 	u32 value = RREG32_SMC(SMU_SCLK_DPM_CNTL);  in trinity_start_dpm()
793 	sclk_dpm_cntl = RREG32_SMC(SMU_SCLK_DPM_CNTL);  in trinity_stop_dpm()
883 	u32 tp = RREG32_SMC(PM_TP);  in trinity_setup_uvd_dpm_interval()
991 	u32 value = RREG32_SMC(SMU_SCLK_DPM_TTT);  in trinity_program_ttt()
1001 	u32 value = RREG32_SMC(SMU_SCLK_DPM_TT_CNTL);  in trinity_enable_att()
1011 	u32 tp = RREG32_SMC(PM_TP);  in trinity_program_sclk_dpm()
1020 	value = RREG32_SMC(PM_I_CNTL_1);  in trinity_program_sclk_dpm()
1163 		(RREG32_SMC(CC_SMU_MISC_FUSES) & MinSClkDid_MASK) >> MinSClkDid_SHIFT;  in trinity_get_min_sclk_divider()
1174 		nbpsconfig = RREG32_SMC(NB_PSTATE_CONFIG);  in trinity_setup_nbp_sim()
1295 	u32 svi_mode = (RREG32_SMC(PM_CONFIG) & SVI_Mode) ? 1 : 0;  in trinity_convert_voltage_index_to_value()
1576 		(RREG32_SMC(GPU_CAC_AVRG_CNTL) & WINDOW_SIZE_MASK) >> WINDOW_SIZE_SHIFT;  in trinity_add_dccac_value()