581 				data = RREG32_SMC(config_regs->offset);  in ci_program_pt_config_registers()
877 	tmp = RREG32_SMC(CG_THERMAL_INT);  in ci_thermal_set_temperature_range()
885 	tmp = RREG32_SMC(CG_THERMAL_CTRL);  in ci_thermal_set_temperature_range()
900 	u32 thermal_int = RREG32_SMC(CG_THERMAL_INT);  in ci_thermal_enable_alert()
932 		tmp = (RREG32_SMC(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;  in ci_fan_ctrl_set_static_mode()
934 		tmp = (RREG32_SMC(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;  in ci_fan_ctrl_set_static_mode()
939 	tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TMIN_MASK;  in ci_fan_ctrl_set_static_mode()
943 	tmp = RREG32_SMC(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;  in ci_fan_ctrl_set_static_mode()
964 	duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;  in ci_thermal_setup_fan_table()
1008 	tmp = (RREG32_SMC(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;  in ci_thermal_setup_fan_table()
1075 	duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;  in ci_fan_ctrl_get_fan_speed_percent()
1076 	duty = (RREG32_SMC(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;  in ci_fan_ctrl_get_fan_speed_percent()
1108 	duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;  in ci_fan_ctrl_set_fan_speed_percent()
1117 	tmp = RREG32_SMC(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;  in ci_fan_ctrl_set_fan_speed_percent()
1148 	tmp = RREG32_SMC(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;  in ci_fan_ctrl_get_mode()
1165 	tach_period = (RREG32_SMC(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
1194 	tmp = RREG32_SMC(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
1210 		tmp = RREG32_SMC(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;  in ci_fan_ctrl_set_default_mode()
1214 		tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TMIN_MASK;  in ci_fan_ctrl_set_default_mode()
1234 		tmp = RREG32_SMC(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;  in ci_thermal_initialize()
1239 	tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;  in ci_thermal_initialize()
1401 		tmp = RREG32_SMC(CG_THERMAL_CTRL);  in ci_set_dpm_event_sources()
1407 		tmp = RREG32_SMC(GENERAL_PWRMGT);  in ci_set_dpm_event_sources()
1414 		tmp = RREG32_SMC(GENERAL_PWRMGT);  in ci_set_dpm_event_sources()
1524 	tmp = RREG32_SMC(GENERAL_PWRMGT);  in ci_start_dpm()
1528 	tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);  in ci_start_dpm()
1585 	tmp = RREG32_SMC(GENERAL_PWRMGT);  in ci_stop_dpm()
1589 	tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);  in ci_stop_dpm()
1612 	u32 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);  in ci_enable_sclk_control()
1775 		if (RREG32_SMC(FIRMWARE_FLAGS) & INTERRUPTS_ENABLED)  in ci_dpm_start_smc()
1845 		RREG32_SMC(CG_SPLL_FUNC_CNTL);  in ci_read_clock_registers()
1847 		RREG32_SMC(CG_SPLL_FUNC_CNTL_2);  in ci_read_clock_registers()
1849 		RREG32_SMC(CG_SPLL_FUNC_CNTL_3);  in ci_read_clock_registers()
1851 		RREG32_SMC(CG_SPLL_FUNC_CNTL_4);  in ci_read_clock_registers()
1853 		RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM);  in ci_read_clock_registers()
1855 		RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM_2);  in ci_read_clock_registers()
1877 	u32 tmp = RREG32_SMC(GENERAL_PWRMGT);  in ci_enable_thermal_protection()
1888 	u32 tmp = RREG32_SMC(GENERAL_PWRMGT);  in ci_enable_acpi_power_management()
1957 	u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);  in ci_program_display_gap()
1996 			tmp = RREG32_SMC(GENERAL_PWRMGT);  in ci_enable_spread_spectrum()
2001 		tmp = RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM);  in ci_enable_spread_spectrum()
2005 		tmp = RREG32_SMC(GENERAL_PWRMGT);  in ci_enable_spread_spectrum()
2018 	u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);  in ci_enable_display_gap()
2031 	tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);  in ci_program_vc()
2049 	tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);  in ci_clear_vc()
2069 		if (RREG32_SMC(RCU_UC_EVENTS) & BOOT_SEQ_DONE)  in ci_upload_firmware()
2457 	tmp = (RREG32_SMC(SMC_SCRATCH9) & 0x0000ff00) >> 8;  in ci_force_switch_to_arb_f0()
4057 		tmp = RREG32_SMC(DPM_TABLE_475);  in ci_update_uvd_dpm()
4095 			tmp = RREG32_SMC(DPM_TABLE_475);  in ci_update_vce_dpm()
4125 		tmp = RREG32_SMC(DPM_TABLE_475);
4192 					tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &  in ci_dpm_force_performance_level()
4211 					tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &  in ci_dpm_force_performance_level()
4230 					tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &  in ci_dpm_force_performance_level()
4247 				tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &  in ci_dpm_force_performance_level()
4262 				tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &  in ci_dpm_force_performance_level()
4277 				tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &  in ci_dpm_force_performance_level()
4758 	u32 tmp = RREG32_SMC(GENERAL_PWRMGT);  in ci_enable_voltage_control()
5800 		u32 tmp = RREG32_SMC(CNB_PWRMGT_CNTL);  in ci_dpm_init()