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Searched refs:R4600_V2_HIT_CACHEOP_WAR (Results 1 – 16 of 16) sorted by relevance

/linux-4.1.27/arch/mips/include/asm/
Dwar.h127 #ifndef R4600_V2_HIT_CACHEOP_WAR
128 #error Check setting of R4600_V2_HIT_CACHEOP_WAR for your platform
/linux-4.1.27/arch/mips/include/asm/mach-sead3/
Dwar.h13 #define R4600_V2_HIT_CACHEOP_WAR 0 macro
/linux-4.1.27/arch/mips/include/asm/mach-tx49xx/
Dwar.h13 #define R4600_V2_HIT_CACHEOP_WAR 0 macro
/linux-4.1.27/arch/mips/include/asm/mach-ip22/
Dwar.h17 #define R4600_V2_HIT_CACHEOP_WAR 1 macro
/linux-4.1.27/arch/mips/include/asm/mach-rc32434/
Dwar.h13 #define R4600_V2_HIT_CACHEOP_WAR 0 macro
/linux-4.1.27/arch/mips/include/asm/mach-ip28/
Dwar.h13 #define R4600_V2_HIT_CACHEOP_WAR 0 macro
/linux-4.1.27/arch/mips/include/asm/mach-ip32/
Dwar.h13 #define R4600_V2_HIT_CACHEOP_WAR 0 macro
/linux-4.1.27/arch/mips/include/asm/mach-ip27/
Dwar.h13 #define R4600_V2_HIT_CACHEOP_WAR 0 macro
/linux-4.1.27/arch/mips/include/asm/mach-malta/
Dwar.h13 #define R4600_V2_HIT_CACHEOP_WAR 0 macro
/linux-4.1.27/arch/mips/include/asm/mach-rm/
Dwar.h17 #define R4600_V2_HIT_CACHEOP_WAR 1 macro
/linux-4.1.27/arch/mips/include/asm/mach-generic/
Dwar.h13 #define R4600_V2_HIT_CACHEOP_WAR 0 macro
/linux-4.1.27/arch/mips/include/asm/mach-cavium-octeon/
Dwar.h14 #define R4600_V2_HIT_CACHEOP_WAR 0 macro
/linux-4.1.27/arch/mips/include/asm/mach-pmcs-msp71xx/
Dwar.h13 #define R4600_V2_HIT_CACHEOP_WAR 0 macro
/linux-4.1.27/arch/mips/include/asm/mach-sibyte/
Dwar.h13 #define R4600_V2_HIT_CACHEOP_WAR 0 macro
/linux-4.1.27/arch/mips/mm/
Dpage.c253 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) in build_clear_pref()
298 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) in build_clear_page()
405 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) in build_copy_store_pref()
449 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) in build_copy_page()
Dc-r4k.c101 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) \