Searched refs:PWM0 (Results 1 - 35 of 35) sorted by relevance

/linux-4.1.27/drivers/video/backlight/
H A Dpandora_bl.c3 * Pandora uses TWL4030 PWM0 -> TPS61161 combo for control backlight.
59 /* first disable PWM0 output, then clock */ pandora_backlight_update_status()
76 /* first enable clock, then PWM0 out */ pandora_backlight_update_status()
/linux-4.1.27/drivers/pinctrl/freescale/
H A Dpinctrl-imx23.c77 PWM0 = PINID(1, 26), enumerator in enum:imx23_pin_enum
197 MXS_PINCTRL_PIN(PWM0),
H A Dpinctrl-imx28.c113 PWM0 = PINID(3, 16), enumerator in enum:imx28_pin_enum
291 MXS_PINCTRL_PIN(PWM0),
/linux-4.1.27/drivers/pwm/
H A Dpwm-clps711x.c33 /* PWM0 - bits 4..7, PWM1 - bits 8..11 */ clps711x_pwm_update_val()
H A Dpwm-twl.c29 * The TRM names for the PWMs on TWL4030 are: PWM0, PWM1
/linux-4.1.27/drivers/leds/
H A Dleds-pca955x.c56 #define PCA955X_LS_BLINK0 0x2 /* Blink at PWM0 rate */
345 /* PWM0 is used for half brightness or 50% duty cycle */ pca955x_probe()
/linux-4.1.27/arch/blackfin/mach-bf609/include/mach/
H A Dirq.h44 #define IRQ_PWM0_TRIP BFIN_IRQ(28) /* PWM0 Trip Interrupt */
45 #define IRQ_PWM0_SYNC BFIN_IRQ(29) /* PWM0 Sync Interrupt */
/linux-4.1.27/drivers/pinctrl/mediatek/
H A Dpinctrl-mtk-mt8173.h365 MTK_FUNCTION(3, "PWM0"),
628 MTK_FUNCTION(3, "PWM0"),
915 MTK_FUNCTION(5, "PWM0"),
/linux-4.1.27/arch/arm/include/asm/hardware/
H A Dsa1111.h110 * SKPEN0 PWM0 Enable Register
111 * SKPWM0 PWM0 Clock Register
/linux-4.1.27/drivers/clk/pxa/
H A Dclk-pxa25x.c135 PXA25X_OSC3_CKEN("pxa25x-pwm.0", NULL, PWM0, 1, 1, 0),
H A Dclk-pxa27x.c128 PXA27X_PBUS_CKEN("pxa27x-pwm.0", NULL, PWM0, 1, 24, 0),
H A Dclk-pxa3xx.c151 PXA3XX_PBUS_CKEN("pxa27x-pwm.0", NULL, PWM0, 1, 6, 1, 48, 0),
/linux-4.1.27/arch/arm/mach-pxa/include/mach/
H A Dpxa2xx-regs.h185 #define CKEN_PWM0 (0) /* PWM0 Clock Enable */
/linux-4.1.27/arch/arm/mach-pxa/
H A Dmxm8x10.c167 GPIO11 - PWM0
H A Dpxa25x.c180 static DEFINE_PXA2_CKEN(pxa25x_pwm0, PWM0, 3686400, 0);
H A Dpcm990-baseboard.c55 /* PWM0 */
H A Dpxa27x.c198 static DEFINE_PXA2_CKEN(pxa27x_pwm0, PWM0, 13000000, 0);
H A Dpxa3xx.c59 static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0);
/linux-4.1.27/drivers/pinctrl/
H A Dpinctrl-tegra114.c1638 PINGROUP(sdmmc1_dat2_py5, SDMMC1, PWM0, SPI4, UARTA, 0x3054, N, N, N),
1653 PINGROUP(uart3_rts_n_pc0, UARTC, PWM0, DTV, DISPLAYA, 0x3180, N, N, N),
1657 PINGROUP(pu3, PWM0, UARTA, DISPLAYA, DISPLAYB, 0x3190, N, N, N),
1689 PINGROUP(gmi_ad8_ph0, PWM0, NAND, GMI, DTV, 0x3210, N, N, N),
1782 PINGROUP(sdmmc3_dat3_pb4, SDMMC3, PWM0, DISPLAYB, SPI3, 0x33a4, N, N, N),
H A Dpinctrl-tegra124.c1831 PINGROUP(sdmmc1_dat2_py5, SDMMC1, PWM0, SPI4, UARTA, 0x3054, N, N, N),
1846 PINGROUP(uart3_rts_n_pc0, UARTC, PWM0, DTV, GMI, 0x3180, N, N, N),
1850 PINGROUP(pu3, PWM0, UARTA, GMI, DISPLAYB, 0x3190, N, N, N),
1882 PINGROUP(ph0, PWM0, TRACE, GMI, DTV, 0x3210, N, N, N),
1979 PINGROUP(sdmmc3_dat3_pb4, SDMMC3, PWM0, DISPLAYB, SPI3, 0x33a4, N, N, N),
H A Dpinctrl-tegra30.c2190 PINGROUP(sdmmc3_dat3_pb4, RSVD1, PWM0, SDMMC3, SPI3, 0x33a4, N, N),
2194 PINGROUP(uart3_rts_n_pc0, UARTC, PWM0, GMI, RSVD4, 0x3180, N, N),
2202 PINGROUP(sdmmc3_dat5_pd0, PWM0, SPI4, SDMMC3, SPI2, 0x33ac, N, N),
2234 PINGROUP(gmi_ad8_ph0, PWM0, NAND, GMI, RSVD4, 0x3210, N, N),
2341 PINGROUP(pu3, PWM0, UARTA, GMI, RSVD4, 0x3190, N, N),
H A Dpinctrl-tegra210.c1485 PINGROUP(lcd_bl_pwm_pv0, DISPLAYA, PWM0, SOR0, RSVD3, 0x31fc, N, N, N, 0xa34, 12, 5, 20, 5, -1, -1, -1, -1),
/linux-4.1.27/arch/arm/mach-davinci/include/mach/
H A Dmux.h64 /* PWM0 */
/linux-4.1.27/drivers/pinctrl/sh-pfc/
H A Dpfc-emev2.c584 PINMUX_IPSR_NOFN(USI_9_8_PORT120, PWM0, SEL_USI_9_8_00),
883 /* = [ PWM0 ] ============= */
884 EMEV_MUX_PIN(pwm0, 120, PWM0);
H A Dpfc-r8a7779.c907 PINMUX_IPSR_DATA(IP4_10_8, PWM0),
H A Dpfc-r8a7790.c1204 PINMUX_IPSR_DATA(IP7_18_16, PWM0),
H A Dpfc-r8a7791.c1538 PINMUX_IPSR_DATA(IP13_30_28, PWM0),
/linux-4.1.27/arch/arm/mach-davinci/
H A Ddm644x.c405 MUX_CFG(DM644X, PWM0, 1, 4, 1, 1, false)
H A Ddm365.c557 MUX_CFG(DM365, PWM0, 1, 0, 3, 2, false)
/linux-4.1.27/drivers/mfd/
H A Dasic3.c64 INIT_CDEX(PWM0, 0),
/linux-4.1.27/drivers/pinctrl/sunxi/
H A Dpinctrl-sun5i-a10s.c147 SUNXI_FUNCTION(0x2, "pwm"), /* PWM0 */
H A Dpinctrl-sun4i-a10.c134 SUNXI_FUNCTION(0x2, "pwm")), /* PWM0 */
H A Dpinctrl-sun7i-a20.c157 SUNXI_FUNCTION(0x2, "pwm")), /* PWM0 */
/linux-4.1.27/drivers/pinctrl/spear/
H A Dpinctrl-spear1340.c185 /* Write 0 to enable PWM0 */
/linux-4.1.27/drivers/pinctrl/intel/
H A Dpinctrl-cherryview.c536 PINCTRL_PIN(5, "PWM0"),

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