Searched refs:PIPE_A (Results 1 – 17 of 17) sorted by relevance
228 gen8_irq_power_well_post_enable(dev_priv, 1 << PIPE_A); in skl_power_well_post_enable()683 assert_pll_disabled(dev_priv, PIPE_A); in chv_dpio_cmn_power_well_disable()768 WARN_ON_ONCE(power_well->data != PIPE_A && in chv_pipe_power_well_enable()774 if (power_well->data == PIPE_A) { in chv_pipe_power_well_enable()795 WARN_ON_ONCE(power_well->data != PIPE_A && in chv_pipe_power_well_disable()799 if (power_well->data == PIPE_A) { in chv_pipe_power_well_disable()807 if (power_well->data == PIPE_A) in chv_pipe_power_well_disable()1165 .data = PIPE_A,
488 i915_enable_pipestat(dev_priv, PIPE_A, in i915_enable_asle_pipestat()1695 case PIPE_A: in valleyview_pipestat_irq_handler()3109 if (pipe_mask & 1 << PIPE_A) in gen8_irq_power_well_post_enable()3110 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_A, in gen8_irq_power_well_post_enable()3111 dev_priv->de_irq_mask[PIPE_A], in gen8_irq_power_well_post_enable()3112 ~dev_priv->de_irq_mask[PIPE_A] | extra_ier); in gen8_irq_power_well_post_enable()3287 POSTING_READ(PIPESTAT(PIPE_A)); in valleyview_display_irqs_install()3292 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); in valleyview_display_irqs_install()3332 i915_disable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); in valleyview_display_irqs_uninstall()3341 POSTING_READ(PIPESTAT(PIPE_A)); in valleyview_display_irqs_uninstall()[all …]
525 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) in _vlv_get_backlight()612 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) in vlv_set_backlight()735 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) in vlv_disable_backlight()934 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) in vlv_enable_backlight()1288 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) in vlv_setup_backlight()
431 for (i = PIPE_A; i <= PIPE_C; i++) { in intel_dp_add_mst_connector()537 for (i = PIPE_A; i <= PIPE_C; i++) in intel_dp_create_fake_mst_encoders()
144 uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN : in ironlake_set_fifo_underrun_reporting()
366 case PIPE_A: in vlv_get_fifo_size()860 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA)); in vlv_write_wm_values()862 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) | in vlv_write_wm_values()863 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) | in vlv_write_wm_values()864 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA)); in vlv_write_wm_values()886 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) | in vlv_write_wm_values()887 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) | in vlv_write_wm_values()888 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI)); in vlv_write_wm_values()898 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) | in vlv_write_wm_values()899 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) | in vlv_write_wm_values()[all …]
3157 .pipe = PIPE_A,3349 case PIPE_A: in vlv_pipe_crc_ctl_reg()3432 if (pipe == PIPE_A) in i9xx_pipe_crc_ctl_reg()3450 case PIPE_A: in vlv_undo_pipe_scramble_reset()3474 if (pipe == PIPE_A) in g4x_undo_pipe_scramble_reset()3516 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]); in hsw_trans_edp_pipe_A_crc_wa()3530 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A)); in hsw_trans_edp_pipe_A_crc_wa()3542 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]); in hsw_undo_trans_edp_pipe_A_crc_wa()3558 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A)); in hsw_undo_trans_edp_pipe_A_crc_wa()3579 if (IS_HASWELL(dev) && pipe == PIPE_A) in ivb_pipe_crc_ctl_reg()[all …]
614 *pipe = port == PORT_A ? PIPE_A : PIPE_B; in intel_dsi_get_hw_state()1040 intel_encoder->crtc_mask = (1 << PIPE_A); in intel_dsi_init()
1238 enum pipe panel_pipe = PIPE_A; in assert_panel_unlocked()1302 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || in assert_pipe()1753 I915_WRITE(DPLL(PIPE_A), in i9xx_disable_pll()1754 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); in i9xx_disable_pll()1758 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || in i9xx_disable_pll()1797 if (pipe != PIPE_A) in chv_disable_pll()2127 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || in intel_enable_pipe()2175 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && in intel_disable_pipe()3959 case PIPE_A: in ivybridge_update_fdi_bc_bifurcation()4085 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); in lpt_pch_enable()[all …]
391 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); in vlv_power_sequencer_pipe()424 pipe = PIPE_A; in vlv_power_sequencer_pipe()476 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { in vlv_initial_pps_pipe()2582 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) in vlv_steal_power_sequencer()5433 if (pipe != PIPE_A && pipe != PIPE_B) in intel_edp_init_connector()5436 if (pipe != PIPE_A && pipe != PIPE_B) in intel_edp_init_connector()5437 pipe = PIPE_A; in intel_edp_init_connector()
1323 case PIPE_A: in intel_ddi_enable_transcoder_func()1468 *pipe = PIPE_A; in intel_ddi_get_hw_state()
453 GEN7_PIPE_DE_LOAD_SL(PIPE_A),
709 case PIPE_A: in vlv_pipe_to_channel()
32 #define _PIPE3(pipe, a, b, c) ((pipe) == PIPE_A ? (a) : \4035 dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \4453 dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
110 PIPE_A = 0, enumerator
480 if (unlikely(pipe == PIPE_A)) in intelfbhw_active_pipe()481 return PIPE_A; in intelfbhw_active_pipe()486 if (likely(pipe == PIPE_A)) in intelfbhw_active_pipe()487 return PIPE_A; in intelfbhw_active_pipe()492 pipe = PIPE_A; in intelfbhw_active_pipe()501 u32 palette_reg = (dinfo->pipe == PIPE_A) ? in intelfbhw_setcolreg()
182 #define PIPE_A 0 macro