Lines Matching refs:PIPE_A
488 i915_enable_pipestat(dev_priv, PIPE_A, in i915_enable_asle_pipestat()
1695 case PIPE_A: in valleyview_pipestat_irq_handler()
3109 if (pipe_mask & 1 << PIPE_A) in gen8_irq_power_well_post_enable()
3110 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_A, in gen8_irq_power_well_post_enable()
3111 dev_priv->de_irq_mask[PIPE_A], in gen8_irq_power_well_post_enable()
3112 ~dev_priv->de_irq_mask[PIPE_A] | extra_ier); in gen8_irq_power_well_post_enable()
3287 POSTING_READ(PIPESTAT(PIPE_A)); in valleyview_display_irqs_install()
3292 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); in valleyview_display_irqs_install()
3332 i915_disable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); in valleyview_display_irqs_uninstall()
3341 POSTING_READ(PIPESTAT(PIPE_A)); in valleyview_display_irqs_uninstall()
3458 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked; in gen8_de_irq_postinstall()
3606 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); in i8xx_irq_postinstall()
3788 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); in i915_irq_postinstall()
3990 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); in i965_irq_postinstall()
3991 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); in i965_irq_postinstall()