Searched refs:PCLK_UART0 (Results 1 - 49 of 49) sorted by relevance

/linux-4.1.27/arch/mips/boot/dts/include/dt-bindings/clock/
H A Ds3c2410.h34 #define PCLK_UART0 16 macro
H A Ds3c2412.h53 #define PCLK_UART0 41 macro
H A Ds3c2443.h69 #define PCLK_UART0 72 macro
H A Dexynos7-clk.h59 #define PCLK_UART0 1 macro
H A Dsamsung,s3c64xx-clock.h91 #define PCLK_UART0 73 macro
H A Drk3188-cru-common.h85 #define PCLK_UART0 332 macro
H A Drk3288-cru.h136 #define PCLK_UART0 341 macro
/linux-4.1.27/arch/powerpc/boot/dts/include/dt-bindings/clock/
H A Ds3c2410.h34 #define PCLK_UART0 16 macro
H A Ds3c2412.h53 #define PCLK_UART0 41 macro
H A Ds3c2443.h69 #define PCLK_UART0 72 macro
H A Dexynos7-clk.h59 #define PCLK_UART0 1 macro
H A Dsamsung,s3c64xx-clock.h91 #define PCLK_UART0 73 macro
H A Drk3188-cru-common.h85 #define PCLK_UART0 332 macro
H A Drk3288-cru.h136 #define PCLK_UART0 341 macro
/linux-4.1.27/arch/arm64/boot/dts/include/dt-bindings/clock/
H A Ds3c2410.h34 #define PCLK_UART0 16 macro
H A Ds3c2412.h53 #define PCLK_UART0 41 macro
H A Ds3c2443.h69 #define PCLK_UART0 72 macro
H A Dexynos7-clk.h59 #define PCLK_UART0 1 macro
H A Dsamsung,s3c64xx-clock.h91 #define PCLK_UART0 73 macro
H A Drk3188-cru-common.h85 #define PCLK_UART0 332 macro
H A Drk3288-cru.h136 #define PCLK_UART0 341 macro
/linux-4.1.27/arch/metag/boot/dts/include/dt-bindings/clock/
H A Ds3c2410.h34 #define PCLK_UART0 16 macro
H A Ds3c2412.h53 #define PCLK_UART0 41 macro
H A Ds3c2443.h69 #define PCLK_UART0 72 macro
H A Dexynos7-clk.h59 #define PCLK_UART0 1 macro
H A Dsamsung,s3c64xx-clock.h91 #define PCLK_UART0 73 macro
H A Drk3188-cru-common.h85 #define PCLK_UART0 332 macro
H A Drk3288-cru.h136 #define PCLK_UART0 341 macro
/linux-4.1.27/arch/arm/boot/dts/include/dt-bindings/clock/
H A Ds3c2410.h34 #define PCLK_UART0 16 macro
H A Ds3c2412.h53 #define PCLK_UART0 41 macro
H A Ds3c2443.h69 #define PCLK_UART0 72 macro
H A Dexynos7-clk.h59 #define PCLK_UART0 1 macro
H A Dsamsung,s3c64xx-clock.h91 #define PCLK_UART0 73 macro
H A Drk3188-cru-common.h85 #define PCLK_UART0 332 macro
H A Drk3288-cru.h136 #define PCLK_UART0 341 macro
/linux-4.1.27/include/dt-bindings/clock/
H A Ds3c2410.h34 #define PCLK_UART0 16 macro
H A Ds3c2412.h53 #define PCLK_UART0 41 macro
H A Ds3c2443.h69 #define PCLK_UART0 72 macro
H A Dexynos7-clk.h59 #define PCLK_UART0 1 macro
H A Dsamsung,s3c64xx-clock.h91 #define PCLK_UART0 73 macro
H A Drk3188-cru-common.h85 #define PCLK_UART0 332 macro
H A Drk3288-cru.h136 #define PCLK_UART0 341 macro
/linux-4.1.27/drivers/clk/samsung/
H A Dclk-s3c2410.c130 GATE(PCLK_UART0, "uart0", "pclk", CLKCON, 10, 0, 0),
221 ALIAS(PCLK_UART0, "s3c2410-uart.0", "uart"),
224 ALIAS(PCLK_UART0, "s3c2410-uart.0", "clk_uart_baud0"),
309 ALIAS(PCLK_UART0, "s3c2440-uart.0", "uart"),
312 ALIAS(PCLK_UART0, "s3c2440-uart.0", "clk_uart_baud2"),
H A Dclk-s3c2412.c165 GATE(PCLK_UART0, "uart0", "pclk", CLKCON, 19, 0, 0),
187 ALIAS(PCLK_UART0, "s3c2412-uart.0", "uart"),
190 ALIAS(PCLK_UART0, "s3c2412-uart.0", "clk_uart_baud2"),
H A Dclk-s3c2443.c190 GATE(PCLK_UART0, "uart0", "pclk", PCLKCON, 0, 0, 0),
196 ALIAS(PCLK_UART0, "s3c2440-uart.0", "uart"),
200 ALIAS(PCLK_UART0, "s3c2440-uart.0", "clk_uart_baud2"),
H A Dclk-s3c64xx.c311 GATE_BUS(PCLK_UART0, "pclk_uart0", "pclk", PCLK_GATE, 1),
416 ALIAS(PCLK_UART0, "s3c6400-uart.0", "uart"),
H A Dclk-exynos7.c578 GATE(PCLK_UART0, "pclk_uart0", "mout_aclk_peric0_66_user",
/linux-4.1.27/drivers/clk/rockchip/
H A Dclk-rk3188.c614 GATE(PCLK_UART0, "pclk_uart0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
701 GATE(PCLK_UART0, "pclk_uart0", "hclk_ahb2apb", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
H A Dclk-rk3288.c692 GATE(PCLK_UART0, "pclk_uart0", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 8, GFLAGS),

Completed in 517 milliseconds