1/* 2 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 3 * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8*/ 9 10#ifndef _DT_BINDINGS_CLOCK_EXYNOS7_H 11#define _DT_BINDINGS_CLOCK_EXYNOS7_H 12 13/* TOPC */ 14#define DOUT_ACLK_PERIS 1 15#define DOUT_SCLK_BUS0_PLL 2 16#define DOUT_SCLK_BUS1_PLL 3 17#define DOUT_SCLK_CC_PLL 4 18#define DOUT_SCLK_MFC_PLL 5 19#define DOUT_ACLK_CCORE_133 6 20#define DOUT_ACLK_MSCL_532 7 21#define ACLK_MSCL_532 8 22#define DOUT_SCLK_AUD_PLL 9 23#define FOUT_AUD_PLL 10 24#define TOPC_NR_CLK 11 25 26/* TOP0 */ 27#define DOUT_ACLK_PERIC1 1 28#define DOUT_ACLK_PERIC0 2 29#define CLK_SCLK_UART0 3 30#define CLK_SCLK_UART1 4 31#define CLK_SCLK_UART2 5 32#define CLK_SCLK_UART3 6 33#define CLK_SCLK_SPI0 7 34#define CLK_SCLK_SPI1 8 35#define CLK_SCLK_SPI2 9 36#define CLK_SCLK_SPI3 10 37#define CLK_SCLK_SPI4 11 38#define CLK_SCLK_SPDIF 12 39#define CLK_SCLK_PCM1 13 40#define CLK_SCLK_I2S1 14 41#define TOP0_NR_CLK 15 42 43/* TOP1 */ 44#define DOUT_ACLK_FSYS1_200 1 45#define DOUT_ACLK_FSYS0_200 2 46#define DOUT_SCLK_MMC2 3 47#define DOUT_SCLK_MMC1 4 48#define DOUT_SCLK_MMC0 5 49#define CLK_SCLK_MMC2 6 50#define CLK_SCLK_MMC1 7 51#define CLK_SCLK_MMC0 8 52#define TOP1_NR_CLK 9 53 54/* CCORE */ 55#define PCLK_RTC 1 56#define CCORE_NR_CLK 2 57 58/* PERIC0 */ 59#define PCLK_UART0 1 60#define SCLK_UART0 2 61#define PCLK_HSI2C0 3 62#define PCLK_HSI2C1 4 63#define PCLK_HSI2C4 5 64#define PCLK_HSI2C5 6 65#define PCLK_HSI2C9 7 66#define PCLK_HSI2C10 8 67#define PCLK_HSI2C11 9 68#define PCLK_PWM 10 69#define SCLK_PWM 11 70#define PCLK_ADCIF 12 71#define PERIC0_NR_CLK 13 72 73/* PERIC1 */ 74#define PCLK_UART1 1 75#define PCLK_UART2 2 76#define PCLK_UART3 3 77#define SCLK_UART1 4 78#define SCLK_UART2 5 79#define SCLK_UART3 6 80#define PCLK_HSI2C2 7 81#define PCLK_HSI2C3 8 82#define PCLK_HSI2C6 9 83#define PCLK_HSI2C7 10 84#define PCLK_HSI2C8 11 85#define PCLK_SPI0 12 86#define PCLK_SPI1 13 87#define PCLK_SPI2 14 88#define PCLK_SPI3 15 89#define PCLK_SPI4 16 90#define SCLK_SPI0 17 91#define SCLK_SPI1 18 92#define SCLK_SPI2 19 93#define SCLK_SPI3 20 94#define SCLK_SPI4 21 95#define PCLK_I2S1 22 96#define PCLK_PCM1 23 97#define PCLK_SPDIF 24 98#define SCLK_I2S1 25 99#define SCLK_PCM1 26 100#define SCLK_SPDIF 27 101#define PERIC1_NR_CLK 28 102 103/* PERIS */ 104#define PCLK_CHIPID 1 105#define SCLK_CHIPID 2 106#define PCLK_WDT 3 107#define PCLK_TMU 4 108#define SCLK_TMU 5 109#define PERIS_NR_CLK 6 110 111/* FSYS0 */ 112#define ACLK_MMC2 1 113#define ACLK_AXIUS_USBDRD30X_FSYS0X 2 114#define ACLK_USBDRD300 3 115#define SCLK_USBDRD300_SUSPENDCLK 4 116#define SCLK_USBDRD300_REFCLK 5 117#define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER 6 118#define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER 7 119#define OSCCLK_PHY_CLKOUT_USB30_PHY 8 120#define ACLK_PDMA0 9 121#define ACLK_PDMA1 10 122#define FSYS0_NR_CLK 11 123 124/* FSYS1 */ 125#define ACLK_MMC1 1 126#define ACLK_MMC0 2 127#define FSYS1_NR_CLK 3 128 129/* MSCL */ 130#define USERMUX_ACLK_MSCL_532 1 131#define DOUT_PCLK_MSCL 2 132#define ACLK_MSCL_0 3 133#define ACLK_MSCL_1 4 134#define ACLK_JPEG 5 135#define ACLK_G2D 6 136#define ACLK_LH_ASYNC_SI_MSCL_0 7 137#define ACLK_LH_ASYNC_SI_MSCL_1 8 138#define ACLK_AXI2ACEL_BRIDGE 9 139#define ACLK_XIU_MSCLX_0 10 140#define ACLK_XIU_MSCLX_1 11 141#define ACLK_QE_MSCL_0 12 142#define ACLK_QE_MSCL_1 13 143#define ACLK_QE_JPEG 14 144#define ACLK_QE_G2D 15 145#define ACLK_PPMU_MSCL_0 16 146#define ACLK_PPMU_MSCL_1 17 147#define ACLK_MSCLNP_133 18 148#define ACLK_AHB2APB_MSCL0P 19 149#define ACLK_AHB2APB_MSCL1P 20 150 151#define PCLK_MSCL_0 21 152#define PCLK_MSCL_1 22 153#define PCLK_JPEG 23 154#define PCLK_G2D 24 155#define PCLK_QE_MSCL_0 25 156#define PCLK_QE_MSCL_1 26 157#define PCLK_QE_JPEG 27 158#define PCLK_QE_G2D 28 159#define PCLK_PPMU_MSCL_0 29 160#define PCLK_PPMU_MSCL_1 30 161#define PCLK_AXI2ACEL_BRIDGE 31 162#define PCLK_PMU_MSCL 32 163#define MSCL_NR_CLK 33 164 165/* AUD */ 166#define SCLK_I2S 1 167#define SCLK_PCM 2 168#define PCLK_I2S 3 169#define PCLK_PCM 4 170#define ACLK_ADMA 5 171#define AUD_NR_CLK 6 172#endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */ 173