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Searched refs:PAUSE (Results 1 – 30 of 30) sorted by relevance

/linux-4.1.27/arch/powerpc/include/asm/
Ddbdma.h33 #define PAUSE 0x4000 macro
102 out_le32(&((regs)->control), (ACTIVE|DEAD|WAKE|FLUSH|PAUSE|RUN)<<16);\
/linux-4.1.27/drivers/net/ethernet/apple/
Dmace.c306 out_le32(&dma->control, (WAKE|FLUSH|PAUSE|RUN) << 16); in dbdma_reset()
472 out_le32(&rd->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */ in mace_open()
482 out_le32(&td->control, (RUN|PAUSE|FLUSH|WAKE) << 16); in mace_open()
510 rd->control = cpu_to_le32((RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */ in mace_close()
511 td->control = cpu_to_le32((RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */ in mace_close()
972 out_le32(&rd->control, (PAUSE << 16) | PAUSE); in mace_rxdma_intr()
Dbmac.c185 DBDMA_SET(RUN|WAKE) | DBDMA_CLEAR(PAUSE|DEAD)); in dbdma_continue()
193 DBDMA_CLEAR(ACTIVE|DEAD|WAKE|FLUSH|PAUSE|RUN)); in dbdma_reset()
486 rd->control = cpu_to_le32(DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */ in bmac_suspend()
487 td->control = cpu_to_le32(DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */ in bmac_suspend()
1414 rd->control = cpu_to_le32(DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */ in bmac_close()
1415 td->control = cpu_to_le32(DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */ in bmac_close()
1504 out_le32(&td->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE|ACTIVE|DEAD)); in bmac_tx_timeout()
1510 out_le32(&rd->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE|ACTIVE|DEAD)); in bmac_tx_timeout()
/linux-4.1.27/Documentation/networking/
Dvortex.txt151 PAUSE command, which means that they will stop sending packets for a
152 short period if they receive a PAUSE frame from the link partner.
160 The 3com cards appear to only respond to PAUSE frames which are
162 do not honour PAUSE frames which are sent to the station MAC address.
Daltera_tse.txt163 802.3-2012, Section 30.3.4.2. This statistic is a count of PAUSE frames
167 802.3-2012, Section 30.3.4.3. This statistic is a count of PAUSE frames
Dixgbe.txt108 receiving and transmitting pause frames for ixgbe. When TX is enabled, PAUSE
111 specified when a PAUSE frame is received.
Dixgb.txt126 Ethernet PAUSE frames. There are hardware bugs associated with enabling
De1000.txt76 to Ethernet PAUSE frames.
/linux-4.1.27/sound/ppc/
Dpmac.c187 out_le32(&rec->dma->control, (RUN|WAKE|FLUSH|PAUSE) << 16); in snd_pmac_dma_stop()
424 out_le32(&rec->dma->control, (RUN|PAUSE|FLUSH|WAKE) << 16); in snd_pmac_pcm_dead_xfer()
748 out_le32(&chip->playback.dma->control, (RUN|PAUSE|FLUSH|WAKE|DEAD) << 16); in snd_pmac_dbdma_reset()
750 out_le32(&chip->capture.dma->control, (RUN|PAUSE|FLUSH|WAKE|DEAD) << 16); in snd_pmac_dbdma_reset()
/linux-4.1.27/drivers/clk/samsung/
Dclk-exynos5260.h325 #define PAUSE 0x1004 macro
Dclk-exynos5433.c967 #define PAUSE 0x1008 macro
1045 PAUSE,
/linux-4.1.27/drivers/scsi/
Dmac53c94.c113 writel((RUN|PAUSE|FLUSH|WAKE) << 16, &dma->control); in DEF_SCSI_QCMD()
139 writel((RUN|PAUSE|FLUSH|WAKE) << 16, &dma->control); in mac53c94_init()
Dmesh.c366 out_le32(&md->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* stop dma */ in mesh_init()
1715 out_le32(&md->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* stop dma */ in mesh_host_reset()
/linux-4.1.27/sound/aoa/soundbus/i2sbus/
Dpcm.c273 out_le32(&pi->dbdma->control, (RUN | PAUSE | 1) << 16); in i2sbus_wait_for_stop()
576 out_le32(&pi->dbdma->control, (RUN | PAUSE | 1) << 16); in i2sbus_pcm_trigger()
692 out_le32(&pi->dbdma->control, (RUN | PAUSE | 1) << 16); in handle_interrupt()
/linux-4.1.27/Documentation/input/
Datarikbd.txt131 It remains in this mode until reset or commanded into another mode. The PAUSE
141 until reset or commanded into another mode. The PAUSE command in this mode not
359 9.14 PAUSE OUTPUT
377 The output is stopped only at the end of the current 'even'. If the PAUSE
379 will still be transmitted to conclusion and then the PAUSE will take effect.
381 MONITORING mode, the PAUSE OUTPUT command also temporarily stops the
/linux-4.1.27/Documentation/
DSAK.txt26 choose CTRL-ALT-PAUSE.
/linux-4.1.27/Documentation/devicetree/bindings/mips/cavium/
Dbootbus.txt44 - cavium,t-pause: A cell specifying the PAUSE timing (in nS).
/linux-4.1.27/drivers/scsi/aic7xxx/
Daic79xx_pci.c461 ahd_outb(ahd, HCNTRL, hcntrl|PAUSE); in ahd_pci_test_register_access()
Daic7xxx_reg.h_shipped629 #define PAUSE 0x04
Daic7xxx_pci.c1219 ahc_outb(ahc, HCNTRL, hcntrl|PAUSE); in ahc_pci_test_register_access()
Daic7xxx.reg830 field PAUSE 0x04
Daic7xxx_core.c328 return ((ahc_inb(ahc, HCNTRL) & PAUSE) != 0); in ahc_is_paused()
4464 ahc->pause = ahc->unpause | PAUSE; in ahc_softc_init()
Daic79xx_reg.h_shipped1318 #define PAUSE 0x04
Daic79xx_core.c359 return ((ahd_inb(ahd, HCNTRL) & PAUSE) != 0); in ahd_is_paused()
6135 ahd->pause = PAUSE; in ahd_softc_init()
Daic79xx.reg269 field PAUSE 0x04
/linux-4.1.27/drivers/ata/
Dpata_macio.c579 writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma_regs->control); in pata_macio_freeze()
/linux-4.1.27/drivers/block/
Dswim3.c773 out_le32(&dr->control, (RUN | PAUSE) << 16); in swim3_interrupt()
/linux-4.1.27/drivers/ide/
Dpmac.c1471 writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma->control); in pmac_ide_build_dmatable()
/linux-4.1.27/arch/powerpc/platforms/powermac/
Dfeature.c519 out_le32(&chan->control, (ACTIVE|DEAD|WAKE|FLUSH|PAUSE|RUN)<<16); in dbdma_restore()
/linux-4.1.27/arch/x86/lib/
Dx86-opcode-map.txt189 90: NOP | PAUSE (F3) | XCHG r8,rAX