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Searched refs:OUT_RING (Results 1 – 33 of 33) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/nouveau/
Dnvc0_fbcon.c43 OUT_RING (chan, 1); in nvc0_fbcon_fillrect()
48 OUT_RING (chan, ((uint32_t *)info->pseudo_palette)[rect->color]); in nvc0_fbcon_fillrect()
50 OUT_RING (chan, rect->color); in nvc0_fbcon_fillrect()
52 OUT_RING (chan, rect->dx); in nvc0_fbcon_fillrect()
53 OUT_RING (chan, rect->dy); in nvc0_fbcon_fillrect()
54 OUT_RING (chan, rect->dx + rect->width); in nvc0_fbcon_fillrect()
55 OUT_RING (chan, rect->dy + rect->height); in nvc0_fbcon_fillrect()
58 OUT_RING (chan, 3); in nvc0_fbcon_fillrect()
77 OUT_RING (chan, 0); in nvc0_fbcon_copyarea()
79 OUT_RING (chan, region->dx); in nvc0_fbcon_copyarea()
[all …]
Dnv50_fbcon.c43 OUT_RING(chan, 1); in nv50_fbcon_fillrect()
48 OUT_RING(chan, ((uint32_t *)info->pseudo_palette)[rect->color]); in nv50_fbcon_fillrect()
50 OUT_RING(chan, rect->color); in nv50_fbcon_fillrect()
52 OUT_RING(chan, rect->dx); in nv50_fbcon_fillrect()
53 OUT_RING(chan, rect->dy); in nv50_fbcon_fillrect()
54 OUT_RING(chan, rect->dx + rect->width); in nv50_fbcon_fillrect()
55 OUT_RING(chan, rect->dy + rect->height); in nv50_fbcon_fillrect()
58 OUT_RING(chan, 3); in nv50_fbcon_fillrect()
77 OUT_RING(chan, 0); in nv50_fbcon_copyarea()
79 OUT_RING(chan, region->dx); in nv50_fbcon_copyarea()
[all …]
Dnv04_fbcon.c42 OUT_RING(chan, (region->sy << 16) | region->sx); in nv04_fbcon_copyarea()
43 OUT_RING(chan, (region->dy << 16) | region->dx); in nv04_fbcon_copyarea()
44 OUT_RING(chan, (region->height << 16) | region->width); in nv04_fbcon_copyarea()
62 OUT_RING(chan, (rect->rop != ROP_COPY) ? 1 : 3); in nv04_fbcon_fillrect()
66 OUT_RING(chan, ((uint32_t *)info->pseudo_palette)[rect->color]); in nv04_fbcon_fillrect()
68 OUT_RING(chan, rect->color); in nv04_fbcon_fillrect()
70 OUT_RING(chan, (rect->dx << 16) | rect->dy); in nv04_fbcon_fillrect()
71 OUT_RING(chan, (rect->width << 16) | rect->height); in nv04_fbcon_fillrect()
105 OUT_RING(chan, (image->dy << 16) | (image->dx & 0xffff)); in nv04_fbcon_imageblit()
106 OUT_RING(chan, ((image->dy + image->height) << 16) | in nv04_fbcon_imageblit()
[all …]
Dnvc0_fence.c37 OUT_RING (chan, upper_32_bits(virtual)); in nvc0_fence_emit32()
38 OUT_RING (chan, lower_32_bits(virtual)); in nvc0_fence_emit32()
39 OUT_RING (chan, sequence); in nvc0_fence_emit32()
40 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG); in nvc0_fence_emit32()
41 OUT_RING (chan, 0x00000000); in nvc0_fence_emit32()
53 OUT_RING (chan, upper_32_bits(virtual)); in nvc0_fence_sync32()
54 OUT_RING (chan, lower_32_bits(virtual)); in nvc0_fence_sync32()
55 OUT_RING (chan, sequence); in nvc0_fence_sync32()
56 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL | in nvc0_fence_sync32()
Dnouveau_bo.c688 OUT_RING (chan, handle & 0x0000ffff); in nve0_bo_move_init()
702 OUT_RING (chan, upper_32_bits(node->vma[0].offset)); in nve0_bo_move_copy()
703 OUT_RING (chan, lower_32_bits(node->vma[0].offset)); in nve0_bo_move_copy()
704 OUT_RING (chan, upper_32_bits(node->vma[1].offset)); in nve0_bo_move_copy()
705 OUT_RING (chan, lower_32_bits(node->vma[1].offset)); in nve0_bo_move_copy()
706 OUT_RING (chan, PAGE_SIZE); in nve0_bo_move_copy()
707 OUT_RING (chan, PAGE_SIZE); in nve0_bo_move_copy()
708 OUT_RING (chan, PAGE_SIZE); in nve0_bo_move_copy()
709 OUT_RING (chan, new_mem->num_pages); in nve0_bo_move_copy()
721 OUT_RING (chan, handle); in nvc0_bo_move_init()
[all …]
Dnv17_fence.c53 OUT_RING (prev, fctx->sema.handle); in nv17_fence_sync()
54 OUT_RING (prev, 0); in nv17_fence_sync()
55 OUT_RING (prev, value + 0); in nv17_fence_sync()
56 OUT_RING (prev, value + 1); in nv17_fence_sync()
62 OUT_RING (chan, fctx->sema.handle); in nv17_fence_sync()
63 OUT_RING (chan, 0); in nv17_fence_sync()
64 OUT_RING (chan, value + 1); in nv17_fence_sync()
65 OUT_RING (chan, value + 2); in nv17_fence_sync()
Dnouveau_dma.h102 OUT_RING(struct nouveau_channel *chan, int data) in OUT_RING() function
113 OUT_RING(chan, 0x00000000 | (subc << 13) | (size << 18) | mthd); in BEGIN_NV04()
119 OUT_RING(chan, 0x40000000 | (subc << 13) | (size << 18) | mthd); in BEGIN_NI04()
125 OUT_RING(chan, 0x20000000 | (size << 16) | (subc << 13) | (mthd >> 2)); in BEGIN_NVC0()
131 OUT_RING(chan, 0x60000000 | (size << 16) | (subc << 13) | (mthd >> 2)); in BEGIN_NIC0()
137 OUT_RING(chan, 0x80000000 | (data << 16) | (subc << 13) | (mthd >> 2)); in BEGIN_IMC0()
Dnv84_fence.c44 OUT_RING (chan, chan->vram.handle); in nv84_fence_emit32()
46 OUT_RING (chan, upper_32_bits(virtual)); in nv84_fence_emit32()
47 OUT_RING (chan, lower_32_bits(virtual)); in nv84_fence_emit32()
48 OUT_RING (chan, sequence); in nv84_fence_emit32()
49 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG); in nv84_fence_emit32()
50 OUT_RING (chan, 0x00000000); in nv84_fence_emit32()
62 OUT_RING (chan, chan->vram.handle); in nv84_fence_sync32()
64 OUT_RING (chan, upper_32_bits(virtual)); in nv84_fence_sync32()
65 OUT_RING (chan, lower_32_bits(virtual)); in nv84_fence_sync32()
66 OUT_RING (chan, sequence); in nv84_fence_sync32()
[all …]
Dnv50_display.c572 OUT_RING (chan, NvEvoSema0 + nv_crtc->index); in nv50_display_flip_next()
573 OUT_RING (chan, sync->addr ^ 0x10); in nv50_display_flip_next()
575 OUT_RING (chan, sync->data + 1); in nv50_display_flip_next()
577 OUT_RING (chan, sync->addr); in nv50_display_flip_next()
578 OUT_RING (chan, sync->data); in nv50_display_flip_next()
587 OUT_RING (chan, chan->vram.handle); in nv50_display_flip_next()
589 OUT_RING (chan, upper_32_bits(addr ^ 0x10)); in nv50_display_flip_next()
590 OUT_RING (chan, lower_32_bits(addr ^ 0x10)); in nv50_display_flip_next()
591 OUT_RING (chan, sync->data + 1); in nv50_display_flip_next()
592 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG); in nv50_display_flip_next()
[all …]
Dnouveau_display.c681 OUT_RING (chan, 0x00000000); in nouveau_page_flip_emit()
770 OUT_RING (chan, 0); in nouveau_crtc_page_flip()
772 OUT_RING (chan, head); in nouveau_crtc_page_flip()
774 OUT_RING (chan, 0); in nouveau_crtc_page_flip()
776 OUT_RING (chan, 0); in nouveau_crtc_page_flip()
Dnv04_fence.c44 OUT_RING (chan, fence->base.seqno); in nv04_fence_emit()
Dnv10_fence.c36 OUT_RING (chan, fence->base.seqno); in nv10_fence_emit()
Dnouveau_gem.c783 OUT_RING(chan, (nvbo->bo.offset + push[i].offset) | 2); in nouveau_gem_ioctl_pushbuf()
784 OUT_RING(chan, 0); in nouveau_gem_ioctl_pushbuf()
817 OUT_RING(chan, 0x20000000 | in nouveau_gem_ioctl_pushbuf()
819 OUT_RING(chan, 0); in nouveau_gem_ioctl_pushbuf()
821 OUT_RING(chan, 0); in nouveau_gem_ioctl_pushbuf()
Dnouveau_chan.c367 OUT_RING(chan, 0x00000000); in nouveau_channel_init()
385 OUT_RING (chan, chan->nvsw.handle); in nouveau_channel_init()
Dnouveau_dma.c227 OUT_RING(chan, chan->push.vma.offset | 0x20000000); in nouveau_dma_wait()
Dnouveau_drm.c240 OUT_RING (drm->channel, NVDRM_NVSW); in nouveau_accel_init()
244 OUT_RING (drm->channel, 0x001f0000); in nouveau_accel_init()
/linux-4.1.27/drivers/gpu/drm/radeon/
Dr600_blit.c95 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); in set_render_target()
96 OUT_RING((R600_CB_COLOR0_BASE - R600_SET_CONTEXT_REG_OFFSET) >> 2); in set_render_target()
97 OUT_RING(gpu_addr >> 8); in set_render_target()
98 OUT_RING(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0)); in set_render_target()
99 OUT_RING(2 << 0); in set_render_target()
102 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); in set_render_target()
103 OUT_RING((R600_CB_COLOR0_BASE - R600_SET_CONTEXT_REG_OFFSET) >> 2); in set_render_target()
104 OUT_RING(gpu_addr >> 8); in set_render_target()
107 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); in set_render_target()
108 OUT_RING((R600_CB_COLOR0_SIZE - R600_SET_CONTEXT_REG_OFFSET) >> 2); in set_render_target()
[all …]
Dradeon_state.c458 OUT_RING(CP_PACKET0(RADEON_RE_TOP_LEFT, 0)); in radeon_emit_clip_rect()
459 OUT_RING((box->y1 << 16) | box->x1); in radeon_emit_clip_rect()
460 OUT_RING(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0)); in radeon_emit_clip_rect()
461 OUT_RING(((box->y2 - 1) << 16) | (box->x2 - 1)); in radeon_emit_clip_rect()
490 OUT_RING(CP_PACKET0(RADEON_PP_MISC, 6)); in radeon_emit_state()
491 OUT_RING(ctx->pp_misc); in radeon_emit_state()
492 OUT_RING(ctx->pp_fog_color); in radeon_emit_state()
493 OUT_RING(ctx->re_solid_color); in radeon_emit_state()
494 OUT_RING(ctx->rb3d_blendcntl); in radeon_emit_state()
495 OUT_RING(ctx->rb3d_depthoffset); in radeon_emit_state()
[all …]
Dr300_cmdbuf.c75 OUT_RING(CP_PACKET0(R300_RE_CLIPRECT_TL_0, nr * 2 - 1)); in r300_emit_cliprects()
107 OUT_RING((box.x1 << R300_CLIPRECT_X_SHIFT) | in r300_emit_cliprects()
109 OUT_RING((box.x2 << R300_CLIPRECT_X_SHIFT) | in r300_emit_cliprects()
121 OUT_RING(CP_PACKET0(R300_RE_SCISSORS_TL, 1)); in r300_emit_cliprects()
122 OUT_RING(0); in r300_emit_cliprects()
123 OUT_RING(R300_SCISSORS_X_MASK | R300_SCISSORS_Y_MASK); in r300_emit_cliprects()
148 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); in r300_emit_cliprects()
149 OUT_RING(R300_RB3D_DC_FLUSH); in r300_emit_cliprects()
152 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); in r300_emit_cliprects()
153 OUT_RING(RADEON_WAIT_3D_IDLECLEAN); in r300_emit_cliprects()
[all …]
Dradeon_drv.h1930 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1931 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1936 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1937 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
1942 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1943 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1949 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1950 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \
1955 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
1956 OUT_RING(RADEON_RB3D_DC_FLUSH); \
[all …]
Dr600_cp.c2313 OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0)); in r600_do_cp_idle()
2314 OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT); in r600_do_cp_idle()
2316 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); in r600_do_cp_idle()
2317 OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2); in r600_do_cp_idle()
2318 OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN); in r600_do_cp_idle()
2335 OUT_RING(CP_PACKET3(R600_IT_ME_INITIALIZE, 5)); in r600_do_cp_start()
2336 OUT_RING(0x00000001); in r600_do_cp_start()
2338 OUT_RING(0x00000003); in r600_do_cp_start()
2340 OUT_RING(0x00000000); in r600_do_cp_start()
2341 OUT_RING((dev_priv->r600_max_hw_contexts - 1)); in r600_do_cp_start()
[all …]
Dradeon_cp.c619 OUT_RING(CP_PACKET0(R300_CP_RESYNC_ADDR, 1)); in radeon_do_cp_start()
620 OUT_RING(5); /* scratch reg 5 */ in radeon_do_cp_start()
621 OUT_RING(0xdeadbeef); in radeon_do_cp_start()
628 OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0)); in radeon_do_cp_start()
629 OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D | in radeon_do_cp_start()
669 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); in radeon_do_cp_stop()
670 OUT_RING(R300_RB3D_DC_FINISH); in radeon_do_cp_stop()
/linux-4.1.27/drivers/gpu/drm/r128/
Dr128_state.c49 OUT_RING(CCE_PACKET0(R128_AUX1_SC_LEFT, 3)); in r128_emit_clip_rects()
50 OUT_RING(boxes[0].x1); in r128_emit_clip_rects()
51 OUT_RING(boxes[0].x2 - 1); in r128_emit_clip_rects()
52 OUT_RING(boxes[0].y1); in r128_emit_clip_rects()
53 OUT_RING(boxes[0].y2 - 1); in r128_emit_clip_rects()
58 OUT_RING(CCE_PACKET0(R128_AUX2_SC_LEFT, 3)); in r128_emit_clip_rects()
59 OUT_RING(boxes[1].x1); in r128_emit_clip_rects()
60 OUT_RING(boxes[1].x2 - 1); in r128_emit_clip_rects()
61 OUT_RING(boxes[1].y1); in r128_emit_clip_rects()
62 OUT_RING(boxes[1].y2 - 1); in r128_emit_clip_rects()
[all …]
Dr128_drv.h466 OUT_RING(CCE_PACKET0(R128_WAIT_UNTIL, 0)); \
467 OUT_RING(R128_EVENT_CRTC_OFFSET); \
525 #define OUT_RING(x) do { \ macro
/linux-4.1.27/drivers/gpu/drm/i810/
Di810_dma.c465 OUT_RING(GFX_OP_COLOR_FACTOR); in i810EmitContextVerified()
466 OUT_RING(code[I810_CTXREG_CF1]); in i810EmitContextVerified()
468 OUT_RING(GFX_OP_STIPPLE); in i810EmitContextVerified()
469 OUT_RING(code[I810_CTXREG_ST1]); in i810EmitContextVerified()
476 OUT_RING(tmp); in i810EmitContextVerified()
483 OUT_RING(0); in i810EmitContextVerified()
497 OUT_RING(GFX_OP_MAP_INFO); in i810EmitTexVerified()
498 OUT_RING(code[I810_TEXREG_MI1]); in i810EmitTexVerified()
499 OUT_RING(code[I810_TEXREG_MI2]); in i810EmitTexVerified()
500 OUT_RING(code[I810_TEXREG_MI3]); in i810EmitTexVerified()
[all …]
Di810_drv.h165 #define OUT_RING(n) do { \ macro
/linux-4.1.27/drivers/gpu/drm/msm/adreno/
Da4xx_gpu.c115 OUT_RING(ring, 0x000003f7); in a4xx_me_init()
116 OUT_RING(ring, 0x00000000); in a4xx_me_init()
117 OUT_RING(ring, 0x00000000); in a4xx_me_init()
118 OUT_RING(ring, 0x00000000); in a4xx_me_init()
119 OUT_RING(ring, 0x00000080); in a4xx_me_init()
120 OUT_RING(ring, 0x00000100); in a4xx_me_init()
121 OUT_RING(ring, 0x00000180); in a4xx_me_init()
122 OUT_RING(ring, 0x00006600); in a4xx_me_init()
123 OUT_RING(ring, 0x00000150); in a4xx_me_init()
124 OUT_RING(ring, 0x0000014e); in a4xx_me_init()
[all …]
Da3xx_gpu.c49 OUT_RING(ring, 0x000003f7); in a3xx_me_init()
50 OUT_RING(ring, 0x00000000); in a3xx_me_init()
51 OUT_RING(ring, 0x00000000); in a3xx_me_init()
52 OUT_RING(ring, 0x00000000); in a3xx_me_init()
53 OUT_RING(ring, 0x00000080); in a3xx_me_init()
54 OUT_RING(ring, 0x00000100); in a3xx_me_init()
55 OUT_RING(ring, 0x00000180); in a3xx_me_init()
56 OUT_RING(ring, 0x00006600); in a3xx_me_init()
57 OUT_RING(ring, 0x00000150); in a3xx_me_init()
58 OUT_RING(ring, 0x0000014e); in a3xx_me_init()
[all …]
Dadreno_gpu.c141 OUT_RING(ring, submit->cmd[i].iova); in adreno_submit()
142 OUT_RING(ring, submit->cmd[i].size); in adreno_submit()
156 OUT_RING(ring, submit->fence); in adreno_submit()
164 OUT_RING(ring, HLSQ_FLUSH); in adreno_submit()
167 OUT_RING(ring, 0x00000000); in adreno_submit()
171 OUT_RING(ring, CACHE_FLUSH_TS); in adreno_submit()
172 OUT_RING(ring, rbmemptr(adreno_gpu, fence)); in adreno_submit()
173 OUT_RING(ring, submit->fence); in adreno_submit()
177 OUT_RING(ring, 0x80000000); in adreno_submit()
183 OUT_RING(ring, CP_REG(REG_A3XX_HLSQ_CL_KERNEL_GROUP_X_REG)); in adreno_submit()
[all …]
Dadreno_gpu.h250 OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF)); in OUT_PKT0()
258 OUT_RING(ring, CP_TYPE2_PKT); in OUT_PKT2()
265 OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8)); in OUT_PKT3()
/linux-4.1.27/drivers/video/fbdev/intelfb/
Dintelfbhw.c1552 OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE); in do_flush()
1553 OUT_RING(MI_NOOP); in do_flush()
1690 OUT_RING(br00); in intelfbhw_do_fillrect()
1691 OUT_RING(br13); in intelfbhw_do_fillrect()
1692 OUT_RING(br14); in intelfbhw_do_fillrect()
1693 OUT_RING(br09); in intelfbhw_do_fillrect()
1694 OUT_RING(br16); in intelfbhw_do_fillrect()
1695 OUT_RING(MI_NOOP); in intelfbhw_do_fillrect()
1739 OUT_RING(br00); in intelfbhw_do_bitblt()
1740 OUT_RING(br13); in intelfbhw_do_bitblt()
[all …]
Dintelfbhw.h534 #define OUT_RING(n) do { \ macro
/linux-4.1.27/drivers/gpu/drm/msm/
Dmsm_ringbuffer.h36 OUT_RING(struct msm_ringbuffer *ring, uint32_t data) in OUT_RING() function