1/* i810_drv.h -- Private header for the Matrox g200/g400 driver -*- linux-c -*- 2 * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com 3 * 4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 6 * All rights reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the next 16 * paragraph) shall be included in all copies or substantial portions of the 17 * Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 25 * DEALINGS IN THE SOFTWARE. 26 * 27 * Authors: Rickard E. (Rik) Faith <faith@valinux.com> 28 * Jeff Hartmann <jhartmann@valinux.com> 29 * 30 */ 31 32#ifndef _I810_DRV_H_ 33#define _I810_DRV_H_ 34 35#include <drm/drm_legacy.h> 36 37/* General customization: 38 */ 39 40#define DRIVER_AUTHOR "VA Linux Systems Inc." 41 42#define DRIVER_NAME "i810" 43#define DRIVER_DESC "Intel i810" 44#define DRIVER_DATE "20030605" 45 46/* Interface history 47 * 48 * 1.1 - XFree86 4.1 49 * 1.2 - XvMC interfaces 50 * - XFree86 4.2 51 * 1.2.1 - Disable copying code (leave stub ioctls for backwards compatibility) 52 * - Remove requirement for interrupt (leave stubs again) 53 * 1.3 - Add page flipping. 54 * 1.4 - fix DRM interface 55 */ 56#define DRIVER_MAJOR 1 57#define DRIVER_MINOR 4 58#define DRIVER_PATCHLEVEL 0 59 60typedef struct drm_i810_buf_priv { 61 u32 *in_use; 62 int my_use_idx; 63 int currently_mapped; 64 void *virtual; 65 void *kernel_virtual; 66 drm_local_map_t map; 67} drm_i810_buf_priv_t; 68 69typedef struct _drm_i810_ring_buffer { 70 int tail_mask; 71 unsigned long Start; 72 unsigned long End; 73 unsigned long Size; 74 u8 *virtual_start; 75 int head; 76 int tail; 77 int space; 78 drm_local_map_t map; 79} drm_i810_ring_buffer_t; 80 81typedef struct drm_i810_private { 82 struct drm_local_map *sarea_map; 83 struct drm_local_map *mmio_map; 84 85 drm_i810_sarea_t *sarea_priv; 86 drm_i810_ring_buffer_t ring; 87 88 void *hw_status_page; 89 unsigned long counter; 90 91 dma_addr_t dma_status_page; 92 93 struct drm_buf *mmap_buffer; 94 95 u32 front_di1, back_di1, zi1; 96 97 int back_offset; 98 int depth_offset; 99 int overlay_offset; 100 int overlay_physical; 101 int w, h; 102 int pitch; 103 int back_pitch; 104 int depth_pitch; 105 106 int do_boxes; 107 int dma_used; 108 109 int current_page; 110 int page_flipping; 111 112 wait_queue_head_t irq_queue; 113 atomic_t irq_received; 114 atomic_t irq_emitted; 115 116 int front_offset; 117} drm_i810_private_t; 118 119 /* i810_dma.c */ 120extern int i810_driver_dma_quiescent(struct drm_device *dev); 121void i810_driver_reclaim_buffers(struct drm_device *dev, 122 struct drm_file *file_priv); 123extern int i810_driver_load(struct drm_device *, unsigned long flags); 124extern void i810_driver_lastclose(struct drm_device *dev); 125extern void i810_driver_preclose(struct drm_device *dev, 126 struct drm_file *file_priv); 127extern int i810_driver_device_is_agp(struct drm_device *dev); 128 129extern long i810_ioctl(struct file *file, unsigned int cmd, unsigned long arg); 130extern const struct drm_ioctl_desc i810_ioctls[]; 131extern int i810_max_ioctl; 132 133#define I810_BASE(reg) ((unsigned long) \ 134 dev_priv->mmio_map->handle) 135#define I810_ADDR(reg) (I810_BASE(reg) + reg) 136#define I810_DEREF(reg) (*(__volatile__ int *)I810_ADDR(reg)) 137#define I810_READ(reg) I810_DEREF(reg) 138#define I810_WRITE(reg, val) do { I810_DEREF(reg) = val; } while (0) 139#define I810_DEREF16(reg) (*(__volatile__ u16 *)I810_ADDR(reg)) 140#define I810_READ16(reg) I810_DEREF16(reg) 141#define I810_WRITE16(reg, val) do { I810_DEREF16(reg) = val; } while (0) 142 143#define I810_VERBOSE 0 144#define RING_LOCALS unsigned int outring, ringmask; \ 145 volatile char *virt; 146 147#define BEGIN_LP_RING(n) do { \ 148 if (I810_VERBOSE) \ 149 DRM_DEBUG("BEGIN_LP_RING(%d)\n", n); \ 150 if (dev_priv->ring.space < n*4) \ 151 i810_wait_ring(dev, n*4); \ 152 dev_priv->ring.space -= n*4; \ 153 outring = dev_priv->ring.tail; \ 154 ringmask = dev_priv->ring.tail_mask; \ 155 virt = dev_priv->ring.virtual_start; \ 156} while (0) 157 158#define ADVANCE_LP_RING() do { \ 159 if (I810_VERBOSE) \ 160 DRM_DEBUG("ADVANCE_LP_RING\n"); \ 161 dev_priv->ring.tail = outring; \ 162 I810_WRITE(LP_RING + RING_TAIL, outring); \ 163} while (0) 164 165#define OUT_RING(n) do { \ 166 if (I810_VERBOSE) \ 167 DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \ 168 *(volatile unsigned int *)(virt + outring) = n; \ 169 outring += 4; \ 170 outring &= ringmask; \ 171} while (0) 172 173#define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23)) 174#define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23)) 175#define CMD_REPORT_HEAD (7<<23) 176#define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1) 177#define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1) 178 179#define INST_PARSER_CLIENT 0x00000000 180#define INST_OP_FLUSH 0x02000000 181#define INST_FLUSH_MAP_CACHE 0x00000001 182 183#define BB1_START_ADDR_MASK (~0x7) 184#define BB1_PROTECTED (1<<0) 185#define BB1_UNPROTECTED (0<<0) 186#define BB2_END_ADDR_MASK (~0x7) 187 188#define I810REG_HWSTAM 0x02098 189#define I810REG_INT_IDENTITY_R 0x020a4 190#define I810REG_INT_MASK_R 0x020a8 191#define I810REG_INT_ENABLE_R 0x020a0 192 193#define LP_RING 0x2030 194#define HP_RING 0x2040 195#define RING_TAIL 0x00 196#define TAIL_ADDR 0x000FFFF8 197#define RING_HEAD 0x04 198#define HEAD_WRAP_COUNT 0xFFE00000 199#define HEAD_WRAP_ONE 0x00200000 200#define HEAD_ADDR 0x001FFFFC 201#define RING_START 0x08 202#define START_ADDR 0x00FFFFF8 203#define RING_LEN 0x0C 204#define RING_NR_PAGES 0x000FF000 205#define RING_REPORT_MASK 0x00000006 206#define RING_REPORT_64K 0x00000002 207#define RING_REPORT_128K 0x00000004 208#define RING_NO_REPORT 0x00000000 209#define RING_VALID_MASK 0x00000001 210#define RING_VALID 0x00000001 211#define RING_INVALID 0x00000000 212 213#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 214#define SC_UPDATE_SCISSOR (0x1<<1) 215#define SC_ENABLE_MASK (0x1<<0) 216#define SC_ENABLE (0x1<<0) 217 218#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) 219#define SCI_YMIN_MASK (0xffff<<16) 220#define SCI_XMIN_MASK (0xffff<<0) 221#define SCI_YMAX_MASK (0xffff<<16) 222#define SCI_XMAX_MASK (0xffff<<0) 223 224#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) 225#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) 226#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x2) 227#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) 228#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) 229#define GFX_OP_PRIMITIVE ((0x3<<29)|(0x1f<<24)) 230 231#define CMD_OP_Z_BUFFER_INFO ((0x0<<29)|(0x16<<23)) 232#define CMD_OP_DESTBUFFER_INFO ((0x0<<29)|(0x15<<23)) 233#define CMD_OP_FRONTBUFFER_INFO ((0x0<<29)|(0x14<<23)) 234#define CMD_OP_WAIT_FOR_EVENT ((0x0<<29)|(0x03<<23)) 235 236#define BR00_BITBLT_CLIENT 0x40000000 237#define BR00_OP_COLOR_BLT 0x10000000 238#define BR00_OP_SRC_COPY_BLT 0x10C00000 239#define BR13_SOLID_PATTERN 0x80000000 240 241#define WAIT_FOR_PLANE_A_SCANLINES (1<<1) 242#define WAIT_FOR_PLANE_A_FLIP (1<<2) 243#define WAIT_FOR_VBLANK (1<<3) 244 245#endif 246