572 		OUT_RING  (chan, NvEvoSema0 + nv_crtc->index);  in nv50_display_flip_next()
573 		OUT_RING  (chan, sync->addr ^ 0x10);  in nv50_display_flip_next()
575 		OUT_RING  (chan, sync->data + 1);  in nv50_display_flip_next()
577 		OUT_RING  (chan, sync->addr);  in nv50_display_flip_next()
578 		OUT_RING  (chan, sync->data);  in nv50_display_flip_next()
587 		OUT_RING  (chan, chan->vram.handle);  in nv50_display_flip_next()
589 		OUT_RING  (chan, upper_32_bits(addr ^ 0x10));  in nv50_display_flip_next()
590 		OUT_RING  (chan, lower_32_bits(addr ^ 0x10));  in nv50_display_flip_next()
591 		OUT_RING  (chan, sync->data + 1);  in nv50_display_flip_next()
592 		OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);  in nv50_display_flip_next()
594 		OUT_RING  (chan, upper_32_bits(addr));  in nv50_display_flip_next()
595 		OUT_RING  (chan, lower_32_bits(addr));  in nv50_display_flip_next()
596 		OUT_RING  (chan, sync->data);  in nv50_display_flip_next()
597 		OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL);  in nv50_display_flip_next()
606 		OUT_RING  (chan, upper_32_bits(addr ^ 0x10));  in nv50_display_flip_next()
607 		OUT_RING  (chan, lower_32_bits(addr ^ 0x10));  in nv50_display_flip_next()
608 		OUT_RING  (chan, sync->data + 1);  in nv50_display_flip_next()
609 		OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG |  in nv50_display_flip_next()
612 		OUT_RING  (chan, upper_32_bits(addr));  in nv50_display_flip_next()
613 		OUT_RING  (chan, lower_32_bits(addr));  in nv50_display_flip_next()
614 		OUT_RING  (chan, sync->data);  in nv50_display_flip_next()
615 		OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL |  in nv50_display_flip_next()