Searched refs:HPRT0 (Results 1 - 7 of 7) sorted by relevance
/linux-4.1.27/drivers/usb/dwc2/ |
H A D | hcd.c | 210 writel(hprt0, hsotg->regs + HPRT0); dwc2_hcd_start() 304 writel(0, hsotg->regs + HPRT0); dwc2_hcd_disconnect() 357 writel(0, hsotg->regs + HPRT0); dwc2_hcd_stop() 382 u32 hprt0 = readl(hsotg->regs + HPRT0); dwc2_hcd_urb_enqueue() 1421 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0); dwc2_wakeup_detected() 1423 writel(hprt0, hsotg->regs + HPRT0); dwc2_wakeup_detected() 1424 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n", dwc2_wakeup_detected() 1425 readl(hsotg->regs + HPRT0)); dwc2_wakeup_detected() 1461 writel(hprt0, hsotg->regs + HPRT0); dwc2_port_suspend() 1525 writel(hprt0, hsotg->regs + HPRT0); dwc2_hcd_hub_control() 1536 writel(hprt0, hsotg->regs + HPRT0); dwc2_hcd_hub_control() 1541 writel(hprt0, hsotg->regs + HPRT0); dwc2_hcd_hub_control() 1549 writel(hprt0, hsotg->regs + HPRT0); dwc2_hcd_hub_control() 1670 hprt0 = readl(hsotg->regs + HPRT0); dwc2_hcd_hub_control() 1671 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0); dwc2_hcd_hub_control() 1735 writel(hprt0, hsotg->regs + HPRT0); dwc2_hcd_hub_control() 1761 writel(hprt0, hsotg->regs + HPRT0); dwc2_hcd_hub_control() 1767 writel(hprt0, hsotg->regs + HPRT0); dwc2_hcd_hub_control() 2255 writel(hprt0, hsotg->regs + HPRT0); dwc2_hcd_reset_func()
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H A D | core_intr.c | 83 u32 hprt0 = readl(hsotg->regs + HPRT0); dwc2_handle_usb_port_intr() 87 writel(hprt0, hsotg->regs + HPRT0); dwc2_handle_usb_port_intr() 510 * The port interrupt occurs while in device mode with HPRT0 dwc2_handle_common_intr()
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H A D | hcd_intr.c | 335 hprt0 = readl(hsotg->regs + HPRT0); dwc2_port_intr() 339 * Clear appropriate bits in HPRT0 to clear the interrupt bit in dwc2_port_intr() 351 "--Port Interrupt HPRT0=0x%08x Port Connect Detected--\n", dwc2_port_intr() 369 " --Port Interrupt HPRT0=0x%08x Port Enable Changed (now %d)--\n", dwc2_port_intr() 381 " --Port Interrupt HPRT0=0x%08x Port Overcurrent Changed--\n", dwc2_port_intr() 388 writel(hprt0_modify, hsotg->regs + HPRT0); dwc2_port_intr()
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H A D | hcd.h | 393 * Reads HPRT0 in preparation to modify. It keeps the WC bits 0 so that if they 398 u32 hprt0 = readl(hsotg->regs + HPRT0); dwc2_read_hprt0()
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H A D | core.c | 764 writel(hprt0, hsotg->regs + HPRT0); dwc2_core_host_init() 1734 hprt0 = readl(hsotg->regs + HPRT0); dwc2_calc_frame_interval() 1832 addr = hsotg->regs + HPRT0; dwc2_dump_host_registers() 1833 dev_dbg(hsotg->dev, "HPRT0 @0x%08lX : 0x%08X\n", dwc2_dump_host_registers()
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H A D | hcd_queue.c | 118 hprt = readl(hsotg->regs + HPRT0); dwc2_qh_init()
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H A D | hw.h | 682 #define HPRT0 HSOTG_REG(0x0440) macro
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