1/* 2 * hw.h - DesignWare HS OTG Controller hardware definitions 3 * 4 * Copyright 2004-2013 Synopsys, Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The names of the above-listed copyright holders may not be used 16 * to endorse or promote products derived from this software without 17 * specific prior written permission. 18 * 19 * ALTERNATIVELY, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") as published by the Free Software 21 * Foundation; either version 2 of the License, or (at your option) any 22 * later version. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37#ifndef __DWC2_HW_H__ 38#define __DWC2_HW_H__ 39 40#define HSOTG_REG(x) (x) 41 42#define GOTGCTL HSOTG_REG(0x000) 43#define GOTGCTL_CHIRPEN (1 << 27) 44#define GOTGCTL_MULT_VALID_BC_MASK (0x1f << 22) 45#define GOTGCTL_MULT_VALID_BC_SHIFT 22 46#define GOTGCTL_OTGVER (1 << 20) 47#define GOTGCTL_BSESVLD (1 << 19) 48#define GOTGCTL_ASESVLD (1 << 18) 49#define GOTGCTL_DBNC_SHORT (1 << 17) 50#define GOTGCTL_CONID_B (1 << 16) 51#define GOTGCTL_DEVHNPEN (1 << 11) 52#define GOTGCTL_HSTSETHNPEN (1 << 10) 53#define GOTGCTL_HNPREQ (1 << 9) 54#define GOTGCTL_HSTNEGSCS (1 << 8) 55#define GOTGCTL_SESREQ (1 << 1) 56#define GOTGCTL_SESREQSCS (1 << 0) 57 58#define GOTGINT HSOTG_REG(0x004) 59#define GOTGINT_DBNCE_DONE (1 << 19) 60#define GOTGINT_A_DEV_TOUT_CHG (1 << 18) 61#define GOTGINT_HST_NEG_DET (1 << 17) 62#define GOTGINT_HST_NEG_SUC_STS_CHNG (1 << 9) 63#define GOTGINT_SES_REQ_SUC_STS_CHNG (1 << 8) 64#define GOTGINT_SES_END_DET (1 << 2) 65 66#define GAHBCFG HSOTG_REG(0x008) 67#define GAHBCFG_AHB_SINGLE (1 << 23) 68#define GAHBCFG_NOTI_ALL_DMA_WRIT (1 << 22) 69#define GAHBCFG_REM_MEM_SUPP (1 << 21) 70#define GAHBCFG_P_TXF_EMP_LVL (1 << 8) 71#define GAHBCFG_NP_TXF_EMP_LVL (1 << 7) 72#define GAHBCFG_DMA_EN (1 << 5) 73#define GAHBCFG_HBSTLEN_MASK (0xf << 1) 74#define GAHBCFG_HBSTLEN_SHIFT 1 75#define GAHBCFG_HBSTLEN_SINGLE 0 76#define GAHBCFG_HBSTLEN_INCR 1 77#define GAHBCFG_HBSTLEN_INCR4 3 78#define GAHBCFG_HBSTLEN_INCR8 5 79#define GAHBCFG_HBSTLEN_INCR16 7 80#define GAHBCFG_GLBL_INTR_EN (1 << 0) 81#define GAHBCFG_CTRL_MASK (GAHBCFG_P_TXF_EMP_LVL | \ 82 GAHBCFG_NP_TXF_EMP_LVL | \ 83 GAHBCFG_DMA_EN | \ 84 GAHBCFG_GLBL_INTR_EN) 85 86#define GUSBCFG HSOTG_REG(0x00C) 87#define GUSBCFG_FORCEDEVMODE (1 << 30) 88#define GUSBCFG_FORCEHOSTMODE (1 << 29) 89#define GUSBCFG_TXENDDELAY (1 << 28) 90#define GUSBCFG_ICTRAFFICPULLREMOVE (1 << 27) 91#define GUSBCFG_ICUSBCAP (1 << 26) 92#define GUSBCFG_ULPI_INT_PROT_DIS (1 << 25) 93#define GUSBCFG_INDICATORPASSTHROUGH (1 << 24) 94#define GUSBCFG_INDICATORCOMPLEMENT (1 << 23) 95#define GUSBCFG_TERMSELDLPULSE (1 << 22) 96#define GUSBCFG_ULPI_INT_VBUS_IND (1 << 21) 97#define GUSBCFG_ULPI_EXT_VBUS_DRV (1 << 20) 98#define GUSBCFG_ULPI_CLK_SUSP_M (1 << 19) 99#define GUSBCFG_ULPI_AUTO_RES (1 << 18) 100#define GUSBCFG_ULPI_FS_LS (1 << 17) 101#define GUSBCFG_OTG_UTMI_FS_SEL (1 << 16) 102#define GUSBCFG_PHY_LP_CLK_SEL (1 << 15) 103#define GUSBCFG_USBTRDTIM_MASK (0xf << 10) 104#define GUSBCFG_USBTRDTIM_SHIFT 10 105#define GUSBCFG_HNPCAP (1 << 9) 106#define GUSBCFG_SRPCAP (1 << 8) 107#define GUSBCFG_DDRSEL (1 << 7) 108#define GUSBCFG_PHYSEL (1 << 6) 109#define GUSBCFG_FSINTF (1 << 5) 110#define GUSBCFG_ULPI_UTMI_SEL (1 << 4) 111#define GUSBCFG_PHYIF16 (1 << 3) 112#define GUSBCFG_PHYIF8 (0 << 3) 113#define GUSBCFG_TOUTCAL_MASK (0x7 << 0) 114#define GUSBCFG_TOUTCAL_SHIFT 0 115#define GUSBCFG_TOUTCAL_LIMIT 0x7 116#define GUSBCFG_TOUTCAL(_x) ((_x) << 0) 117 118#define GRSTCTL HSOTG_REG(0x010) 119#define GRSTCTL_AHBIDLE (1 << 31) 120#define GRSTCTL_DMAREQ (1 << 30) 121#define GRSTCTL_TXFNUM_MASK (0x1f << 6) 122#define GRSTCTL_TXFNUM_SHIFT 6 123#define GRSTCTL_TXFNUM_LIMIT 0x1f 124#define GRSTCTL_TXFNUM(_x) ((_x) << 6) 125#define GRSTCTL_TXFFLSH (1 << 5) 126#define GRSTCTL_RXFFLSH (1 << 4) 127#define GRSTCTL_IN_TKNQ_FLSH (1 << 3) 128#define GRSTCTL_FRMCNTRRST (1 << 2) 129#define GRSTCTL_HSFTRST (1 << 1) 130#define GRSTCTL_CSFTRST (1 << 0) 131 132#define GINTSTS HSOTG_REG(0x014) 133#define GINTMSK HSOTG_REG(0x018) 134#define GINTSTS_WKUPINT (1 << 31) 135#define GINTSTS_SESSREQINT (1 << 30) 136#define GINTSTS_DISCONNINT (1 << 29) 137#define GINTSTS_CONIDSTSCHNG (1 << 28) 138#define GINTSTS_LPMTRANRCVD (1 << 27) 139#define GINTSTS_PTXFEMP (1 << 26) 140#define GINTSTS_HCHINT (1 << 25) 141#define GINTSTS_PRTINT (1 << 24) 142#define GINTSTS_RESETDET (1 << 23) 143#define GINTSTS_FET_SUSP (1 << 22) 144#define GINTSTS_INCOMPL_IP (1 << 21) 145#define GINTSTS_INCOMPL_SOIN (1 << 20) 146#define GINTSTS_OEPINT (1 << 19) 147#define GINTSTS_IEPINT (1 << 18) 148#define GINTSTS_EPMIS (1 << 17) 149#define GINTSTS_RESTOREDONE (1 << 16) 150#define GINTSTS_EOPF (1 << 15) 151#define GINTSTS_ISOUTDROP (1 << 14) 152#define GINTSTS_ENUMDONE (1 << 13) 153#define GINTSTS_USBRST (1 << 12) 154#define GINTSTS_USBSUSP (1 << 11) 155#define GINTSTS_ERLYSUSP (1 << 10) 156#define GINTSTS_I2CINT (1 << 9) 157#define GINTSTS_ULPI_CK_INT (1 << 8) 158#define GINTSTS_GOUTNAKEFF (1 << 7) 159#define GINTSTS_GINNAKEFF (1 << 6) 160#define GINTSTS_NPTXFEMP (1 << 5) 161#define GINTSTS_RXFLVL (1 << 4) 162#define GINTSTS_SOF (1 << 3) 163#define GINTSTS_OTGINT (1 << 2) 164#define GINTSTS_MODEMIS (1 << 1) 165#define GINTSTS_CURMODE_HOST (1 << 0) 166 167#define GRXSTSR HSOTG_REG(0x01C) 168#define GRXSTSP HSOTG_REG(0x020) 169#define GRXSTS_FN_MASK (0x7f << 25) 170#define GRXSTS_FN_SHIFT 25 171#define GRXSTS_PKTSTS_MASK (0xf << 17) 172#define GRXSTS_PKTSTS_SHIFT 17 173#define GRXSTS_PKTSTS_GLOBALOUTNAK 1 174#define GRXSTS_PKTSTS_OUTRX 2 175#define GRXSTS_PKTSTS_HCHIN 2 176#define GRXSTS_PKTSTS_OUTDONE 3 177#define GRXSTS_PKTSTS_HCHIN_XFER_COMP 3 178#define GRXSTS_PKTSTS_SETUPDONE 4 179#define GRXSTS_PKTSTS_DATATOGGLEERR 5 180#define GRXSTS_PKTSTS_SETUPRX 6 181#define GRXSTS_PKTSTS_HCHHALTED 7 182#define GRXSTS_HCHNUM_MASK (0xf << 0) 183#define GRXSTS_HCHNUM_SHIFT 0 184#define GRXSTS_DPID_MASK (0x3 << 15) 185#define GRXSTS_DPID_SHIFT 15 186#define GRXSTS_BYTECNT_MASK (0x7ff << 4) 187#define GRXSTS_BYTECNT_SHIFT 4 188#define GRXSTS_EPNUM_MASK (0xf << 0) 189#define GRXSTS_EPNUM_SHIFT 0 190 191#define GRXFSIZ HSOTG_REG(0x024) 192#define GRXFSIZ_DEPTH_MASK (0xffff << 0) 193#define GRXFSIZ_DEPTH_SHIFT 0 194 195#define GNPTXFSIZ HSOTG_REG(0x028) 196/* Use FIFOSIZE_* constants to access this register */ 197 198#define GNPTXSTS HSOTG_REG(0x02C) 199#define GNPTXSTS_NP_TXQ_TOP_MASK (0x7f << 24) 200#define GNPTXSTS_NP_TXQ_TOP_SHIFT 24 201#define GNPTXSTS_NP_TXQ_SPC_AVAIL_MASK (0xff << 16) 202#define GNPTXSTS_NP_TXQ_SPC_AVAIL_SHIFT 16 203#define GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(_v) (((_v) >> 16) & 0xff) 204#define GNPTXSTS_NP_TXF_SPC_AVAIL_MASK (0xffff << 0) 205#define GNPTXSTS_NP_TXF_SPC_AVAIL_SHIFT 0 206#define GNPTXSTS_NP_TXF_SPC_AVAIL_GET(_v) (((_v) >> 0) & 0xffff) 207 208#define GI2CCTL HSOTG_REG(0x0030) 209#define GI2CCTL_BSYDNE (1 << 31) 210#define GI2CCTL_RW (1 << 30) 211#define GI2CCTL_I2CDATSE0 (1 << 28) 212#define GI2CCTL_I2CDEVADDR_MASK (0x3 << 26) 213#define GI2CCTL_I2CDEVADDR_SHIFT 26 214#define GI2CCTL_I2CSUSPCTL (1 << 25) 215#define GI2CCTL_ACK (1 << 24) 216#define GI2CCTL_I2CEN (1 << 23) 217#define GI2CCTL_ADDR_MASK (0x7f << 16) 218#define GI2CCTL_ADDR_SHIFT 16 219#define GI2CCTL_REGADDR_MASK (0xff << 8) 220#define GI2CCTL_REGADDR_SHIFT 8 221#define GI2CCTL_RWDATA_MASK (0xff << 0) 222#define GI2CCTL_RWDATA_SHIFT 0 223 224#define GPVNDCTL HSOTG_REG(0x0034) 225#define GGPIO HSOTG_REG(0x0038) 226#define GUID HSOTG_REG(0x003c) 227#define GSNPSID HSOTG_REG(0x0040) 228#define GHWCFG1 HSOTG_REG(0x0044) 229 230#define GHWCFG2 HSOTG_REG(0x0048) 231#define GHWCFG2_OTG_ENABLE_IC_USB (1 << 31) 232#define GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK (0x1f << 26) 233#define GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT 26 234#define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK (0x3 << 24) 235#define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT 24 236#define GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK (0x3 << 22) 237#define GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT 22 238#define GHWCFG2_MULTI_PROC_INT (1 << 20) 239#define GHWCFG2_DYNAMIC_FIFO (1 << 19) 240#define GHWCFG2_PERIO_EP_SUPPORTED (1 << 18) 241#define GHWCFG2_NUM_HOST_CHAN_MASK (0xf << 14) 242#define GHWCFG2_NUM_HOST_CHAN_SHIFT 14 243#define GHWCFG2_NUM_DEV_EP_MASK (0xf << 10) 244#define GHWCFG2_NUM_DEV_EP_SHIFT 10 245#define GHWCFG2_FS_PHY_TYPE_MASK (0x3 << 8) 246#define GHWCFG2_FS_PHY_TYPE_SHIFT 8 247#define GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED 0 248#define GHWCFG2_FS_PHY_TYPE_DEDICATED 1 249#define GHWCFG2_FS_PHY_TYPE_SHARED_UTMI 2 250#define GHWCFG2_FS_PHY_TYPE_SHARED_ULPI 3 251#define GHWCFG2_HS_PHY_TYPE_MASK (0x3 << 6) 252#define GHWCFG2_HS_PHY_TYPE_SHIFT 6 253#define GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0 254#define GHWCFG2_HS_PHY_TYPE_UTMI 1 255#define GHWCFG2_HS_PHY_TYPE_ULPI 2 256#define GHWCFG2_HS_PHY_TYPE_UTMI_ULPI 3 257#define GHWCFG2_POINT2POINT (1 << 5) 258#define GHWCFG2_ARCHITECTURE_MASK (0x3 << 3) 259#define GHWCFG2_ARCHITECTURE_SHIFT 3 260#define GHWCFG2_SLAVE_ONLY_ARCH 0 261#define GHWCFG2_EXT_DMA_ARCH 1 262#define GHWCFG2_INT_DMA_ARCH 2 263#define GHWCFG2_OP_MODE_MASK (0x7 << 0) 264#define GHWCFG2_OP_MODE_SHIFT 0 265#define GHWCFG2_OP_MODE_HNP_SRP_CAPABLE 0 266#define GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE 1 267#define GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE 2 268#define GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3 269#define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4 270#define GHWCFG2_OP_MODE_SRP_CAPABLE_HOST 5 271#define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6 272#define GHWCFG2_OP_MODE_UNDEFINED 7 273 274#define GHWCFG3 HSOTG_REG(0x004c) 275#define GHWCFG3_DFIFO_DEPTH_MASK (0xffff << 16) 276#define GHWCFG3_DFIFO_DEPTH_SHIFT 16 277#define GHWCFG3_OTG_LPM_EN (1 << 15) 278#define GHWCFG3_BC_SUPPORT (1 << 14) 279#define GHWCFG3_OTG_ENABLE_HSIC (1 << 13) 280#define GHWCFG3_ADP_SUPP (1 << 12) 281#define GHWCFG3_SYNCH_RESET_TYPE (1 << 11) 282#define GHWCFG3_OPTIONAL_FEATURES (1 << 10) 283#define GHWCFG3_VENDOR_CTRL_IF (1 << 9) 284#define GHWCFG3_I2C (1 << 8) 285#define GHWCFG3_OTG_FUNC (1 << 7) 286#define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK (0x7 << 4) 287#define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT 4 288#define GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK (0xf << 0) 289#define GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT 0 290 291#define GHWCFG4 HSOTG_REG(0x0050) 292#define GHWCFG4_DESC_DMA_DYN (1 << 31) 293#define GHWCFG4_DESC_DMA (1 << 30) 294#define GHWCFG4_NUM_IN_EPS_MASK (0xf << 26) 295#define GHWCFG4_NUM_IN_EPS_SHIFT 26 296#define GHWCFG4_DED_FIFO_EN (1 << 25) 297#define GHWCFG4_DED_FIFO_SHIFT 25 298#define GHWCFG4_SESSION_END_FILT_EN (1 << 24) 299#define GHWCFG4_B_VALID_FILT_EN (1 << 23) 300#define GHWCFG4_A_VALID_FILT_EN (1 << 22) 301#define GHWCFG4_VBUS_VALID_FILT_EN (1 << 21) 302#define GHWCFG4_IDDIG_FILT_EN (1 << 20) 303#define GHWCFG4_NUM_DEV_MODE_CTRL_EP_MASK (0xf << 16) 304#define GHWCFG4_NUM_DEV_MODE_CTRL_EP_SHIFT 16 305#define GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK (0x3 << 14) 306#define GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT 14 307#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8 0 308#define GHWCFG4_UTMI_PHY_DATA_WIDTH_16 1 309#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16 2 310#define GHWCFG4_XHIBER (1 << 7) 311#define GHWCFG4_HIBER (1 << 6) 312#define GHWCFG4_MIN_AHB_FREQ (1 << 5) 313#define GHWCFG4_POWER_OPTIMIZ (1 << 4) 314#define GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK (0xf << 0) 315#define GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT 0 316 317#define GLPMCFG HSOTG_REG(0x0054) 318#define GLPMCFG_INV_SEL_HSIC (1 << 31) 319#define GLPMCFG_HSIC_CONNECT (1 << 30) 320#define GLPMCFG_RETRY_COUNT_STS_MASK (0x7 << 25) 321#define GLPMCFG_RETRY_COUNT_STS_SHIFT 25 322#define GLPMCFG_SEND_LPM (1 << 24) 323#define GLPMCFG_RETRY_COUNT_MASK (0x7 << 21) 324#define GLPMCFG_RETRY_COUNT_SHIFT 21 325#define GLPMCFG_LPM_CHAN_INDEX_MASK (0xf << 17) 326#define GLPMCFG_LPM_CHAN_INDEX_SHIFT 17 327#define GLPMCFG_SLEEP_STATE_RESUMEOK (1 << 16) 328#define GLPMCFG_PRT_SLEEP_STS (1 << 15) 329#define GLPMCFG_LPM_RESP_MASK (0x3 << 13) 330#define GLPMCFG_LPM_RESP_SHIFT 13 331#define GLPMCFG_HIRD_THRES_MASK (0x1f << 8) 332#define GLPMCFG_HIRD_THRES_SHIFT 8 333#define GLPMCFG_HIRD_THRES_EN (0x10 << 8) 334#define GLPMCFG_EN_UTMI_SLEEP (1 << 7) 335#define GLPMCFG_REM_WKUP_EN (1 << 6) 336#define GLPMCFG_HIRD_MASK (0xf << 2) 337#define GLPMCFG_HIRD_SHIFT 2 338#define GLPMCFG_APPL_RESP (1 << 1) 339#define GLPMCFG_LPM_CAP_EN (1 << 0) 340 341#define GPWRDN HSOTG_REG(0x0058) 342#define GPWRDN_MULT_VAL_ID_BC_MASK (0x1f << 24) 343#define GPWRDN_MULT_VAL_ID_BC_SHIFT 24 344#define GPWRDN_ADP_INT (1 << 23) 345#define GPWRDN_BSESSVLD (1 << 22) 346#define GPWRDN_IDSTS (1 << 21) 347#define GPWRDN_LINESTATE_MASK (0x3 << 19) 348#define GPWRDN_LINESTATE_SHIFT 19 349#define GPWRDN_STS_CHGINT_MSK (1 << 18) 350#define GPWRDN_STS_CHGINT (1 << 17) 351#define GPWRDN_SRP_DET_MSK (1 << 16) 352#define GPWRDN_SRP_DET (1 << 15) 353#define GPWRDN_CONNECT_DET_MSK (1 << 14) 354#define GPWRDN_CONNECT_DET (1 << 13) 355#define GPWRDN_DISCONN_DET_MSK (1 << 12) 356#define GPWRDN_DISCONN_DET (1 << 11) 357#define GPWRDN_RST_DET_MSK (1 << 10) 358#define GPWRDN_RST_DET (1 << 9) 359#define GPWRDN_LNSTSCHG_MSK (1 << 8) 360#define GPWRDN_LNSTSCHG (1 << 7) 361#define GPWRDN_DIS_VBUS (1 << 6) 362#define GPWRDN_PWRDNSWTCH (1 << 5) 363#define GPWRDN_PWRDNRSTN (1 << 4) 364#define GPWRDN_PWRDNCLMP (1 << 3) 365#define GPWRDN_RESTORE (1 << 2) 366#define GPWRDN_PMUACTV (1 << 1) 367#define GPWRDN_PMUINTSEL (1 << 0) 368 369#define GDFIFOCFG HSOTG_REG(0x005c) 370#define GDFIFOCFG_EPINFOBASE_MASK (0xffff << 16) 371#define GDFIFOCFG_EPINFOBASE_SHIFT 16 372#define GDFIFOCFG_GDFIFOCFG_MASK (0xffff << 0) 373#define GDFIFOCFG_GDFIFOCFG_SHIFT 0 374 375#define ADPCTL HSOTG_REG(0x0060) 376#define ADPCTL_AR_MASK (0x3 << 27) 377#define ADPCTL_AR_SHIFT 27 378#define ADPCTL_ADP_TMOUT_INT_MSK (1 << 26) 379#define ADPCTL_ADP_SNS_INT_MSK (1 << 25) 380#define ADPCTL_ADP_PRB_INT_MSK (1 << 24) 381#define ADPCTL_ADP_TMOUT_INT (1 << 23) 382#define ADPCTL_ADP_SNS_INT (1 << 22) 383#define ADPCTL_ADP_PRB_INT (1 << 21) 384#define ADPCTL_ADPENA (1 << 20) 385#define ADPCTL_ADPRES (1 << 19) 386#define ADPCTL_ENASNS (1 << 18) 387#define ADPCTL_ENAPRB (1 << 17) 388#define ADPCTL_RTIM_MASK (0x7ff << 6) 389#define ADPCTL_RTIM_SHIFT 6 390#define ADPCTL_PRB_PER_MASK (0x3 << 4) 391#define ADPCTL_PRB_PER_SHIFT 4 392#define ADPCTL_PRB_DELTA_MASK (0x3 << 2) 393#define ADPCTL_PRB_DELTA_SHIFT 2 394#define ADPCTL_PRB_DSCHRG_MASK (0x3 << 0) 395#define ADPCTL_PRB_DSCHRG_SHIFT 0 396 397#define HPTXFSIZ HSOTG_REG(0x100) 398/* Use FIFOSIZE_* constants to access this register */ 399 400#define DPTXFSIZN(_a) HSOTG_REG(0x104 + (((_a) - 1) * 4)) 401/* Use FIFOSIZE_* constants to access this register */ 402 403/* These apply to the GNPTXFSIZ, HPTXFSIZ and DPTXFSIZN registers */ 404#define FIFOSIZE_DEPTH_MASK (0xffff << 16) 405#define FIFOSIZE_DEPTH_SHIFT 16 406#define FIFOSIZE_STARTADDR_MASK (0xffff << 0) 407#define FIFOSIZE_STARTADDR_SHIFT 0 408#define FIFOSIZE_DEPTH_GET(_x) (((_x) >> 16) & 0xffff) 409 410/* Device mode registers */ 411 412#define DCFG HSOTG_REG(0x800) 413#define DCFG_EPMISCNT_MASK (0x1f << 18) 414#define DCFG_EPMISCNT_SHIFT 18 415#define DCFG_EPMISCNT_LIMIT 0x1f 416#define DCFG_EPMISCNT(_x) ((_x) << 18) 417#define DCFG_PERFRINT_MASK (0x3 << 11) 418#define DCFG_PERFRINT_SHIFT 11 419#define DCFG_PERFRINT_LIMIT 0x3 420#define DCFG_PERFRINT(_x) ((_x) << 11) 421#define DCFG_DEVADDR_MASK (0x7f << 4) 422#define DCFG_DEVADDR_SHIFT 4 423#define DCFG_DEVADDR_LIMIT 0x7f 424#define DCFG_DEVADDR(_x) ((_x) << 4) 425#define DCFG_NZ_STS_OUT_HSHK (1 << 2) 426#define DCFG_DEVSPD_MASK (0x3 << 0) 427#define DCFG_DEVSPD_SHIFT 0 428#define DCFG_DEVSPD_HS 0 429#define DCFG_DEVSPD_FS 1 430#define DCFG_DEVSPD_LS 2 431#define DCFG_DEVSPD_FS48 3 432 433#define DCTL HSOTG_REG(0x804) 434#define DCTL_PWRONPRGDONE (1 << 11) 435#define DCTL_CGOUTNAK (1 << 10) 436#define DCTL_SGOUTNAK (1 << 9) 437#define DCTL_CGNPINNAK (1 << 8) 438#define DCTL_SGNPINNAK (1 << 7) 439#define DCTL_TSTCTL_MASK (0x7 << 4) 440#define DCTL_TSTCTL_SHIFT 4 441#define DCTL_GOUTNAKSTS (1 << 3) 442#define DCTL_GNPINNAKSTS (1 << 2) 443#define DCTL_SFTDISCON (1 << 1) 444#define DCTL_RMTWKUPSIG (1 << 0) 445 446#define DSTS HSOTG_REG(0x808) 447#define DSTS_SOFFN_MASK (0x3fff << 8) 448#define DSTS_SOFFN_SHIFT 8 449#define DSTS_SOFFN_LIMIT 0x3fff 450#define DSTS_SOFFN(_x) ((_x) << 8) 451#define DSTS_ERRATICERR (1 << 3) 452#define DSTS_ENUMSPD_MASK (0x3 << 1) 453#define DSTS_ENUMSPD_SHIFT 1 454#define DSTS_ENUMSPD_HS 0 455#define DSTS_ENUMSPD_FS 1 456#define DSTS_ENUMSPD_LS 2 457#define DSTS_ENUMSPD_FS48 3 458#define DSTS_SUSPSTS (1 << 0) 459 460#define DIEPMSK HSOTG_REG(0x810) 461#define DIEPMSK_TXFIFOEMPTY (1 << 7) 462#define DIEPMSK_INEPNAKEFFMSK (1 << 6) 463#define DIEPMSK_INTKNEPMISMSK (1 << 5) 464#define DIEPMSK_INTKNTXFEMPMSK (1 << 4) 465#define DIEPMSK_TIMEOUTMSK (1 << 3) 466#define DIEPMSK_AHBERRMSK (1 << 2) 467#define DIEPMSK_EPDISBLDMSK (1 << 1) 468#define DIEPMSK_XFERCOMPLMSK (1 << 0) 469 470#define DOEPMSK HSOTG_REG(0x814) 471#define DOEPMSK_BACK2BACKSETUP (1 << 6) 472#define DOEPMSK_OUTTKNEPDISMSK (1 << 4) 473#define DOEPMSK_SETUPMSK (1 << 3) 474#define DOEPMSK_AHBERRMSK (1 << 2) 475#define DOEPMSK_EPDISBLDMSK (1 << 1) 476#define DOEPMSK_XFERCOMPLMSK (1 << 0) 477 478#define DAINT HSOTG_REG(0x818) 479#define DAINTMSK HSOTG_REG(0x81C) 480#define DAINT_OUTEP_SHIFT 16 481#define DAINT_OUTEP(_x) (1 << ((_x) + 16)) 482#define DAINT_INEP(_x) (1 << (_x)) 483 484#define DTKNQR1 HSOTG_REG(0x820) 485#define DTKNQR2 HSOTG_REG(0x824) 486#define DTKNQR3 HSOTG_REG(0x830) 487#define DTKNQR4 HSOTG_REG(0x834) 488 489#define DVBUSDIS HSOTG_REG(0x828) 490#define DVBUSPULSE HSOTG_REG(0x82C) 491 492#define DIEPCTL0 HSOTG_REG(0x900) 493#define DIEPCTL(_a) HSOTG_REG(0x900 + ((_a) * 0x20)) 494 495#define DOEPCTL0 HSOTG_REG(0xB00) 496#define DOEPCTL(_a) HSOTG_REG(0xB00 + ((_a) * 0x20)) 497 498/* EP0 specialness: 499 * bits[29..28] - reserved (no SetD0PID, SetD1PID) 500 * bits[25..22] - should always be zero, this isn't a periodic endpoint 501 * bits[10..0] - MPS setting different for EP0 502 */ 503#define D0EPCTL_MPS_MASK (0x3 << 0) 504#define D0EPCTL_MPS_SHIFT 0 505#define D0EPCTL_MPS_64 0 506#define D0EPCTL_MPS_32 1 507#define D0EPCTL_MPS_16 2 508#define D0EPCTL_MPS_8 3 509 510#define DXEPCTL_EPENA (1 << 31) 511#define DXEPCTL_EPDIS (1 << 30) 512#define DXEPCTL_SETD1PID (1 << 29) 513#define DXEPCTL_SETODDFR (1 << 29) 514#define DXEPCTL_SETD0PID (1 << 28) 515#define DXEPCTL_SETEVENFR (1 << 28) 516#define DXEPCTL_SNAK (1 << 27) 517#define DXEPCTL_CNAK (1 << 26) 518#define DXEPCTL_TXFNUM_MASK (0xf << 22) 519#define DXEPCTL_TXFNUM_SHIFT 22 520#define DXEPCTL_TXFNUM_LIMIT 0xf 521#define DXEPCTL_TXFNUM(_x) ((_x) << 22) 522#define DXEPCTL_STALL (1 << 21) 523#define DXEPCTL_SNP (1 << 20) 524#define DXEPCTL_EPTYPE_MASK (0x3 << 18) 525#define DXEPCTL_EPTYPE_CONTROL (0x0 << 18) 526#define DXEPCTL_EPTYPE_ISO (0x1 << 18) 527#define DXEPCTL_EPTYPE_BULK (0x2 << 18) 528#define DXEPCTL_EPTYPE_INTERRUPT (0x3 << 18) 529 530#define DXEPCTL_NAKSTS (1 << 17) 531#define DXEPCTL_DPID (1 << 16) 532#define DXEPCTL_EOFRNUM (1 << 16) 533#define DXEPCTL_USBACTEP (1 << 15) 534#define DXEPCTL_NEXTEP_MASK (0xf << 11) 535#define DXEPCTL_NEXTEP_SHIFT 11 536#define DXEPCTL_NEXTEP_LIMIT 0xf 537#define DXEPCTL_NEXTEP(_x) ((_x) << 11) 538#define DXEPCTL_MPS_MASK (0x7ff << 0) 539#define DXEPCTL_MPS_SHIFT 0 540#define DXEPCTL_MPS_LIMIT 0x7ff 541#define DXEPCTL_MPS(_x) ((_x) << 0) 542 543#define DIEPINT(_a) HSOTG_REG(0x908 + ((_a) * 0x20)) 544#define DOEPINT(_a) HSOTG_REG(0xB08 + ((_a) * 0x20)) 545#define DXEPINT_SETUP_RCVD (1 << 15) 546#define DXEPINT_INEPNAKEFF (1 << 6) 547#define DXEPINT_BACK2BACKSETUP (1 << 6) 548#define DXEPINT_INTKNEPMIS (1 << 5) 549#define DXEPINT_INTKNTXFEMP (1 << 4) 550#define DXEPINT_OUTTKNEPDIS (1 << 4) 551#define DXEPINT_TIMEOUT (1 << 3) 552#define DXEPINT_SETUP (1 << 3) 553#define DXEPINT_AHBERR (1 << 2) 554#define DXEPINT_EPDISBLD (1 << 1) 555#define DXEPINT_XFERCOMPL (1 << 0) 556 557#define DIEPTSIZ0 HSOTG_REG(0x910) 558#define DIEPTSIZ0_PKTCNT_MASK (0x3 << 19) 559#define DIEPTSIZ0_PKTCNT_SHIFT 19 560#define DIEPTSIZ0_PKTCNT_LIMIT 0x3 561#define DIEPTSIZ0_PKTCNT(_x) ((_x) << 19) 562#define DIEPTSIZ0_XFERSIZE_MASK (0x7f << 0) 563#define DIEPTSIZ0_XFERSIZE_SHIFT 0 564#define DIEPTSIZ0_XFERSIZE_LIMIT 0x7f 565#define DIEPTSIZ0_XFERSIZE(_x) ((_x) << 0) 566 567#define DOEPTSIZ0 HSOTG_REG(0xB10) 568#define DOEPTSIZ0_SUPCNT_MASK (0x3 << 29) 569#define DOEPTSIZ0_SUPCNT_SHIFT 29 570#define DOEPTSIZ0_SUPCNT_LIMIT 0x3 571#define DOEPTSIZ0_SUPCNT(_x) ((_x) << 29) 572#define DOEPTSIZ0_PKTCNT (1 << 19) 573#define DOEPTSIZ0_XFERSIZE_MASK (0x7f << 0) 574#define DOEPTSIZ0_XFERSIZE_SHIFT 0 575 576#define DIEPTSIZ(_a) HSOTG_REG(0x910 + ((_a) * 0x20)) 577#define DOEPTSIZ(_a) HSOTG_REG(0xB10 + ((_a) * 0x20)) 578#define DXEPTSIZ_MC_MASK (0x3 << 29) 579#define DXEPTSIZ_MC_SHIFT 29 580#define DXEPTSIZ_MC_LIMIT 0x3 581#define DXEPTSIZ_MC(_x) ((_x) << 29) 582#define DXEPTSIZ_PKTCNT_MASK (0x3ff << 19) 583#define DXEPTSIZ_PKTCNT_SHIFT 19 584#define DXEPTSIZ_PKTCNT_LIMIT 0x3ff 585#define DXEPTSIZ_PKTCNT_GET(_v) (((_v) >> 19) & 0x3ff) 586#define DXEPTSIZ_PKTCNT(_x) ((_x) << 19) 587#define DXEPTSIZ_XFERSIZE_MASK (0x7ffff << 0) 588#define DXEPTSIZ_XFERSIZE_SHIFT 0 589#define DXEPTSIZ_XFERSIZE_LIMIT 0x7ffff 590#define DXEPTSIZ_XFERSIZE_GET(_v) (((_v) >> 0) & 0x7ffff) 591#define DXEPTSIZ_XFERSIZE(_x) ((_x) << 0) 592 593#define DIEPDMA(_a) HSOTG_REG(0x914 + ((_a) * 0x20)) 594#define DOEPDMA(_a) HSOTG_REG(0xB14 + ((_a) * 0x20)) 595 596#define DTXFSTS(_a) HSOTG_REG(0x918 + ((_a) * 0x20)) 597 598#define PCGCTL HSOTG_REG(0x0e00) 599#define PCGCTL_IF_DEV_MODE (1 << 31) 600#define PCGCTL_P2HD_PRT_SPD_MASK (0x3 << 29) 601#define PCGCTL_P2HD_PRT_SPD_SHIFT 29 602#define PCGCTL_P2HD_DEV_ENUM_SPD_MASK (0x3 << 27) 603#define PCGCTL_P2HD_DEV_ENUM_SPD_SHIFT 27 604#define PCGCTL_MAC_DEV_ADDR_MASK (0x7f << 20) 605#define PCGCTL_MAC_DEV_ADDR_SHIFT 20 606#define PCGCTL_MAX_TERMSEL (1 << 19) 607#define PCGCTL_MAX_XCVRSELECT_MASK (0x3 << 17) 608#define PCGCTL_MAX_XCVRSELECT_SHIFT 17 609#define PCGCTL_PORT_POWER (1 << 16) 610#define PCGCTL_PRT_CLK_SEL_MASK (0x3 << 14) 611#define PCGCTL_PRT_CLK_SEL_SHIFT 14 612#define PCGCTL_ESS_REG_RESTORED (1 << 13) 613#define PCGCTL_EXTND_HIBER_SWITCH (1 << 12) 614#define PCGCTL_EXTND_HIBER_PWRCLMP (1 << 11) 615#define PCGCTL_ENBL_EXTND_HIBER (1 << 10) 616#define PCGCTL_RESTOREMODE (1 << 9) 617#define PCGCTL_RESETAFTSUSP (1 << 8) 618#define PCGCTL_DEEP_SLEEP (1 << 7) 619#define PCGCTL_PHY_IN_SLEEP (1 << 6) 620#define PCGCTL_ENBL_SLEEP_GATING (1 << 5) 621#define PCGCTL_RSTPDWNMODULE (1 << 3) 622#define PCGCTL_PWRCLMP (1 << 2) 623#define PCGCTL_GATEHCLK (1 << 1) 624#define PCGCTL_STOPPCLK (1 << 0) 625 626#define EPFIFO(_a) HSOTG_REG(0x1000 + ((_a) * 0x1000)) 627 628/* Host Mode Registers */ 629 630#define HCFG HSOTG_REG(0x0400) 631#define HCFG_MODECHTIMEN (1 << 31) 632#define HCFG_PERSCHEDENA (1 << 26) 633#define HCFG_FRLISTEN_MASK (0x3 << 24) 634#define HCFG_FRLISTEN_SHIFT 24 635#define HCFG_FRLISTEN_8 (0 << 24) 636#define FRLISTEN_8_SIZE 8 637#define HCFG_FRLISTEN_16 (1 << 24) 638#define FRLISTEN_16_SIZE 16 639#define HCFG_FRLISTEN_32 (2 << 24) 640#define FRLISTEN_32_SIZE 32 641#define HCFG_FRLISTEN_64 (3 << 24) 642#define FRLISTEN_64_SIZE 64 643#define HCFG_DESCDMA (1 << 23) 644#define HCFG_RESVALID_MASK (0xff << 8) 645#define HCFG_RESVALID_SHIFT 8 646#define HCFG_ENA32KHZ (1 << 7) 647#define HCFG_FSLSSUPP (1 << 2) 648#define HCFG_FSLSPCLKSEL_MASK (0x3 << 0) 649#define HCFG_FSLSPCLKSEL_SHIFT 0 650#define HCFG_FSLSPCLKSEL_30_60_MHZ 0 651#define HCFG_FSLSPCLKSEL_48_MHZ 1 652#define HCFG_FSLSPCLKSEL_6_MHZ 2 653 654#define HFIR HSOTG_REG(0x0404) 655#define HFIR_FRINT_MASK (0xffff << 0) 656#define HFIR_FRINT_SHIFT 0 657#define HFIR_RLDCTRL (1 << 16) 658 659#define HFNUM HSOTG_REG(0x0408) 660#define HFNUM_FRREM_MASK (0xffff << 16) 661#define HFNUM_FRREM_SHIFT 16 662#define HFNUM_FRNUM_MASK (0xffff << 0) 663#define HFNUM_FRNUM_SHIFT 0 664#define HFNUM_MAX_FRNUM 0x3fff 665 666#define HPTXSTS HSOTG_REG(0x0410) 667#define TXSTS_QTOP_ODD (1 << 31) 668#define TXSTS_QTOP_CHNEP_MASK (0xf << 27) 669#define TXSTS_QTOP_CHNEP_SHIFT 27 670#define TXSTS_QTOP_TOKEN_MASK (0x3 << 25) 671#define TXSTS_QTOP_TOKEN_SHIFT 25 672#define TXSTS_QTOP_TERMINATE (1 << 24) 673#define TXSTS_QSPCAVAIL_MASK (0xff << 16) 674#define TXSTS_QSPCAVAIL_SHIFT 16 675#define TXSTS_FSPCAVAIL_MASK (0xffff << 0) 676#define TXSTS_FSPCAVAIL_SHIFT 0 677 678#define HAINT HSOTG_REG(0x0414) 679#define HAINTMSK HSOTG_REG(0x0418) 680#define HFLBADDR HSOTG_REG(0x041c) 681 682#define HPRT0 HSOTG_REG(0x0440) 683#define HPRT0_SPD_MASK (0x3 << 17) 684#define HPRT0_SPD_SHIFT 17 685#define HPRT0_SPD_HIGH_SPEED 0 686#define HPRT0_SPD_FULL_SPEED 1 687#define HPRT0_SPD_LOW_SPEED 2 688#define HPRT0_TSTCTL_MASK (0xf << 13) 689#define HPRT0_TSTCTL_SHIFT 13 690#define HPRT0_PWR (1 << 12) 691#define HPRT0_LNSTS_MASK (0x3 << 10) 692#define HPRT0_LNSTS_SHIFT 10 693#define HPRT0_RST (1 << 8) 694#define HPRT0_SUSP (1 << 7) 695#define HPRT0_RES (1 << 6) 696#define HPRT0_OVRCURRCHG (1 << 5) 697#define HPRT0_OVRCURRACT (1 << 4) 698#define HPRT0_ENACHG (1 << 3) 699#define HPRT0_ENA (1 << 2) 700#define HPRT0_CONNDET (1 << 1) 701#define HPRT0_CONNSTS (1 << 0) 702 703#define HCCHAR(_ch) HSOTG_REG(0x0500 + 0x20 * (_ch)) 704#define HCCHAR_CHENA (1 << 31) 705#define HCCHAR_CHDIS (1 << 30) 706#define HCCHAR_ODDFRM (1 << 29) 707#define HCCHAR_DEVADDR_MASK (0x7f << 22) 708#define HCCHAR_DEVADDR_SHIFT 22 709#define HCCHAR_MULTICNT_MASK (0x3 << 20) 710#define HCCHAR_MULTICNT_SHIFT 20 711#define HCCHAR_EPTYPE_MASK (0x3 << 18) 712#define HCCHAR_EPTYPE_SHIFT 18 713#define HCCHAR_LSPDDEV (1 << 17) 714#define HCCHAR_EPDIR (1 << 15) 715#define HCCHAR_EPNUM_MASK (0xf << 11) 716#define HCCHAR_EPNUM_SHIFT 11 717#define HCCHAR_MPS_MASK (0x7ff << 0) 718#define HCCHAR_MPS_SHIFT 0 719 720#define HCSPLT(_ch) HSOTG_REG(0x0504 + 0x20 * (_ch)) 721#define HCSPLT_SPLTENA (1 << 31) 722#define HCSPLT_COMPSPLT (1 << 16) 723#define HCSPLT_XACTPOS_MASK (0x3 << 14) 724#define HCSPLT_XACTPOS_SHIFT 14 725#define HCSPLT_XACTPOS_MID 0 726#define HCSPLT_XACTPOS_END 1 727#define HCSPLT_XACTPOS_BEGIN 2 728#define HCSPLT_XACTPOS_ALL 3 729#define HCSPLT_HUBADDR_MASK (0x7f << 7) 730#define HCSPLT_HUBADDR_SHIFT 7 731#define HCSPLT_PRTADDR_MASK (0x7f << 0) 732#define HCSPLT_PRTADDR_SHIFT 0 733 734#define HCINT(_ch) HSOTG_REG(0x0508 + 0x20 * (_ch)) 735#define HCINTMSK(_ch) HSOTG_REG(0x050c + 0x20 * (_ch)) 736#define HCINTMSK_RESERVED14_31 (0x3ffff << 14) 737#define HCINTMSK_FRM_LIST_ROLL (1 << 13) 738#define HCINTMSK_XCS_XACT (1 << 12) 739#define HCINTMSK_BNA (1 << 11) 740#define HCINTMSK_DATATGLERR (1 << 10) 741#define HCINTMSK_FRMOVRUN (1 << 9) 742#define HCINTMSK_BBLERR (1 << 8) 743#define HCINTMSK_XACTERR (1 << 7) 744#define HCINTMSK_NYET (1 << 6) 745#define HCINTMSK_ACK (1 << 5) 746#define HCINTMSK_NAK (1 << 4) 747#define HCINTMSK_STALL (1 << 3) 748#define HCINTMSK_AHBERR (1 << 2) 749#define HCINTMSK_CHHLTD (1 << 1) 750#define HCINTMSK_XFERCOMPL (1 << 0) 751 752#define HCTSIZ(_ch) HSOTG_REG(0x0510 + 0x20 * (_ch)) 753#define TSIZ_DOPNG (1 << 31) 754#define TSIZ_SC_MC_PID_MASK (0x3 << 29) 755#define TSIZ_SC_MC_PID_SHIFT 29 756#define TSIZ_SC_MC_PID_DATA0 0 757#define TSIZ_SC_MC_PID_DATA2 1 758#define TSIZ_SC_MC_PID_DATA1 2 759#define TSIZ_SC_MC_PID_MDATA 3 760#define TSIZ_SC_MC_PID_SETUP 3 761#define TSIZ_PKTCNT_MASK (0x3ff << 19) 762#define TSIZ_PKTCNT_SHIFT 19 763#define TSIZ_NTD_MASK (0xff << 8) 764#define TSIZ_NTD_SHIFT 8 765#define TSIZ_SCHINFO_MASK (0xff << 0) 766#define TSIZ_SCHINFO_SHIFT 0 767#define TSIZ_XFERSIZE_MASK (0x7ffff << 0) 768#define TSIZ_XFERSIZE_SHIFT 0 769 770#define HCDMA(_ch) HSOTG_REG(0x0514 + 0x20 * (_ch)) 771#define HCDMA_DMA_ADDR_MASK (0x1fffff << 11) 772#define HCDMA_DMA_ADDR_SHIFT 11 773#define HCDMA_CTD_MASK (0xff << 3) 774#define HCDMA_CTD_SHIFT 3 775 776#define HCDMAB(_ch) HSOTG_REG(0x051c + 0x20 * (_ch)) 777 778#define HCFIFO(_ch) HSOTG_REG(0x1000 + 0x1000 * (_ch)) 779 780/** 781 * struct dwc2_hcd_dma_desc - Host-mode DMA descriptor structure 782 * 783 * @status: DMA descriptor status quadlet 784 * @buf: DMA descriptor data buffer pointer 785 * 786 * DMA Descriptor structure contains two quadlets: 787 * Status quadlet and Data buffer pointer. 788 */ 789struct dwc2_hcd_dma_desc { 790 u32 status; 791 u32 buf; 792}; 793 794#define HOST_DMA_A (1 << 31) 795#define HOST_DMA_STS_MASK (0x3 << 28) 796#define HOST_DMA_STS_SHIFT 28 797#define HOST_DMA_STS_PKTERR (1 << 28) 798#define HOST_DMA_EOL (1 << 26) 799#define HOST_DMA_IOC (1 << 25) 800#define HOST_DMA_SUP (1 << 24) 801#define HOST_DMA_ALT_QTD (1 << 23) 802#define HOST_DMA_QTD_OFFSET_MASK (0x3f << 17) 803#define HOST_DMA_QTD_OFFSET_SHIFT 17 804#define HOST_DMA_ISOC_NBYTES_MASK (0xfff << 0) 805#define HOST_DMA_ISOC_NBYTES_SHIFT 0 806#define HOST_DMA_NBYTES_MASK (0x1ffff << 0) 807#define HOST_DMA_NBYTES_SHIFT 0 808 809#define MAX_DMA_DESC_SIZE 131071 810#define MAX_DMA_DESC_NUM_GENERIC 64 811#define MAX_DMA_DESC_NUM_HS_ISOC 256 812 813#endif /* __DWC2_HW_H__ */ 814