Searched refs:DCSR (Results 1 – 13 of 13) sorted by relevance
2 Debug Control and Status Register (DCSR) Binding16 defined DCSR Memory Map. Child nodes will describe the individual25 The DCSR space exists in the memory-mapped bus.44 range of the DCSR space.57 This node represents the region of DCSR space allocated to the EPU98 offset and length of the DCSR space registers of the device114 This node represents the region of DCSR space allocated to the NPC127 offset and length of the DCSR space registers of the device129 The Nexus Port controller occupies two regions in the DCSR space151 This node represents the region of DCSR space allocated to the NXC[all …]
132 while (!(DCSR(channel) & DCSR_STOPSTATE) && --limit) in wait_dma_channel_stop()142 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL; in pxa2xx_spi_dma_error_stop()143 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL; in pxa2xx_spi_dma_error_stop()171 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL; in pxa2xx_spi_dma_transfer_complete()172 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL; in pxa2xx_spi_dma_transfer_complete()211 u32 irq_status = DCSR(channel) & DMA_INT_MASK; in pxa2xx_spi_dma_handler()252 && (DCSR(drv_data->tx_channel) & DCSR_RUN)) { in pxa2xx_spi_dma_transfer()291 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL; in pxa2xx_spi_dma_prepare()308 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL; in pxa2xx_spi_dma_prepare()333 DCSR(drv_data->rx_channel) |= DCSR_RUN; in pxa2xx_spi_dma_start()[all …]
128 DCSR(prtd->dma_ch) = DCSR_RUN; in pxa2xx_pcm_trigger()134 DCSR(prtd->dma_ch) &= ~DCSR_RUN; in pxa2xx_pcm_trigger()138 DCSR(prtd->dma_ch) |= DCSR_RUN; in pxa2xx_pcm_trigger()142 DCSR(prtd->dma_ch) |= DCSR_RUN; in pxa2xx_pcm_trigger()180 DCSR(prtd->dma_ch) &= ~DCSR_RUN; in __pxa2xx_pcm_prepare()181 DCSR(prtd->dma_ch) = 0; in __pxa2xx_pcm_prepare()195 dcsr = DCSR(dma_ch); in pxa2xx_pcm_dma_irq()196 DCSR(dma_ch) = dcsr & ~DCSR_STOPIRQEN; in pxa2xx_pcm_dma_irq()
116 DCSR(pd->dma_channel) = 0; in pxa_qc_prep()148 DCSR(pd->dma_channel) = DCSR_RUN; in pxa_bmdma_start()158 if ((DCSR(pd->dma_channel) & DCSR_RUN) && in pxa_bmdma_stop()162 DCSR(pd->dma_channel) = 0; in pxa_bmdma_stop()224 pd->dma_dcsr = DCSR(dma); in pxa_ata_dma_irq()225 DCSR(dma) = pd->dma_dcsr; in pxa_ata_dma_irq()358 DCSR(data->dma_channel) = 0; in pxa_ata_probe()
156 DCSR(si->rxdma) = DCSR_NODESC; in pxa_irda_fir_dma_rx_start()160 DCSR(si->rxdma) |= DCSR_RUN; in pxa_irda_fir_dma_rx_start()165 DCSR(si->txdma) = DCSR_NODESC; in pxa_irda_fir_dma_tx_start()169 DCSR(si->txdma) |= DCSR_RUN; in pxa_irda_fir_dma_tx_start()208 DCSR(si->rxdma) &= ~DCSR_RUN; in pxa_irda_set_speed()350 int dcsr = DCSR(channel); in pxa_irda_fir_dma_rx_irq()352 DCSR(channel) = dcsr & ~DCSR_RUN; in pxa_irda_fir_dma_rx_irq()364 dcsr = DCSR(channel); in pxa_irda_fir_dma_tx_irq()365 DCSR(channel) = dcsr & ~DCSR_RUN; in pxa_irda_fir_dma_tx_irq()475 DCSR(si->rxdma) &= ~DCSR_RUN; in pxa_irda_fir_irq()[all …]
138 dcsr = DCSR(chan); in dbg_show_chan_state()301 DCSR(i) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR; in pxa_request_dma()327 DCSR(dma_ch) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR; in pxa_free_dma()350 DCSR(i) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR; in dma_irq_handler()370 DCSR(i) = 0; in pxa_init_dma()
296 DCSR(dma) = DCSR_NODESC; in smc_pxa_dma_insl()301 DCSR(dma) = DCSR_NODESC | DCSR_RUN; in smc_pxa_dma_insl()302 while (!(DCSR(dma) & DCSR_STOPSTATE)) in smc_pxa_dma_insl()304 DCSR(dma) = 0; in smc_pxa_dma_insl()335 DCSR(dma) = DCSR_NODESC; in smc_pxa_dma_insw()340 DCSR(dma) = DCSR_NODESC | DCSR_RUN; in smc_pxa_dma_insw()341 while (!(DCSR(dma) & DCSR_STOPSTATE)) in smc_pxa_dma_insw()343 DCSR(dma) = 0; in smc_pxa_dma_insw()351 DCSR(dma) = 0; in smc_pxa_dma_irq()
228 if (DCSR(dma) & DCSR_BUSERR) { \231 DCSR(dma) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR; \261 DCSR(dma) = DCSR_NODESC; in smc_pxa_dma_insl()266 DCSR(dma) = DCSR_NODESC | DCSR_RUN; in smc_pxa_dma_insl()289 DCSR(dma) = DCSR_NODESC; in smc_pxa_dma_outsl()294 DCSR(dma) = DCSR_NODESC | DCSR_RUN; in smc_pxa_dma_outsl()
6 #define DCSR(n) DMAC_REG((n) << 2) macro
254 DCSR(host->dma) = DCSR_RUN; in pxamci_setup_data()346 DCSR(host->dma) = DCSR_RUN; in pxamci_cmd_done()361 DCSR(host->dma) = 0; in pxamci_data_done()558 int dcsr = DCSR(dma); in pxamci_dma_irq()559 DCSR(dma) = dcsr & ~DCSR_STOPIRQEN; in pxamci_dma_irq()
559 DCSR(pcdev->dma_chans[i]) = DCSR_RUN; in pxa_dma_start_channels()570 DCSR(pcdev->dma_chans[i]) = 0; in pxa_dma_stop_channels()743 status = DCSR(channel); in pxa_camera_dma_irq()744 DCSR(channel) = status; in pxa_camera_dma_irq()996 DCSR(pcdev->dma_chans[0]) = 0; in pxa_camera_clock_stop()997 DCSR(pcdev->dma_chans[1]) = 0; in pxa_camera_clock_stop()998 DCSR(pcdev->dma_chans[2]) = 0; in pxa_camera_clock_stop()
28 #define DCSR 0x0000 macro168 reg = (phy->idx << 2) + DCSR; in enable_chan()179 reg = (phy->idx << 2) + DCSR; in disable_chan()187 u32 reg = (phy->idx << 2) + DCSR; in clear_chan_irq()
584 DCSR(info->data_dma_ch) |= DCSR_RUN; in start_data_dma()592 dcsr = DCSR(channel); in pxa3xx_nand_data_dma_irq()593 DCSR(channel) = dcsr; in pxa3xx_nand_data_dma_irq()