1/*
2 * Generic PXA PATA driver
3 *
4 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
5 *
6 *  This program is free software; you can redistribute it and/or modify
7 *  it under the terms of the GNU General Public License as published by
8 *  the Free Software Foundation; either version 2, or (at your option)
9 *  any later version.
10 *
11 *  This program is distributed in the hope that it will be useful,
12 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
13 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14 *  GNU General Public License for more details.
15 *
16 *  You should have received a copy of the GNU General Public License
17 *  along with this program; see the file COPYING.  If not, write to
18 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/blkdev.h>
24#include <linux/ata.h>
25#include <linux/libata.h>
26#include <linux/platform_device.h>
27#include <linux/gpio.h>
28#include <linux/slab.h>
29#include <linux/completion.h>
30
31#include <scsi/scsi_host.h>
32
33#include <mach/pxa2xx-regs.h>
34#include <linux/platform_data/ata-pxa.h>
35#include <mach/dma.h>
36
37#define DRV_NAME	"pata_pxa"
38#define DRV_VERSION	"0.1"
39
40struct pata_pxa_data {
41	uint32_t		dma_channel;
42	struct pxa_dma_desc	*dma_desc;
43	dma_addr_t		dma_desc_addr;
44	uint32_t		dma_desc_id;
45
46	/* DMA IO physical address */
47	uint32_t		dma_io_addr;
48	/* PXA DREQ<0:2> pin selector */
49	uint32_t		dma_dreq;
50	/* DMA DCSR register value */
51	uint32_t		dma_dcsr;
52
53	struct completion	dma_done;
54};
55
56/*
57 * Setup the DMA descriptors. The size is transfer capped at 4k per descriptor,
58 * if the transfer is longer, it is split into multiple chained descriptors.
59 */
60static void pxa_load_dmac(struct scatterlist *sg, struct ata_queued_cmd *qc)
61{
62	struct pata_pxa_data *pd = qc->ap->private_data;
63
64	uint32_t cpu_len, seg_len;
65	dma_addr_t cpu_addr;
66
67	cpu_addr = sg_dma_address(sg);
68	cpu_len = sg_dma_len(sg);
69
70	do {
71		seg_len = (cpu_len > 0x1000) ? 0x1000 : cpu_len;
72
73		pd->dma_desc[pd->dma_desc_id].ddadr = pd->dma_desc_addr +
74			((pd->dma_desc_id + 1) * sizeof(struct pxa_dma_desc));
75
76		pd->dma_desc[pd->dma_desc_id].dcmd = DCMD_BURST32 |
77					DCMD_WIDTH2 | (DCMD_LENGTH & seg_len);
78
79		if (qc->tf.flags & ATA_TFLAG_WRITE) {
80			pd->dma_desc[pd->dma_desc_id].dsadr = cpu_addr;
81			pd->dma_desc[pd->dma_desc_id].dtadr = pd->dma_io_addr;
82			pd->dma_desc[pd->dma_desc_id].dcmd |= DCMD_INCSRCADDR |
83						DCMD_FLOWTRG;
84		} else {
85			pd->dma_desc[pd->dma_desc_id].dsadr = pd->dma_io_addr;
86			pd->dma_desc[pd->dma_desc_id].dtadr = cpu_addr;
87			pd->dma_desc[pd->dma_desc_id].dcmd |= DCMD_INCTRGADDR |
88						DCMD_FLOWSRC;
89		}
90
91		cpu_len -= seg_len;
92		cpu_addr += seg_len;
93		pd->dma_desc_id++;
94
95	} while (cpu_len);
96
97	/* Should not happen */
98	if (seg_len & 0x1f)
99		DALGN |= (1 << pd->dma_dreq);
100}
101
102/*
103 * Prepare taskfile for submission.
104 */
105static void pxa_qc_prep(struct ata_queued_cmd *qc)
106{
107	struct pata_pxa_data *pd = qc->ap->private_data;
108	int si = 0;
109	struct scatterlist *sg;
110
111	if (!(qc->flags & ATA_QCFLAG_DMAMAP))
112		return;
113
114	pd->dma_desc_id = 0;
115
116	DCSR(pd->dma_channel) = 0;
117	DALGN &= ~(1 << pd->dma_dreq);
118
119	for_each_sg(qc->sg, sg, qc->n_elem, si)
120		pxa_load_dmac(sg, qc);
121
122	pd->dma_desc[pd->dma_desc_id - 1].ddadr = DDADR_STOP;
123
124	/* Fire IRQ only at the end of last block */
125	pd->dma_desc[pd->dma_desc_id - 1].dcmd |= DCMD_ENDIRQEN;
126
127	DDADR(pd->dma_channel) = pd->dma_desc_addr;
128	DRCMR(pd->dma_dreq) = DRCMR_MAPVLD | pd->dma_channel;
129
130}
131
132/*
133 * Configure the DMA controller, load the DMA descriptors, but don't start the
134 * DMA controller yet. Only issue the ATA command.
135 */
136static void pxa_bmdma_setup(struct ata_queued_cmd *qc)
137{
138	qc->ap->ops->sff_exec_command(qc->ap, &qc->tf);
139}
140
141/*
142 * Execute the DMA transfer.
143 */
144static void pxa_bmdma_start(struct ata_queued_cmd *qc)
145{
146	struct pata_pxa_data *pd = qc->ap->private_data;
147	init_completion(&pd->dma_done);
148	DCSR(pd->dma_channel) = DCSR_RUN;
149}
150
151/*
152 * Wait until the DMA transfer completes, then stop the DMA controller.
153 */
154static void pxa_bmdma_stop(struct ata_queued_cmd *qc)
155{
156	struct pata_pxa_data *pd = qc->ap->private_data;
157
158	if ((DCSR(pd->dma_channel) & DCSR_RUN) &&
159		wait_for_completion_timeout(&pd->dma_done, HZ))
160		dev_err(qc->ap->dev, "Timeout waiting for DMA completion!");
161
162	DCSR(pd->dma_channel) = 0;
163}
164
165/*
166 * Read DMA status. The bmdma_stop() will take care of properly finishing the
167 * DMA transfer so we always have DMA-complete interrupt here.
168 */
169static unsigned char pxa_bmdma_status(struct ata_port *ap)
170{
171	struct pata_pxa_data *pd = ap->private_data;
172	unsigned char ret = ATA_DMA_INTR;
173
174	if (pd->dma_dcsr & DCSR_BUSERR)
175		ret |= ATA_DMA_ERR;
176
177	return ret;
178}
179
180/*
181 * No IRQ register present so we do nothing.
182 */
183static void pxa_irq_clear(struct ata_port *ap)
184{
185}
186
187/*
188 * Check for ATAPI DMA. ATAPI DMA is unsupported by this driver. It's still
189 * unclear why ATAPI has DMA issues.
190 */
191static int pxa_check_atapi_dma(struct ata_queued_cmd *qc)
192{
193	return -EOPNOTSUPP;
194}
195
196static struct scsi_host_template pxa_ata_sht = {
197	ATA_BMDMA_SHT(DRV_NAME),
198};
199
200static struct ata_port_operations pxa_ata_port_ops = {
201	.inherits		= &ata_bmdma_port_ops,
202	.cable_detect		= ata_cable_40wire,
203
204	.bmdma_setup		= pxa_bmdma_setup,
205	.bmdma_start		= pxa_bmdma_start,
206	.bmdma_stop		= pxa_bmdma_stop,
207	.bmdma_status		= pxa_bmdma_status,
208
209	.check_atapi_dma	= pxa_check_atapi_dma,
210
211	.sff_irq_clear		= pxa_irq_clear,
212
213	.qc_prep		= pxa_qc_prep,
214};
215
216/*
217 * DMA interrupt handler.
218 */
219static void pxa_ata_dma_irq(int dma, void *port)
220{
221	struct ata_port *ap = port;
222	struct pata_pxa_data *pd = ap->private_data;
223
224	pd->dma_dcsr = DCSR(dma);
225	DCSR(dma) = pd->dma_dcsr;
226
227	if (pd->dma_dcsr & DCSR_STOPSTATE)
228		complete(&pd->dma_done);
229}
230
231static int pxa_ata_probe(struct platform_device *pdev)
232{
233	struct ata_host *host;
234	struct ata_port *ap;
235	struct pata_pxa_data *data;
236	struct resource *cmd_res;
237	struct resource *ctl_res;
238	struct resource *dma_res;
239	struct resource *irq_res;
240	struct pata_pxa_pdata *pdata = dev_get_platdata(&pdev->dev);
241	int ret = 0;
242
243	/*
244	 * Resource validation, three resources are needed:
245	 *  - CMD port base address
246	 *  - CTL port base address
247	 *  - DMA port base address
248	 *  - IRQ pin
249	 */
250	if (pdev->num_resources != 4) {
251		dev_err(&pdev->dev, "invalid number of resources\n");
252		return -EINVAL;
253	}
254
255	/*
256	 * CMD port base address
257	 */
258	cmd_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
259	if (unlikely(cmd_res == NULL))
260		return -EINVAL;
261
262	/*
263	 * CTL port base address
264	 */
265	ctl_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
266	if (unlikely(ctl_res == NULL))
267		return -EINVAL;
268
269	/*
270	 * DMA port base address
271	 */
272	dma_res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
273	if (unlikely(dma_res == NULL))
274		return -EINVAL;
275
276	/*
277	 * IRQ pin
278	 */
279	irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
280	if (unlikely(irq_res == NULL))
281		return -EINVAL;
282
283	/*
284	 * Allocate the host
285	 */
286	host = ata_host_alloc(&pdev->dev, 1);
287	if (!host)
288		return -ENOMEM;
289
290	ap		= host->ports[0];
291	ap->ops		= &pxa_ata_port_ops;
292	ap->pio_mask	= ATA_PIO4;
293	ap->mwdma_mask	= ATA_MWDMA2;
294
295	ap->ioaddr.cmd_addr	= devm_ioremap(&pdev->dev, cmd_res->start,
296						resource_size(cmd_res));
297	ap->ioaddr.ctl_addr	= devm_ioremap(&pdev->dev, ctl_res->start,
298						resource_size(ctl_res));
299	ap->ioaddr.bmdma_addr	= devm_ioremap(&pdev->dev, dma_res->start,
300						resource_size(dma_res));
301
302	/*
303	 * Adjust register offsets
304	 */
305	ap->ioaddr.altstatus_addr = ap->ioaddr.ctl_addr;
306	ap->ioaddr.data_addr	= ap->ioaddr.cmd_addr +
307					(ATA_REG_DATA << pdata->reg_shift);
308	ap->ioaddr.error_addr	= ap->ioaddr.cmd_addr +
309					(ATA_REG_ERR << pdata->reg_shift);
310	ap->ioaddr.feature_addr	= ap->ioaddr.cmd_addr +
311					(ATA_REG_FEATURE << pdata->reg_shift);
312	ap->ioaddr.nsect_addr	= ap->ioaddr.cmd_addr +
313					(ATA_REG_NSECT << pdata->reg_shift);
314	ap->ioaddr.lbal_addr	= ap->ioaddr.cmd_addr +
315					(ATA_REG_LBAL << pdata->reg_shift);
316	ap->ioaddr.lbam_addr	= ap->ioaddr.cmd_addr +
317					(ATA_REG_LBAM << pdata->reg_shift);
318	ap->ioaddr.lbah_addr	= ap->ioaddr.cmd_addr +
319					(ATA_REG_LBAH << pdata->reg_shift);
320	ap->ioaddr.device_addr	= ap->ioaddr.cmd_addr +
321					(ATA_REG_DEVICE << pdata->reg_shift);
322	ap->ioaddr.status_addr	= ap->ioaddr.cmd_addr +
323					(ATA_REG_STATUS << pdata->reg_shift);
324	ap->ioaddr.command_addr	= ap->ioaddr.cmd_addr +
325					(ATA_REG_CMD << pdata->reg_shift);
326
327	/*
328	 * Allocate and load driver's internal data structure
329	 */
330	data = devm_kzalloc(&pdev->dev, sizeof(struct pata_pxa_data),
331								GFP_KERNEL);
332	if (!data)
333		return -ENOMEM;
334
335	ap->private_data = data;
336	data->dma_dreq = pdata->dma_dreq;
337	data->dma_io_addr = dma_res->start;
338
339	/*
340	 * Allocate space for the DMA descriptors
341	 */
342	data->dma_desc = dmam_alloc_coherent(&pdev->dev, PAGE_SIZE,
343					&data->dma_desc_addr, GFP_KERNEL);
344	if (!data->dma_desc)
345		return -EINVAL;
346
347	/*
348	 * Request the DMA channel
349	 */
350	data->dma_channel = pxa_request_dma(DRV_NAME, DMA_PRIO_LOW,
351						pxa_ata_dma_irq, ap);
352	if (data->dma_channel < 0)
353		return -EBUSY;
354
355	/*
356	 * Stop and clear the DMA channel
357	 */
358	DCSR(data->dma_channel) = 0;
359
360	/*
361	 * Activate the ATA host
362	 */
363	ret = ata_host_activate(host, irq_res->start, ata_sff_interrupt,
364				pdata->irq_flags, &pxa_ata_sht);
365	if (ret)
366		pxa_free_dma(data->dma_channel);
367
368	return ret;
369}
370
371static int pxa_ata_remove(struct platform_device *pdev)
372{
373	struct ata_host *host = platform_get_drvdata(pdev);
374	struct pata_pxa_data *data = host->ports[0]->private_data;
375
376	pxa_free_dma(data->dma_channel);
377
378	ata_host_detach(host);
379
380	return 0;
381}
382
383static struct platform_driver pxa_ata_driver = {
384	.probe		= pxa_ata_probe,
385	.remove		= pxa_ata_remove,
386	.driver		= {
387		.name		= DRV_NAME,
388	},
389};
390
391module_platform_driver(pxa_ata_driver);
392
393MODULE_AUTHOR("Marek Vasut <marek.vasut@gmail.com>");
394MODULE_DESCRIPTION("DMA-capable driver for PATA on PXA CPU");
395MODULE_LICENSE("GPL");
396MODULE_VERSION(DRV_VERSION);
397MODULE_ALIAS("platform:" DRV_NAME);
398