Searched refs:Current (Results 1 - 200 of 936) sorted by relevance

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/linux-4.1.27/arch/mips/fw/arc/
H A D	tree.c	19 ArcGetPeer(pcomponent *Current) ArcGetPeer() argument 21 if (Current == PROM_NULL_COMPONENT) ArcGetPeer() 24 return (pcomponent *) ARC_CALL1(next_component, Current); ArcGetPeer() 28 ArcGetChild(pcomponent *Current) ArcGetChild() argument 30 return (pcomponent *) ARC_CALL1(child_component, Current); ArcGetChild() 34 ArcGetParent(pcomponent *Current) ArcGetParent() argument 36 if (Current == PROM_NULL_COMPONENT) ArcGetParent() 39 return (pcomponent *) ARC_CALL1(parent_component, Current); ArcGetParent() 43 ArcGetConfigurationData(VOID *Buffer, pcomponent *Current) ArcGetConfigurationData() argument 45 return ARC_CALL2(component_data, Buffer, Current); ArcGetConfigurationData() 49 ArcAddChild(pcomponent *Current, pcomponent *Template, VOID *ConfigurationData) ArcAddChild() argument 52 ARC_CALL3(child_add, Current, Template, ConfigurationData); ArcAddChild()
H A D	memory.c	35 struct linux_mdesc * __init ArcGetMemoryDescriptor(struct linux_mdesc *Current) ArcGetMemoryDescriptor() argument 37 return (struct linux_mdesc *) ARC_CALL1(get_mdesc, Current); ArcGetMemoryDescriptor()
/linux-4.1.27/drivers/rtc/
H A D	rtc-at91rm9200.h	36 #define AT91_RTC_SEC (0x7f << 0) /* Current Second */ 37 #define AT91_RTC_MIN (0x7f << 8) /* Current Minute */ 38 #define AT91_RTC_HOUR (0x3f << 16) /* Current Hour */ 42 #define AT91_RTC_CENT (0x7f << 0) /* Current Century */ 43 #define AT91_RTC_YEAR (0xff << 8) /* Current Year */ 44 #define AT91_RTC_MONTH (0x1f << 16) /* Current Month */ 45 #define AT91_RTC_DAY (7 << 21) /* Current Day */ 46 #define AT91_RTC_DATE (0x3f << 24) /* Current Date */
H A D	systohc.c	12 * @now: Current time of day
H A D	rtc-ds1347.c	3 * Driver for Dallas Semiconductor DS1347 Low Current, SPI Compatible
/linux-4.1.27/include/linux/iio/dac/
H A D	ad5421.h	5 * enum ad5421_current_range - Current range the AD5421 is configured for. 20 * @current_range: Current range the AD5421 is configured for
/linux-4.1.27/include/linux/
H A D	keyboard.h	13 int shift; /* Current shift mask */ 14 int ledstate; /* Current led state */
H A D	timekeeper_internal.h	15 * @clock: Current clocksource used for timekeeping. 45 * @xtime_sec: Current CLOCK_REALTIME time in seconds 46 * @ktime_sec: Current CLOCK_MONOTONIC time in seconds
H A D	mempool.h	17 int curr_nr; /* Current nr of elements at *elements */
H A D	backlight.h	68 /* Current User requested brightness (0 - max_brightness) */ 72 /* Current FB Power mode (0: full on, 1..3: power saving
H A D	console_struct.h	41 unsigned char vc_attr; /* Current attributes */ 57 struct console_font vc_font; /* Current VC font set */
H A D	nsproxy.h	43 * any pointer on the nsproxy itself. Current must hold the task_lock
H A D	flex_proportions.h	30 /* Current period */
H A D	kgdb.h	29 * @regs: Current &struct pt_regs. 181 * @flags: Current IRQ state 199 * @regs: Current &struct pt_regs.
H A D	led-lm3530.h	16 #define LM3530_FS_CURR_5mA (0) /* Full Scale Current */
/linux-4.1.27/arch/blackfin/mach-bf538/include/mach/
H A D	defBF539.h	64 #define MXVR_DMA0_CURR_ADDR 0xFFC027A4 /* MXVR Sync Data DMA0 Current Address Register */ 65 #define MXVR_DMA0_CURR_COUNT 0xFFC027A8 /* MXVR Sync Data DMA0 Current Loop Count Register */ 70 #define MXVR_DMA1_CURR_ADDR 0xFFC027B8 /* MXVR Sync Data DMA1 Current Address Register */ 71 #define MXVR_DMA1_CURR_COUNT 0xFFC027BC /* MXVR Sync Data DMA1 Current Loop Count Register */ 76 #define MXVR_DMA2_CURR_ADDR 0xFFC027CC /* MXVR Sync Data DMA2 Current Address Register */ 77 #define MXVR_DMA2_CURR_COUNT 0xFFC027D0 /* MXVR Sync Data DMA2 Current Loop Count Register */ 82 #define MXVR_DMA3_CURR_ADDR 0xFFC027E0 /* MXVR Sync Data DMA3 Current Address Register */ 83 #define MXVR_DMA3_CURR_COUNT 0xFFC027E4 /* MXVR Sync Data DMA3 Current Loop Count Register */ 88 #define MXVR_DMA4_CURR_ADDR 0xFFC027F4 /* MXVR Sync Data DMA4 Current Address Register */ 89 #define MXVR_DMA4_CURR_COUNT 0xFFC027F8 /* MXVR Sync Data DMA4 Current Loop Count Register */ 94 #define MXVR_DMA5_CURR_ADDR 0xFFC02808 /* MXVR Sync Data DMA5 Current Address Register */ 95 #define MXVR_DMA5_CURR_COUNT 0xFFC0280C /* MXVR Sync Data DMA5 Current Loop Count Register */ 100 #define MXVR_DMA6_CURR_ADDR 0xFFC0281C /* MXVR Sync Data DMA6 Current Address Register */ 101 #define MXVR_DMA6_CURR_COUNT 0xFFC02820 /* MXVR Sync Data DMA6 Current Loop Count Register */ 106 #define MXVR_DMA7_CURR_ADDR 0xFFC02830 /* MXVR Sync Data DMA7 Current Address Register */ 107 #define MXVR_DMA7_CURR_COUNT 0xFFC02834 /* MXVR Sync Data DMA7 Current Loop Count Register */ 111 #define MXVR_APRB_CURR_ADDR 0xFFC02840 /* MXVR Async Packet RX Buffer Current Addr Register */ 113 #define MXVR_APTB_CURR_ADDR 0xFFC02848 /* MXVR Async Packet TX Buffer Current Addr Register */ 117 #define MXVR_CMRB_CURR_ADDR 0xFFC02854 /* MXVR Control Message RX Buffer Current Address */ 119 #define MXVR_CMTB_CURR_ADDR 0xFFC0285C /* MXVR Control Message TX Buffer Current Address */ 122 #define MXVR_RRDB_CURR_ADDR 0xFFC02864 /* MXVR Remote Read Buffer Current Addr Register */
H A D	defBF538.h	137 #define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ 162 #define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ 192 #define DMAC0_TC_CNT 0xFFC00B10 /* DMA Controller 0 Traffic Control Current Counts Register */ 205 #define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ 206 #define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ 209 #define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ 210 #define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ 219 #define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ 220 #define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ 223 #define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ 224 #define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ 233 #define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ 234 #define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ 237 #define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ 238 #define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ 247 #define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ 248 #define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ 251 #define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ 252 #define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ 261 #define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ 262 #define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ 265 #define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ 266 #define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ 275 #define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ 276 #define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ 279 #define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ 280 #define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ 289 #define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ 290 #define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ 293 #define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ 294 #define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ 303 #define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ 304 #define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ 307 #define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ 308 #define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ 317 #define MDMA_D0_CURR_DESC_PTR 0xFFC00E20 /* MemDMA0 Stream 0 Destination Current Descriptor Pointer Register */ 318 #define MDMA_D0_CURR_ADDR 0xFFC00E24 /* MemDMA0 Stream 0 Destination Current Address Register */ 321 #define MDMA_D0_CURR_X_COUNT 0xFFC00E30 /* MemDMA0 Stream 0 Destination Current X Count Register */ 322 #define MDMA_D0_CURR_Y_COUNT 0xFFC00E38 /* MemDMA0 Stream 0 Destination Current Y Count Register */ 331 #define MDMA_S0_CURR_DESC_PTR 0xFFC00E60 /* MemDMA0 Stream 0 Source Current Descriptor Pointer Register */ 332 #define MDMA_S0_CURR_ADDR 0xFFC00E64 /* MemDMA0 Stream 0 Source Current Address Register */ 335 #define MDMA_S0_CURR_X_COUNT 0xFFC00E70 /* MemDMA0 Stream 0 Source Current X Count Register */ 336 #define MDMA_S0_CURR_Y_COUNT 0xFFC00E78 /* MemDMA0 Stream 0 Source Current Y Count Register */ 345 #define MDMA_D1_CURR_DESC_PTR 0xFFC00EA0 /* MemDMA0 Stream 1 Destination Current Descriptor Pointer Register */ 346 #define MDMA_D1_CURR_ADDR 0xFFC00EA4 /* MemDMA0 Stream 1 Destination Current Address Register */ 349 #define MDMA_D1_CURR_X_COUNT 0xFFC00EB0 /* MemDMA0 Stream 1 Destination Current X Count Register */ 350 #define MDMA_D1_CURR_Y_COUNT 0xFFC00EB8 /* MemDMA0 Stream 1 Destination Current Y Count Register */ 359 #define MDMA_S1_CURR_DESC_PTR 0xFFC00EE0 /* MemDMA0 Stream 1 Source Current Descriptor Pointer Register */ 360 #define MDMA_S1_CURR_ADDR 0xFFC00EE4 /* MemDMA0 Stream 1 Source Current Address Register */ 363 #define MDMA_S1_CURR_X_COUNT 0xFFC00EF0 /* MemDMA0 Stream 1 Source Current X Count Register */ 364 #define MDMA_S1_CURR_Y_COUNT 0xFFC00EF8 /* MemDMA0 Stream 1 Source Current Y Count Register */ 433 #define DMAC1_TC_CNT 0xFFC01B10 /* DMA Controller 1 Traffic Control Current Counts Register */ 445 #define DMA8_CURR_DESC_PTR 0xFFC01C20 /* DMA Channel 8 Current Descriptor Pointer Register */ 446 #define DMA8_CURR_ADDR 0xFFC01C24 /* DMA Channel 8 Current Address Register */ 449 #define DMA8_CURR_X_COUNT 0xFFC01C30 /* DMA Channel 8 Current X Count Register */ 450 #define DMA8_CURR_Y_COUNT 0xFFC01C38 /* DMA Channel 8 Current Y Count Register */ 459 #define DMA9_CURR_DESC_PTR 0xFFC01C60 /* DMA Channel 9 Current Descriptor Pointer Register */ 460 #define DMA9_CURR_ADDR 0xFFC01C64 /* DMA Channel 9 Current Address Register */ 463 #define DMA9_CURR_X_COUNT 0xFFC01C70 /* DMA Channel 9 Current X Count Register */ 464 #define DMA9_CURR_Y_COUNT 0xFFC01C78 /* DMA Channel 9 Current Y Count Register */ 473 #define DMA10_CURR_DESC_PTR 0xFFC01CA0 /* DMA Channel 10 Current Descriptor Pointer Register */ 474 #define DMA10_CURR_ADDR 0xFFC01CA4 /* DMA Channel 10 Current Address Register */ 477 #define DMA10_CURR_X_COUNT 0xFFC01CB0 /* DMA Channel 10 Current X Count Register */ 478 #define DMA10_CURR_Y_COUNT 0xFFC01CB8 /* DMA Channel 10 Current Y Count Register */ 487 #define DMA11_CURR_DESC_PTR 0xFFC01CE0 /* DMA Channel 11 Current Descriptor Pointer Register */ 488 #define DMA11_CURR_ADDR 0xFFC01CE4 /* DMA Channel 11 Current Address Register */ 491 #define DMA11_CURR_X_COUNT 0xFFC01CF0 /* DMA Channel 11 Current X Count Register */ 492 #define DMA11_CURR_Y_COUNT 0xFFC01CF8 /* DMA Channel 11 Current Y Count Register */ 501 #define DMA12_CURR_DESC_PTR 0xFFC01D20 /* DMA Channel 12 Current Descriptor Pointer Register */ 502 #define DMA12_CURR_ADDR 0xFFC01D24 /* DMA Channel 12 Current Address Register */ 505 #define DMA12_CURR_X_COUNT 0xFFC01D30 /* DMA Channel 12 Current X Count Register */ 506 #define DMA12_CURR_Y_COUNT 0xFFC01D38 /* DMA Channel 12 Current Y Count Register */ 515 #define DMA13_CURR_DESC_PTR 0xFFC01D60 /* DMA Channel 13 Current Descriptor Pointer Register */ 516 #define DMA13_CURR_ADDR 0xFFC01D64 /* DMA Channel 13 Current Address Register */ 519 #define DMA13_CURR_X_COUNT 0xFFC01D70 /* DMA Channel 13 Current X Count Register */ 520 #define DMA13_CURR_Y_COUNT 0xFFC01D78 /* DMA Channel 13 Current Y Count Register */ 529 #define DMA14_CURR_DESC_PTR 0xFFC01DA0 /* DMA Channel 14 Current Descriptor Pointer Register */ 530 #define DMA14_CURR_ADDR 0xFFC01DA4 /* DMA Channel 14 Current Address Register */ 533 #define DMA14_CURR_X_COUNT 0xFFC01DB0 /* DMA Channel 14 Current X Count Register */ 534 #define DMA14_CURR_Y_COUNT 0xFFC01DB8 /* DMA Channel 14 Current Y Count Register */ 543 #define DMA15_CURR_DESC_PTR 0xFFC01DE0 /* DMA Channel 15 Current Descriptor Pointer Register */ 544 #define DMA15_CURR_ADDR 0xFFC01DE4 /* DMA Channel 15 Current Address Register */ 547 #define DMA15_CURR_X_COUNT 0xFFC01DF0 /* DMA Channel 15 Current X Count Register */ 548 #define DMA15_CURR_Y_COUNT 0xFFC01DF8 /* DMA Channel 15 Current Y Count Register */ 557 #define DMA16_CURR_DESC_PTR 0xFFC01E20 /* DMA Channel 16 Current Descriptor Pointer Register */ 558 #define DMA16_CURR_ADDR 0xFFC01E24 /* DMA Channel 16 Current Address Register */ 561 #define DMA16_CURR_X_COUNT 0xFFC01E30 /* DMA Channel 16 Current X Count Register */ 562 #define DMA16_CURR_Y_COUNT 0xFFC01E38 /* DMA Channel 16 Current Y Count Register */ 571 #define DMA17_CURR_DESC_PTR 0xFFC01E60 /* DMA Channel 17 Current Descriptor Pointer Register */ 572 #define DMA17_CURR_ADDR 0xFFC01E64 /* DMA Channel 17 Current Address Register */ 575 #define DMA17_CURR_X_COUNT 0xFFC01E70 /* DMA Channel 17 Current X Count Register */ 576 #define DMA17_CURR_Y_COUNT 0xFFC01E78 /* DMA Channel 17 Current Y Count Register */ 585 #define DMA18_CURR_DESC_PTR 0xFFC01EA0 /* DMA Channel 18 Current Descriptor Pointer Register */ 586 #define DMA18_CURR_ADDR 0xFFC01EA4 /* DMA Channel 18 Current Address Register */ 589 #define DMA18_CURR_X_COUNT 0xFFC01EB0 /* DMA Channel 18 Current X Count Register */ 590 #define DMA18_CURR_Y_COUNT 0xFFC01EB8 /* DMA Channel 18 Current Y Count Register */ 599 #define DMA19_CURR_DESC_PTR 0xFFC01EE0 /* DMA Channel 19 Current Descriptor Pointer Register */ 600 #define DMA19_CURR_ADDR 0xFFC01EE4 /* DMA Channel 19 Current Address Register */ 603 #define DMA19_CURR_X_COUNT 0xFFC01EF0 /* DMA Channel 19 Current X Count Register */ 604 #define DMA19_CURR_Y_COUNT 0xFFC01EF8 /* DMA Channel 19 Current Y Count Register */ 613 #define MDMA_D2_CURR_DESC_PTR 0xFFC01F20 /* MemDMA1 Stream 0 Destination Current Descriptor Pointer Register */ 614 #define MDMA_D2_CURR_ADDR 0xFFC01F24 /* MemDMA1 Stream 0 Destination Current Address Register */ 617 #define MDMA_D2_CURR_X_COUNT 0xFFC01F30 /* MemDMA1 Stream 0 Destination Current X Count Register */ 618 #define MDMA_D2_CURR_Y_COUNT 0xFFC01F38 /* MemDMA1 Stream 0 Destination Current Y Count Register */ 627 #define MDMA_S2_CURR_DESC_PTR 0xFFC01F60 /* MemDMA1 Stream 0 Source Current Descriptor Pointer Register */ 628 #define MDMA_S2_CURR_ADDR 0xFFC01F64 /* MemDMA1 Stream 0 Source Current Address Register */ 631 #define MDMA_S2_CURR_X_COUNT 0xFFC01F70 /* MemDMA1 Stream 0 Source Current X Count Register */ 632 #define MDMA_S2_CURR_Y_COUNT 0xFFC01F78 /* MemDMA1 Stream 0 Source Current Y Count Register */ 641 #define MDMA_D3_CURR_DESC_PTR 0xFFC01FA0 /* MemDMA1 Stream 1 Destination Current Descriptor Pointer Register */ 642 #define MDMA_D3_CURR_ADDR 0xFFC01FA4 /* MemDMA1 Stream 1 Destination Current Address Register */ 645 #define MDMA_D3_CURR_X_COUNT 0xFFC01FB0 /* MemDMA1 Stream 1 Destination Current X Count Register */ 646 #define MDMA_D3_CURR_Y_COUNT 0xFFC01FB8 /* MemDMA1 Stream 1 Destination Current Y Count Register */ 655 #define MDMA_S3_CURR_DESC_PTR 0xFFC01FE0 /* MemDMA1 Stream 1 Source Current Descriptor Pointer Register */ 656 #define MDMA_S3_CURR_ADDR 0xFFC01FE4 /* MemDMA1 Stream 1 Source Current Address Register */ 659 #define MDMA_S3_CURR_X_COUNT 0xFFC01FF0 /* MemDMA1 Stream 1 Source Current X Count Register */ 660 #define MDMA_S3_CURR_Y_COUNT 0xFFC01FF8 /* MemDMA1 Stream 1 Source Current Y Count Register */ 749 #define SPORT2_CHNL 0xFFC02534 /* SPORT2 Current Channel Register */ 774 #define SPORT3_CHNL 0xFFC02634 /* SPORT3 Current Channel Register */
H A D	anomaly.h	50 /* Current DMA Address Shows Wrong Value During Carry Fix */ 82 /* Hibernate Leakage Current Is Higher Than Specified */ 112 /* Entering Hibernate State with Peripheral Wakeups Enabled Draws Excess Current */
/linux-4.1.27/scripts/dtc/
H A D	srcpos.h	79 #define YYLLOC_DEFAULT(Current, Rhs, N) \ 82 (Current).first_line = YYRHSLOC(Rhs, 1).first_line; \ 83 (Current).first_column = YYRHSLOC(Rhs, 1).first_column; \ 84 (Current).last_line = YYRHSLOC(Rhs, N).last_line; \ 85 (Current).last_column = YYRHSLOC (Rhs, N).last_column; \ 86 (Current).file = YYRHSLOC(Rhs, N).file; \ 88 (Current).first_line = (Current).last_line = \ 90 (Current).first_column = (Current).last_column = \ 92 (Current).file = YYRHSLOC (Rhs, 0).file; \
/linux-4.1.27/arch/blackfin/mach-bf548/include/mach/
H A D	defBF549.h	67 #define MXVR_DMA0_CURR_ADDR 0xffc027a4 /* MXVR Sync Data DMA0 Current Address */ 68 #define MXVR_DMA0_CURR_COUNT 0xffc027a8 /* MXVR Sync Data DMA0 Current Loop Count */ 75 #define MXVR_DMA1_CURR_ADDR 0xffc027b8 /* MXVR Sync Data DMA1 Current Address */ 76 #define MXVR_DMA1_CURR_COUNT 0xffc027bc /* MXVR Sync Data DMA1 Current Loop Count */ 83 #define MXVR_DMA2_CURR_ADDR 0xffc027cc /* MXVR Sync Data DMA2 Current Address */ 84 #define MXVR_DMA2_CURR_COUNT 0xffc027d0 /* MXVR Sync Data DMA2 Current Loop Count */ 91 #define MXVR_DMA3_CURR_ADDR 0xffc027e0 /* MXVR Sync Data DMA3 Current Address */ 92 #define MXVR_DMA3_CURR_COUNT 0xffc027e4 /* MXVR Sync Data DMA3 Current Loop Count */ 99 #define MXVR_DMA4_CURR_ADDR 0xffc027f4 /* MXVR Sync Data DMA4 Current Address */ 100 #define MXVR_DMA4_CURR_COUNT 0xffc027f8 /* MXVR Sync Data DMA4 Current Loop Count */ 107 #define MXVR_DMA5_CURR_ADDR 0xffc02808 /* MXVR Sync Data DMA5 Current Address */ 108 #define MXVR_DMA5_CURR_COUNT 0xffc0280c /* MXVR Sync Data DMA5 Current Loop Count */ 115 #define MXVR_DMA6_CURR_ADDR 0xffc0281c /* MXVR Sync Data DMA6 Current Address */ 116 #define MXVR_DMA6_CURR_COUNT 0xffc02820 /* MXVR Sync Data DMA6 Current Loop Count */ 123 #define MXVR_DMA7_CURR_ADDR 0xffc02830 /* MXVR Sync Data DMA7 Current Address */ 124 #define MXVR_DMA7_CURR_COUNT 0xffc02834 /* MXVR Sync Data DMA7 Current Loop Count */ 130 #define MXVR_APRB_CURR_ADDR 0xffc02840 /* MXVR Async Packet RX Buffer Current Addr Register */ 132 #define MXVR_APTB_CURR_ADDR 0xffc02848 /* MXVR Async Packet TX Buffer Current Addr Register */ 138 #define MXVR_CMRB_CURR_ADDR 0xffc02854 /* MXVR Control Message RX Buffer Current Address */ 140 #define MXVR_CMTB_CURR_ADDR 0xffc0285c /* MXVR Control Message TX Buffer Current Address */ 145 #define MXVR_RRDB_CURR_ADDR 0xffc02864 /* MXVR Remote Read Buffer Current Addr Register */
H A D	defBF54x_base.h	139 #define SPORT1_CHNL 0xffc00934 /* SPORT1 Current Channel Register */ 203 #define DMAC0_TC_CNT 0xffc00b10 /* DMA Controller 0 Current Counts Register */ 214 #define DMA0_CURR_DESC_PTR 0xffc00c20 /* DMA Channel 0 Current Descriptor Pointer Register */ 215 #define DMA0_CURR_ADDR 0xffc00c24 /* DMA Channel 0 Current Address Register */ 218 #define DMA0_CURR_X_COUNT 0xffc00c30 /* DMA Channel 0 Current X Count Register */ 219 #define DMA0_CURR_Y_COUNT 0xffc00c38 /* DMA Channel 0 Current Y Count Register */ 230 #define DMA1_CURR_DESC_PTR 0xffc00c60 /* DMA Channel 1 Current Descriptor Pointer Register */ 231 #define DMA1_CURR_ADDR 0xffc00c64 /* DMA Channel 1 Current Address Register */ 234 #define DMA1_CURR_X_COUNT 0xffc00c70 /* DMA Channel 1 Current X Count Register */ 235 #define DMA1_CURR_Y_COUNT 0xffc00c78 /* DMA Channel 1 Current Y Count Register */ 246 #define DMA2_CURR_DESC_PTR 0xffc00ca0 /* DMA Channel 2 Current Descriptor Pointer Register */ 247 #define DMA2_CURR_ADDR 0xffc00ca4 /* DMA Channel 2 Current Address Register */ 250 #define DMA2_CURR_X_COUNT 0xffc00cb0 /* DMA Channel 2 Current X Count Register */ 251 #define DMA2_CURR_Y_COUNT 0xffc00cb8 /* DMA Channel 2 Current Y Count Register */ 262 #define DMA3_CURR_DESC_PTR 0xffc00ce0 /* DMA Channel 3 Current Descriptor Pointer Register */ 263 #define DMA3_CURR_ADDR 0xffc00ce4 /* DMA Channel 3 Current Address Register */ 266 #define DMA3_CURR_X_COUNT 0xffc00cf0 /* DMA Channel 3 Current X Count Register */ 267 #define DMA3_CURR_Y_COUNT 0xffc00cf8 /* DMA Channel 3 Current Y Count Register */ 278 #define DMA4_CURR_DESC_PTR 0xffc00d20 /* DMA Channel 4 Current Descriptor Pointer Register */ 279 #define DMA4_CURR_ADDR 0xffc00d24 /* DMA Channel 4 Current Address Register */ 282 #define DMA4_CURR_X_COUNT 0xffc00d30 /* DMA Channel 4 Current X Count Register */ 283 #define DMA4_CURR_Y_COUNT 0xffc00d38 /* DMA Channel 4 Current Y Count Register */ 294 #define DMA5_CURR_DESC_PTR 0xffc00d60 /* DMA Channel 5 Current Descriptor Pointer Register */ 295 #define DMA5_CURR_ADDR 0xffc00d64 /* DMA Channel 5 Current Address Register */ 298 #define DMA5_CURR_X_COUNT 0xffc00d70 /* DMA Channel 5 Current X Count Register */ 299 #define DMA5_CURR_Y_COUNT 0xffc00d78 /* DMA Channel 5 Current Y Count Register */ 310 #define DMA6_CURR_DESC_PTR 0xffc00da0 /* DMA Channel 6 Current Descriptor Pointer Register */ 311 #define DMA6_CURR_ADDR 0xffc00da4 /* DMA Channel 6 Current Address Register */ 314 #define DMA6_CURR_X_COUNT 0xffc00db0 /* DMA Channel 6 Current X Count Register */ 315 #define DMA6_CURR_Y_COUNT 0xffc00db8 /* DMA Channel 6 Current Y Count Register */ 326 #define DMA7_CURR_DESC_PTR 0xffc00de0 /* DMA Channel 7 Current Descriptor Pointer Register */ 327 #define DMA7_CURR_ADDR 0xffc00de4 /* DMA Channel 7 Current Address Register */ 330 #define DMA7_CURR_X_COUNT 0xffc00df0 /* DMA Channel 7 Current X Count Register */ 331 #define DMA7_CURR_Y_COUNT 0xffc00df8 /* DMA Channel 7 Current Y Count Register */ 342 #define DMA8_CURR_DESC_PTR 0xffc00e20 /* DMA Channel 8 Current Descriptor Pointer Register */ 343 #define DMA8_CURR_ADDR 0xffc00e24 /* DMA Channel 8 Current Address Register */ 346 #define DMA8_CURR_X_COUNT 0xffc00e30 /* DMA Channel 8 Current X Count Register */ 347 #define DMA8_CURR_Y_COUNT 0xffc00e38 /* DMA Channel 8 Current Y Count Register */ 358 #define DMA9_CURR_DESC_PTR 0xffc00e60 /* DMA Channel 9 Current Descriptor Pointer Register */ 359 #define DMA9_CURR_ADDR 0xffc00e64 /* DMA Channel 9 Current Address Register */ 362 #define DMA9_CURR_X_COUNT 0xffc00e70 /* DMA Channel 9 Current X Count Register */ 363 #define DMA9_CURR_Y_COUNT 0xffc00e78 /* DMA Channel 9 Current Y Count Register */ 374 #define DMA10_CURR_DESC_PTR 0xffc00ea0 /* DMA Channel 10 Current Descriptor Pointer Register */ 375 #define DMA10_CURR_ADDR 0xffc00ea4 /* DMA Channel 10 Current Address Register */ 378 #define DMA10_CURR_X_COUNT 0xffc00eb0 /* DMA Channel 10 Current X Count Register */ 379 #define DMA10_CURR_Y_COUNT 0xffc00eb8 /* DMA Channel 10 Current Y Count Register */ 390 #define DMA11_CURR_DESC_PTR 0xffc00ee0 /* DMA Channel 11 Current Descriptor Pointer Register */ 391 #define DMA11_CURR_ADDR 0xffc00ee4 /* DMA Channel 11 Current Address Register */ 394 #define DMA11_CURR_X_COUNT 0xffc00ef0 /* DMA Channel 11 Current X Count Register */ 395 #define DMA11_CURR_Y_COUNT 0xffc00ef8 /* DMA Channel 11 Current Y Count Register */ 406 #define MDMA_D0_CURR_DESC_PTR 0xffc00f20 /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */ 407 #define MDMA_D0_CURR_ADDR 0xffc00f24 /* Memory DMA Stream 0 Destination Current Address Register */ 410 #define MDMA_D0_CURR_X_COUNT 0xffc00f30 /* Memory DMA Stream 0 Destination Current X Count Register */ 411 #define MDMA_D0_CURR_Y_COUNT 0xffc00f38 /* Memory DMA Stream 0 Destination Current Y Count Register */ 419 #define MDMA_S0_CURR_DESC_PTR 0xffc00f60 /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */ 420 #define MDMA_S0_CURR_ADDR 0xffc00f64 /* Memory DMA Stream 0 Source Current Address Register */ 423 #define MDMA_S0_CURR_X_COUNT 0xffc00f70 /* Memory DMA Stream 0 Source Current X Count Register */ 424 #define MDMA_S0_CURR_Y_COUNT 0xffc00f78 /* Memory DMA Stream 0 Source Current Y Count Register */ 435 #define MDMA_D1_CURR_DESC_PTR 0xffc00fa0 /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */ 436 #define MDMA_D1_CURR_ADDR 0xffc00fa4 /* Memory DMA Stream 1 Destination Current Address Register */ 439 #define MDMA_D1_CURR_X_COUNT 0xffc00fb0 /* Memory DMA Stream 1 Destination Current X Count Register */ 440 #define MDMA_D1_CURR_Y_COUNT 0xffc00fb8 /* Memory DMA Stream 1 Destination Current Y Count Register */ 448 #define MDMA_S1_CURR_DESC_PTR 0xffc00fe0 /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */ 449 #define MDMA_S1_CURR_ADDR 0xffc00fe4 /* Memory DMA Stream 1 Source Current Address Register */ 452 #define MDMA_S1_CURR_X_COUNT 0xffc00ff0 /* Memory DMA Stream 1 Source Current X Count Register */ 453 #define MDMA_S1_CURR_Y_COUNT 0xffc00ff8 /* Memory DMA Stream 1 Source Current Y Count Register */ 693 #define DMAC1_TC_CNT 0xffc01b10 /* DMA Controller 1 Current Counts Register */ 704 #define DMA12_CURR_DESC_PTR 0xffc01c20 /* DMA Channel 12 Current Descriptor Pointer Register */ 705 #define DMA12_CURR_ADDR 0xffc01c24 /* DMA Channel 12 Current Address Register */ 708 #define DMA12_CURR_X_COUNT 0xffc01c30 /* DMA Channel 12 Current X Count Register */ 709 #define DMA12_CURR_Y_COUNT 0xffc01c38 /* DMA Channel 12 Current Y Count Register */ 720 #define DMA13_CURR_DESC_PTR 0xffc01c60 /* DMA Channel 13 Current Descriptor Pointer Register */ 721 #define DMA13_CURR_ADDR 0xffc01c64 /* DMA Channel 13 Current Address Register */ 724 #define DMA13_CURR_X_COUNT 0xffc01c70 /* DMA Channel 13 Current X Count Register */ 725 #define DMA13_CURR_Y_COUNT 0xffc01c78 /* DMA Channel 13 Current Y Count Register */ 736 #define DMA14_CURR_DESC_PTR 0xffc01ca0 /* DMA Channel 14 Current Descriptor Pointer Register */ 737 #define DMA14_CURR_ADDR 0xffc01ca4 /* DMA Channel 14 Current Address Register */ 740 #define DMA14_CURR_X_COUNT 0xffc01cb0 /* DMA Channel 14 Current X Count Register */ 741 #define DMA14_CURR_Y_COUNT 0xffc01cb8 /* DMA Channel 14 Current Y Count Register */ 752 #define DMA15_CURR_DESC_PTR 0xffc01ce0 /* DMA Channel 15 Current Descriptor Pointer Register */ 753 #define DMA15_CURR_ADDR 0xffc01ce4 /* DMA Channel 15 Current Address Register */ 756 #define DMA15_CURR_X_COUNT 0xffc01cf0 /* DMA Channel 15 Current X Count Register */ 757 #define DMA15_CURR_Y_COUNT 0xffc01cf8 /* DMA Channel 15 Current Y Count Register */ 768 #define DMA16_CURR_DESC_PTR 0xffc01d20 /* DMA Channel 16 Current Descriptor Pointer Register */ 769 #define DMA16_CURR_ADDR 0xffc01d24 /* DMA Channel 16 Current Address Register */ 772 #define DMA16_CURR_X_COUNT 0xffc01d30 /* DMA Channel 16 Current X Count Register */ 773 #define DMA16_CURR_Y_COUNT 0xffc01d38 /* DMA Channel 16 Current Y Count Register */ 784 #define DMA17_CURR_DESC_PTR 0xffc01d60 /* DMA Channel 17 Current Descriptor Pointer Register */ 785 #define DMA17_CURR_ADDR 0xffc01d64 /* DMA Channel 17 Current Address Register */ 788 #define DMA17_CURR_X_COUNT 0xffc01d70 /* DMA Channel 17 Current X Count Register */ 789 #define DMA17_CURR_Y_COUNT 0xffc01d78 /* DMA Channel 17 Current Y Count Register */ 800 #define DMA18_CURR_DESC_PTR 0xffc01da0 /* DMA Channel 18 Current Descriptor Pointer Register */ 801 #define DMA18_CURR_ADDR 0xffc01da4 /* DMA Channel 18 Current Address Register */ 804 #define DMA18_CURR_X_COUNT 0xffc01db0 /* DMA Channel 18 Current X Count Register */ 805 #define DMA18_CURR_Y_COUNT 0xffc01db8 /* DMA Channel 18 Current Y Count Register */ 816 #define DMA19_CURR_DESC_PTR 0xffc01de0 /* DMA Channel 19 Current Descriptor Pointer Register */ 817 #define DMA19_CURR_ADDR 0xffc01de4 /* DMA Channel 19 Current Address Register */ 820 #define DMA19_CURR_X_COUNT 0xffc01df0 /* DMA Channel 19 Current X Count Register */ 821 #define DMA19_CURR_Y_COUNT 0xffc01df8 /* DMA Channel 19 Current Y Count Register */ 832 #define DMA20_CURR_DESC_PTR 0xffc01e20 /* DMA Channel 20 Current Descriptor Pointer Register */ 833 #define DMA20_CURR_ADDR 0xffc01e24 /* DMA Channel 20 Current Address Register */ 836 #define DMA20_CURR_X_COUNT 0xffc01e30 /* DMA Channel 20 Current X Count Register */ 837 #define DMA20_CURR_Y_COUNT 0xffc01e38 /* DMA Channel 20 Current Y Count Register */ 848 #define DMA21_CURR_DESC_PTR 0xffc01e60 /* DMA Channel 21 Current Descriptor Pointer Register */ 849 #define DMA21_CURR_ADDR 0xffc01e64 /* DMA Channel 21 Current Address Register */ 852 #define DMA21_CURR_X_COUNT 0xffc01e70 /* DMA Channel 21 Current X Count Register */ 853 #define DMA21_CURR_Y_COUNT 0xffc01e78 /* DMA Channel 21 Current Y Count Register */ 864 #define DMA22_CURR_DESC_PTR 0xffc01ea0 /* DMA Channel 22 Current Descriptor Pointer Register */ 865 #define DMA22_CURR_ADDR 0xffc01ea4 /* DMA Channel 22 Current Address Register */ 868 #define DMA22_CURR_X_COUNT 0xffc01eb0 /* DMA Channel 22 Current X Count Register */ 869 #define DMA22_CURR_Y_COUNT 0xffc01eb8 /* DMA Channel 22 Current Y Count Register */ 880 #define DMA23_CURR_DESC_PTR 0xffc01ee0 /* DMA Channel 23 Current Descriptor Pointer Register */ 881 #define DMA23_CURR_ADDR 0xffc01ee4 /* DMA Channel 23 Current Address Register */ 884 #define DMA23_CURR_X_COUNT 0xffc01ef0 /* DMA Channel 23 Current X Count Register */ 885 #define DMA23_CURR_Y_COUNT 0xffc01ef8 /* DMA Channel 23 Current Y Count Register */ 896 #define MDMA_D2_CURR_DESC_PTR 0xffc01f20 /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */ 897 #define MDMA_D2_CURR_ADDR 0xffc01f24 /* Memory DMA Stream 2 Destination Current Address Register */ 900 #define MDMA_D2_CURR_X_COUNT 0xffc01f30 /* Memory DMA Stream 2 Destination Current X Count Register */ 901 #define MDMA_D2_CURR_Y_COUNT 0xffc01f38 /* Memory DMA Stream 2 Destination Current Y Count Register */ 909 #define MDMA_S2_CURR_DESC_PTR 0xffc01f60 /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */ 910 #define MDMA_S2_CURR_ADDR 0xffc01f64 /* Memory DMA Stream 2 Source Current Address Register */ 913 #define MDMA_S2_CURR_X_COUNT 0xffc01f70 /* Memory DMA Stream 2 Source Current X Count Register */ 914 #define MDMA_S2_CURR_Y_COUNT 0xffc01f78 /* Memory DMA Stream 2 Source Current Y Count Register */ 925 #define MDMA_D3_CURR_DESC_PTR 0xffc01fa0 /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */ 926 #define MDMA_D3_CURR_ADDR 0xffc01fa4 /* Memory DMA Stream 3 Destination Current Address Register */ 929 #define MDMA_D3_CURR_X_COUNT 0xffc01fb0 /* Memory DMA Stream 3 Destination Current X Count Register */ 930 #define MDMA_D3_CURR_Y_COUNT 0xffc01fb8 /* Memory DMA Stream 3 Destination Current Y Count Register */ 938 #define MDMA_S3_CURR_DESC_PTR 0xffc01fe0 /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */ 939 #define MDMA_S3_CURR_ADDR 0xffc01fe4 /* Memory DMA Stream 3 Source Current Address Register */ 942 #define MDMA_S3_CURR_X_COUNT 0xffc01ff0 /* Memory DMA Stream 3 Source Current X Count Register */ 943 #define MDMA_S3_CURR_Y_COUNT 0xffc01ff8 /* Memory DMA Stream 3 Source Current Y Count Register */ 986 #define SPORT2_CHNL 0xffc02534 /* SPORT2 Current Channel Register */ 1011 #define SPORT3_CHNL 0xffc02634 /* SPORT3 Current Channel Register */
/linux-4.1.27/arch/blackfin/mach-bf561/include/mach/
H A D	defBF561.h	245 #define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ 269 #define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ 320 #define DMA1_0_CURR_DESC_PTR 0xFFC01C20 /* DMA1 Channel 0 Current Descriptor Pointer */ 321 #define DMA1_0_CURR_ADDR 0xFFC01C24 /* DMA1 Channel 0 Current Address Pointer */ 322 #define DMA1_0_CURR_X_COUNT 0xFFC01C30 /* DMA1 Channel 0 Current Inner Loop Count */ 323 #define DMA1_0_CURR_Y_COUNT 0xFFC01C38 /* DMA1 Channel 0 Current Outer Loop Count */ 334 #define DMA1_1_CURR_DESC_PTR 0xFFC01C60 /* DMA1 Channel 1 Current Descriptor Pointer */ 335 #define DMA1_1_CURR_ADDR 0xFFC01C64 /* DMA1 Channel 1 Current Address Pointer */ 336 #define DMA1_1_CURR_X_COUNT 0xFFC01C70 /* DMA1 Channel 1 Current Inner Loop Count */ 337 #define DMA1_1_CURR_Y_COUNT 0xFFC01C78 /* DMA1 Channel 1 Current Outer Loop Count */ 348 #define DMA1_2_CURR_DESC_PTR 0xFFC01CA0 /* DMA1 Channel 2 Current Descriptor Pointer */ 349 #define DMA1_2_CURR_ADDR 0xFFC01CA4 /* DMA1 Channel 2 Current Address Pointer */ 350 #define DMA1_2_CURR_X_COUNT 0xFFC01CB0 /* DMA1 Channel 2 Current Inner Loop Count */ 351 #define DMA1_2_CURR_Y_COUNT 0xFFC01CB8 /* DMA1 Channel 2 Current Outer Loop Count */ 362 #define DMA1_3_CURR_DESC_PTR 0xFFC01CE0 /* DMA1 Channel 3 Current Descriptor Pointer */ 363 #define DMA1_3_CURR_ADDR 0xFFC01CE4 /* DMA1 Channel 3 Current Address Pointer */ 364 #define DMA1_3_CURR_X_COUNT 0xFFC01CF0 /* DMA1 Channel 3 Current Inner Loop Count */ 365 #define DMA1_3_CURR_Y_COUNT 0xFFC01CF8 /* DMA1 Channel 3 Current Outer Loop Count */ 376 #define DMA1_4_CURR_DESC_PTR 0xFFC01D20 /* DMA1 Channel 4 Current Descriptor Pointer */ 377 #define DMA1_4_CURR_ADDR 0xFFC01D24 /* DMA1 Channel 4 Current Address Pointer */ 378 #define DMA1_4_CURR_X_COUNT 0xFFC01D30 /* DMA1 Channel 4 Current Inner Loop Count */ 379 #define DMA1_4_CURR_Y_COUNT 0xFFC01D38 /* DMA1 Channel 4 Current Outer Loop Count */ 390 #define DMA1_5_CURR_DESC_PTR 0xFFC01D60 /* DMA1 Channel 5 Current Descriptor Pointer */ 391 #define DMA1_5_CURR_ADDR 0xFFC01D64 /* DMA1 Channel 5 Current Address Pointer */ 392 #define DMA1_5_CURR_X_COUNT 0xFFC01D70 /* DMA1 Channel 5 Current Inner Loop Count */ 393 #define DMA1_5_CURR_Y_COUNT 0xFFC01D78 /* DMA1 Channel 5 Current Outer Loop Count */ 404 #define DMA1_6_CURR_DESC_PTR 0xFFC01DA0 /* DMA1 Channel 6 Current Descriptor Pointer */ 405 #define DMA1_6_CURR_ADDR 0xFFC01DA4 /* DMA1 Channel 6 Current Address Pointer */ 406 #define DMA1_6_CURR_X_COUNT 0xFFC01DB0 /* DMA1 Channel 6 Current Inner Loop Count */ 407 #define DMA1_6_CURR_Y_COUNT 0xFFC01DB8 /* DMA1 Channel 6 Current Outer Loop Count */ 418 #define DMA1_7_CURR_DESC_PTR 0xFFC01DE0 /* DMA1 Channel 7 Current Descriptor Pointer */ 419 #define DMA1_7_CURR_ADDR 0xFFC01DE4 /* DMA1 Channel 7 Current Address Pointer */ 420 #define DMA1_7_CURR_X_COUNT 0xFFC01DF0 /* DMA1 Channel 7 Current Inner Loop Count */ 421 #define DMA1_7_CURR_Y_COUNT 0xFFC01DF8 /* DMA1 Channel 7 Current Outer Loop Count */ 432 #define DMA1_8_CURR_DESC_PTR 0xFFC01E20 /* DMA1 Channel 8 Current Descriptor Pointer */ 433 #define DMA1_8_CURR_ADDR 0xFFC01E24 /* DMA1 Channel 8 Current Address Pointer */ 434 #define DMA1_8_CURR_X_COUNT 0xFFC01E30 /* DMA1 Channel 8 Current Inner Loop Count */ 435 #define DMA1_8_CURR_Y_COUNT 0xFFC01E38 /* DMA1 Channel 8 Current Outer Loop Count */ 446 #define DMA1_9_CURR_DESC_PTR 0xFFC01E60 /* DMA1 Channel 9 Current Descriptor Pointer */ 447 #define DMA1_9_CURR_ADDR 0xFFC01E64 /* DMA1 Channel 9 Current Address Pointer */ 448 #define DMA1_9_CURR_X_COUNT 0xFFC01E70 /* DMA1 Channel 9 Current Inner Loop Count */ 449 #define DMA1_9_CURR_Y_COUNT 0xFFC01E78 /* DMA1 Channel 9 Current Outer Loop Count */ 460 #define DMA1_10_CURR_DESC_PTR 0xFFC01EA0 /* DMA1 Channel 10 Current Descriptor Pointer */ 461 #define DMA1_10_CURR_ADDR 0xFFC01EA4 /* DMA1 Channel 10 Current Address Pointer */ 462 #define DMA1_10_CURR_X_COUNT 0xFFC01EB0 /* DMA1 Channel 10 Current Inner Loop Count */ 463 #define DMA1_10_CURR_Y_COUNT 0xFFC01EB8 /* DMA1 Channel 10 Current Outer Loop Count */ 474 #define DMA1_11_CURR_DESC_PTR 0xFFC01EE0 /* DMA1 Channel 11 Current Descriptor Pointer */ 475 #define DMA1_11_CURR_ADDR 0xFFC01EE4 /* DMA1 Channel 11 Current Address Pointer */ 476 #define DMA1_11_CURR_X_COUNT 0xFFC01EF0 /* DMA1 Channel 11 Current Inner Loop Count */ 477 #define DMA1_11_CURR_Y_COUNT 0xFFC01EF8 /* DMA1 Channel 11 Current Outer Loop Count */ 489 #define MDMA_D0_CURR_DESC_PTR 0xFFC01F20 /*MemDMA1 Stream 0 Dest Current Descriptor Ptr reg */ 490 #define MDMA_D0_CURR_ADDR 0xFFC01F24 /*MemDMA1 Stream 0 Destination Current Address */ 491 #define MDMA_D0_CURR_X_COUNT 0xFFC01F30 /*MemDMA1 Stream 0 Dest Current Inner-Loop Count */ 492 #define MDMA_D0_CURR_Y_COUNT 0xFFC01F38 /*MemDMA1 Stream 0 Dest Current Outer-Loop Count */ 503 #define MDMA_S0_CURR_DESC_PTR 0xFFC01F60 /*MemDMA1 Stream 0 Source Current Descriptor Ptr reg */ 504 #define MDMA_S0_CURR_ADDR 0xFFC01F64 /*MemDMA1 Stream 0 Source Current Address */ 505 #define MDMA_S0_CURR_X_COUNT 0xFFC01F70 /*MemDMA1 Stream 0 Source Current Inner-Loop Count */ 506 #define MDMA_S0_CURR_Y_COUNT 0xFFC01F78 /*MemDMA1 Stream 0 Source Current Outer-Loop Count */ 517 #define MDMA_D1_CURR_DESC_PTR 0xFFC01FA0 /*MemDMA1 Stream 1 Dest Current Descriptor Ptr reg */ 518 #define MDMA_D1_CURR_ADDR 0xFFC01FA4 /*MemDMA1 Stream 1 Dest Current Address */ 519 #define MDMA_D1_CURR_X_COUNT 0xFFC01FB0 /*MemDMA1 Stream 1 Dest Current Inner-Loop Count */ 520 #define MDMA_D1_CURR_Y_COUNT 0xFFC01FB8 /*MemDMA1 Stream 1 Dest Current Outer-Loop Count */ 531 #define MDMA_S1_CURR_DESC_PTR 0xFFC01FE0 /*MemDMA1 Stream 1 Source Current Descriptor Ptr reg */ 532 #define MDMA_S1_CURR_ADDR 0xFFC01FE4 /*MemDMA1 Stream 1 Source Current Address */ 533 #define MDMA_S1_CURR_X_COUNT 0xFFC01FF0 /*MemDMA1 Stream 1 Source Current Inner-Loop Count */ 534 #define MDMA_S1_CURR_Y_COUNT 0xFFC01FF8 /*MemDMA1 Stream 1 Source Current Outer-Loop Count */ 546 #define DMA2_0_CURR_DESC_PTR 0xFFC00C20 /* DMA2 Channel 0 Current Descriptor Pointer */ 547 #define DMA2_0_CURR_ADDR 0xFFC00C24 /* DMA2 Channel 0 Current Address Pointer */ 548 #define DMA2_0_CURR_X_COUNT 0xFFC00C30 /* DMA2 Channel 0 Current Inner Loop Count */ 549 #define DMA2_0_CURR_Y_COUNT 0xFFC00C38 /* DMA2 Channel 0 Current Outer Loop Count */ 560 #define DMA2_1_CURR_DESC_PTR 0xFFC00C60 /* DMA2 Channel 1 Current Descriptor Pointer */ 561 #define DMA2_1_CURR_ADDR 0xFFC00C64 /* DMA2 Channel 1 Current Address Pointer */ 562 #define DMA2_1_CURR_X_COUNT 0xFFC00C70 /* DMA2 Channel 1 Current Inner Loop Count */ 563 #define DMA2_1_CURR_Y_COUNT 0xFFC00C78 /* DMA2 Channel 1 Current Outer Loop Count */ 574 #define DMA2_2_CURR_DESC_PTR 0xFFC00CA0 /* DMA2 Channel 2 Current Descriptor Pointer */ 575 #define DMA2_2_CURR_ADDR 0xFFC00CA4 /* DMA2 Channel 2 Current Address Pointer */ 576 #define DMA2_2_CURR_X_COUNT 0xFFC00CB0 /* DMA2 Channel 2 Current Inner Loop Count */ 577 #define DMA2_2_CURR_Y_COUNT 0xFFC00CB8 /* DMA2 Channel 2 Current Outer Loop Count */ 588 #define DMA2_3_CURR_DESC_PTR 0xFFC00CE0 /* DMA2 Channel 3 Current Descriptor Pointer */ 589 #define DMA2_3_CURR_ADDR 0xFFC00CE4 /* DMA2 Channel 3 Current Address Pointer */ 590 #define DMA2_3_CURR_X_COUNT 0xFFC00CF0 /* DMA2 Channel 3 Current Inner Loop Count */ 591 #define DMA2_3_CURR_Y_COUNT 0xFFC00CF8 /* DMA2 Channel 3 Current Outer Loop Count */ 602 #define DMA2_4_CURR_DESC_PTR 0xFFC00D20 /* DMA2 Channel 4 Current Descriptor Pointer */ 603 #define DMA2_4_CURR_ADDR 0xFFC00D24 /* DMA2 Channel 4 Current Address Pointer */ 604 #define DMA2_4_CURR_X_COUNT 0xFFC00D30 /* DMA2 Channel 4 Current Inner Loop Count */ 605 #define DMA2_4_CURR_Y_COUNT 0xFFC00D38 /* DMA2 Channel 4 Current Outer Loop Count */ 616 #define DMA2_5_CURR_DESC_PTR 0xFFC00D60 /* DMA2 Channel 5 Current Descriptor Pointer */ 617 #define DMA2_5_CURR_ADDR 0xFFC00D64 /* DMA2 Channel 5 Current Address Pointer */ 618 #define DMA2_5_CURR_X_COUNT 0xFFC00D70 /* DMA2 Channel 5 Current Inner Loop Count */ 619 #define DMA2_5_CURR_Y_COUNT 0xFFC00D78 /* DMA2 Channel 5 Current Outer Loop Count */ 630 #define DMA2_6_CURR_DESC_PTR 0xFFC00DA0 /* DMA2 Channel 6 Current Descriptor Pointer */ 631 #define DMA2_6_CURR_ADDR 0xFFC00DA4 /* DMA2 Channel 6 Current Address Pointer */ 632 #define DMA2_6_CURR_X_COUNT 0xFFC00DB0 /* DMA2 Channel 6 Current Inner Loop Count */ 633 #define DMA2_6_CURR_Y_COUNT 0xFFC00DB8 /* DMA2 Channel 6 Current Outer Loop Count */ 644 #define DMA2_7_CURR_DESC_PTR 0xFFC00DE0 /* DMA2 Channel 7 Current Descriptor Pointer */ 645 #define DMA2_7_CURR_ADDR 0xFFC00DE4 /* DMA2 Channel 7 Current Address Pointer */ 646 #define DMA2_7_CURR_X_COUNT 0xFFC00DF0 /* DMA2 Channel 7 Current Inner Loop Count */ 647 #define DMA2_7_CURR_Y_COUNT 0xFFC00DF8 /* DMA2 Channel 7 Current Outer Loop Count */ 658 #define DMA2_8_CURR_DESC_PTR 0xFFC00E20 /* DMA2 Channel 8 Current Descriptor Pointer */ 659 #define DMA2_8_CURR_ADDR 0xFFC00E24 /* DMA2 Channel 8 Current Address Pointer */ 660 #define DMA2_8_CURR_X_COUNT 0xFFC00E30 /* DMA2 Channel 8 Current Inner Loop Count */ 661 #define DMA2_8_CURR_Y_COUNT 0xFFC00E38 /* DMA2 Channel 8 Current Outer Loop Count */ 672 #define DMA2_9_CURR_DESC_PTR 0xFFC00E60 /* DMA2 Channel 9 Current Descriptor Pointer */ 673 #define DMA2_9_CURR_ADDR 0xFFC00E64 /* DMA2 Channel 9 Current Address Pointer */ 674 #define DMA2_9_CURR_X_COUNT 0xFFC00E70 /* DMA2 Channel 9 Current Inner Loop Count */ 675 #define DMA2_9_CURR_Y_COUNT 0xFFC00E78 /* DMA2 Channel 9 Current Outer Loop Count */ 686 #define DMA2_10_CURR_DESC_PTR 0xFFC00EA0 /* DMA2 Channel 10 Current Descriptor Pointer */ 687 #define DMA2_10_CURR_ADDR 0xFFC00EA4 /* DMA2 Channel 10 Current Address Pointer */ 688 #define DMA2_10_CURR_X_COUNT 0xFFC00EB0 /* DMA2 Channel 10 Current Inner Loop Count */ 689 #define DMA2_10_CURR_Y_COUNT 0xFFC00EB8 /* DMA2 Channel 10 Current Outer Loop Count */ 700 #define DMA2_11_CURR_DESC_PTR 0xFFC00EE0 /* DMA2 Channel 11 Current Descriptor Pointer */ 701 #define DMA2_11_CURR_ADDR 0xFFC00EE4 /* DMA2 Channel 11 Current Address Pointer */ 702 #define DMA2_11_CURR_X_COUNT 0xFFC00EF0 /* DMA2 Channel 11 Current Inner Loop Count */ 703 #define DMA2_11_CURR_Y_COUNT 0xFFC00EF8 /* DMA2 Channel 11 Current Outer Loop Count */ 715 #define MDMA_D2_CURR_DESC_PTR 0xFFC00F20 /*MemDMA2 Stream 0 Dest Current Descriptor Ptr reg */ 716 #define MDMA_D2_CURR_ADDR 0xFFC00F24 /*MemDMA2 Stream 0 Destination Current Address */ 717 #define MDMA_D2_CURR_X_COUNT 0xFFC00F30 /*MemDMA2 Stream 0 Dest Current Inner-Loop Count reg */ 718 #define MDMA_D2_CURR_Y_COUNT 0xFFC00F38 /*MemDMA2 Stream 0 Dest Current Outer-Loop Count reg */ 729 #define MDMA_S2_CURR_DESC_PTR 0xFFC00F60 /*MemDMA2 Stream 0 Source Current Descriptor Ptr reg */ 730 #define MDMA_S2_CURR_ADDR 0xFFC00F64 /*MemDMA2 Stream 0 Source Current Address */ 731 #define MDMA_S2_CURR_X_COUNT 0xFFC00F70 /*MemDMA2 Stream 0 Src Current Inner-Loop Count reg */ 732 #define MDMA_S2_CURR_Y_COUNT 0xFFC00F78 /*MemDMA2 Stream 0 Src Current Outer-Loop Count reg */ 743 #define MDMA_D3_CURR_DESC_PTR 0xFFC00FA0 /*MemDMA2 Stream 1 Destination Current Descriptor Ptr */ 744 #define MDMA_D3_CURR_ADDR 0xFFC00FA4 /*MemDMA2 Stream 1 Destination Current Address reg */ 745 #define MDMA_D3_CURR_X_COUNT 0xFFC00FB0 /*MemDMA2 Stream 1 Dest Current Inner-Loop Count reg */ 746 #define MDMA_D3_CURR_Y_COUNT 0xFFC00FB8 /*MemDMA2 Stream 1 Dest Current Outer-Loop Count reg */ 757 #define MDMA_S3_CURR_DESC_PTR 0xFFC00FE0 /*MemDMA2 Stream 1 Source Current Descriptor Ptr reg */ 758 #define MDMA_S3_CURR_ADDR 0xFFC00FE4 /*MemDMA2 Stream 1 Source Current Address */ 759 #define MDMA_S3_CURR_X_COUNT 0xFFC00FF0 /*MemDMA2 Stream 1 Source Current Inner-Loop Count */ 760 #define MDMA_S3_CURR_Y_COUNT 0xFFC00FF8 /*MemDMA2 Stream 1 Source Current Outer-Loop Count */ 772 #define IMDMA_D0_CURR_DESC_PTR 0xFFC01820 /*IMDMA Stream 0 Destination Current Descriptor Ptr */ 773 #define IMDMA_D0_CURR_ADDR 0xFFC01824 /*IMDMA Stream 0 Destination Current Address */ 774 #define IMDMA_D0_CURR_X_COUNT 0xFFC01830 /*IMDMA Stream 0 Destination Current Inner-Loop Count */ 775 #define IMDMA_D0_CURR_Y_COUNT 0xFFC01838 /*IMDMA Stream 0 Destination Current Outer-Loop Count */ 785 #define IMDMA_S0_CURR_DESC_PTR 0xFFC01860 /*IMDMA Stream 0 Source Current Descriptor Ptr reg */ 786 #define IMDMA_S0_CURR_ADDR 0xFFC01864 /*IMDMA Stream 0 Source Current Address */ 787 #define IMDMA_S0_CURR_X_COUNT 0xFFC01870 /*IMDMA Stream 0 Source Current Inner-Loop Count */ 788 #define IMDMA_S0_CURR_Y_COUNT 0xFFC01878 /*IMDMA Stream 0 Source Current Outer-Loop Count */ 798 #define IMDMA_D1_CURR_DESC_PTR 0xFFC018A0 /*IMDMA Stream 1 Destination Current Descriptor Ptr */ 799 #define IMDMA_D1_CURR_ADDR 0xFFC018A4 /*IMDMA Stream 1 Destination Current Address */ 800 #define IMDMA_D1_CURR_X_COUNT 0xFFC018B0 /*IMDMA Stream 1 Destination Current Inner-Loop Count */ 801 #define IMDMA_D1_CURR_Y_COUNT 0xFFC018B8 /*IMDMA Stream 1 Destination Current Outer-Loop Count */ 811 #define IMDMA_S1_CURR_DESC_PTR 0xFFC018E0 /*IMDMA Stream 1 Source Current Descriptor Ptr reg */ 812 #define IMDMA_S1_CURR_ADDR 0xFFC018E4 /*IMDMA Stream 1 Source Current Address */ 813 #define IMDMA_S1_CURR_X_COUNT 0xFFC018F0 /*IMDMA Stream 1 Source Current Inner-Loop Count */ 814 #define IMDMA_S1_CURR_Y_COUNT 0xFFC018F8 /*IMDMA Stream 1 Source Current Outer-Loop Count */
/linux-4.1.27/arch/arc/include/asm/
H A D	current.h	9 * - Current macro is now implemented as "global register" r25
H A D	mach_desc.h	52 * Current machine - only accessible during boot.
/linux-4.1.27/sound/soc/codecs/
H A D	cs35l32.h	22 /* LED Current Management*/ 58 #define CS35L32_FLASH_MODE 0x19 /* LED Flash Mode Current */ 59 #define CS35L32_MOVIE_MODE 0x1A /* LED Movie Mode Current */ 61 #define CS35L32_FLASH_INHIBIT 0x1C /* LED Flash Inhibit Current */
H A D	88pm860x-codec.c	517 SOC_ENUM("Headset1 Operational Amplifier Current", 519 SOC_ENUM("Headset2 Operational Amplifier Current", 521 SOC_ENUM("Headset1 Amplifier Current", pm860x_hs1_pa_enum), 522 SOC_ENUM("Headset2 Amplifier Current", pm860x_hs2_pa_enum), 523 SOC_ENUM("Lineout1 Operational Amplifier Current", 525 SOC_ENUM("Lineout2 Operational Amplifier Current", 527 SOC_ENUM("Lineout1 Amplifier Current", pm860x_lo1_pa_enum), 528 SOC_ENUM("Lineout2 Amplifier Current", pm860x_lo2_pa_enum), 529 SOC_ENUM("Speaker Operational Amplifier Current", 531 SOC_ENUM("Speaker Amplifier Current", pm860x_spk_pa_enum), 532 SOC_ENUM("Earpiece Amplifier Current", pm860x_ear_pa_enum),
H A D	cs35l32.c	69 { 0x19, 0x00 }, /* LED Flash Mode Current */ 70 { 0x1A, 0x00 }, /* LED Movie Mode Current */ 72 { 0x1C, 0x00 }, /* LED Flash Inhibit Current */ 279 /* Current and threshold powerup sequence Pg37 in datasheet */
H A D	pcm1681.c	85 /* Current deemphasis status */ 87 /* Current rate for deemphasis control */
/linux-4.1.27/arch/blackfin/mach-bf609/include/mach/
H A D	defBF60x_base.h	445 #define LP0_CNT 0xFFC0100C /* LP0 Current Count Value of Clock Divider */ 453 #define LP1_CNT 0xFFC0110C /* LP1 Current Count Value of Clock Divider */ 461 #define LP2_CNT 0xFFC0120C /* LP2 Current Count Value of Clock Divider */ 469 #define LP3_CNT 0xFFC0130C /* LP3 Current Count Value of Clock Divider */ 567 #define REG_CRC0_RESULT_CUR 0xFFC01C50 /* CRC0 Current CRC Result Register */ 586 #define REG_CRC1_RESULT_CUR 0xFFC01D50 /* CRC1 Current CRC Result Register */ 1346 #define SPORT0_CNT_A 0xFFC4001C /* SPORT0 'A' Frame Sync And Clock Divisor Current Count */ 1361 #define SPORT0_CNT_B 0xFFC4009C /* SPORT0 'B' Frame Sync And Clock Divisor Current Count */ 1380 #define SPORT1_CNT_A 0xFFC4011C /* SPORT1 'A' Frame Sync And Clock Divisor Current Count */ 1395 #define SPORT1_CNT_B 0xFFC4019C /* SPORT1 'B' Frame Sync And Clock Divisor Current Count */ 1414 #define SPORT2_CNT_A 0xFFC4021C /* SPORT2 'A' Frame Sync And Clock Divisor Current Count */ 1429 #define SPORT2_CNT_B 0xFFC4029C /* SPORT2 'B' Frame Sync And Clock Divisor Current Count */ 1521 #define DMA0_START_ADDR 0xFFC41004 /* DMA0 Start Address of Current Buffer */ 1527 #define DMA0_CURR_DESC_PTR 0xFFC41024 /* DMA0 Current Descriptor Pointer */ 1529 #define DMA0_CURR_ADDR 0xFFC4102C /* DMA0 Current Address */ 1531 #define DMA0_CURR_X_COUNT 0xFFC41034 /* DMA0 Current Count(1D) or intra-row XCNT (2D) */ 1532 #define DMA0_CURR_Y_COUNT 0xFFC41038 /* DMA0 Current Row Count (2D only) */ 1534 #define DMA0_CURR_BWL_COUNT 0xFFC41044 /* DMA0 Bandwidth Limit Count Current */ 1536 #define DMA0_CURR_BWM_COUNT 0xFFC4104C /* DMA0 Bandwidth Monitor Count Current */ 1542 #define DMA1_START_ADDR 0xFFC41084 /* DMA1 Start Address of Current Buffer */ 1548 #define DMA1_CURR_DESC_PTR 0xFFC410A4 /* DMA1 Current Descriptor Pointer */ 1550 #define DMA1_CURR_ADDR 0xFFC410AC /* DMA1 Current Address */ 1552 #define DMA1_CURR_X_COUNT 0xFFC410B4 /* DMA1 Current Count(1D) or intra-row XCNT (2D) */ 1553 #define DMA1_CURR_Y_COUNT 0xFFC410B8 /* DMA1 Current Row Count (2D only) */ 1555 #define DMA1_CURR_BWL_COUNT 0xFFC410C4 /* DMA1 Bandwidth Limit Count Current */ 1557 #define DMA1_CURR_BWM_COUNT 0xFFC410CC /* DMA1 Bandwidth Monitor Count Current */ 1563 #define DMA2_START_ADDR 0xFFC41104 /* DMA2 Start Address of Current Buffer */ 1569 #define DMA2_CURR_DESC_PTR 0xFFC41124 /* DMA2 Current Descriptor Pointer */ 1571 #define DMA2_CURR_ADDR 0xFFC4112C /* DMA2 Current Address */ 1573 #define DMA2_CURR_X_COUNT 0xFFC41134 /* DMA2 Current Count(1D) or intra-row XCNT (2D) */ 1574 #define DMA2_CURR_Y_COUNT 0xFFC41138 /* DMA2 Current Row Count (2D only) */ 1576 #define DMA2_CURR_BWL_COUNT 0xFFC41144 /* DMA2 Bandwidth Limit Count Current */ 1578 #define DMA2_CURR_BWM_COUNT 0xFFC4114C /* DMA2 Bandwidth Monitor Count Current */ 1584 #define DMA3_START_ADDR 0xFFC41184 /* DMA3 Start Address of Current Buffer */ 1590 #define DMA3_CURR_DESC_PTR 0xFFC411A4 /* DMA3 Current Descriptor Pointer */ 1592 #define DMA3_CURR_ADDR 0xFFC411AC /* DMA3 Current Address */ 1594 #define DMA3_CURR_X_COUNT 0xFFC411B4 /* DMA3 Current Count(1D) or intra-row XCNT (2D) */ 1595 #define DMA3_CURR_Y_COUNT 0xFFC411B8 /* DMA3 Current Row Count (2D only) */ 1597 #define DMA3_CURR_BWL_COUNT 0xFFC411C4 /* DMA3 Bandwidth Limit Count Current */ 1599 #define DMA3_CURR_BWM_COUNT 0xFFC411CC /* DMA3 Bandwidth Monitor Count Current */ 1605 #define DMA4_START_ADDR 0xFFC41204 /* DMA4 Start Address of Current Buffer */ 1611 #define DMA4_CURR_DESC_PTR 0xFFC41224 /* DMA4 Current Descriptor Pointer */ 1613 #define DMA4_CURR_ADDR 0xFFC4122C /* DMA4 Current Address */ 1615 #define DMA4_CURR_X_COUNT 0xFFC41234 /* DMA4 Current Count(1D) or intra-row XCNT (2D) */ 1616 #define DMA4_CURR_Y_COUNT 0xFFC41238 /* DMA4 Current Row Count (2D only) */ 1618 #define DMA4_CURR_BWL_COUNT 0xFFC41244 /* DMA4 Bandwidth Limit Count Current */ 1620 #define DMA4_CURR_BWM_COUNT 0xFFC4124C /* DMA4 Bandwidth Monitor Count Current */ 1626 #define DMA5_START_ADDR 0xFFC41284 /* DMA5 Start Address of Current Buffer */ 1632 #define DMA5_CURR_DESC_PTR 0xFFC412A4 /* DMA5 Current Descriptor Pointer */ 1634 #define DMA5_CURR_ADDR 0xFFC412AC /* DMA5 Current Address */ 1636 #define DMA5_CURR_X_COUNT 0xFFC412B4 /* DMA5 Current Count(1D) or intra-row XCNT (2D) */ 1637 #define DMA5_CURR_Y_COUNT 0xFFC412B8 /* DMA5 Current Row Count (2D only) */ 1639 #define DMA5_CURR_BWL_COUNT 0xFFC412C4 /* DMA5 Bandwidth Limit Count Current */ 1641 #define DMA5_CURR_BWM_COUNT 0xFFC412CC /* DMA5 Bandwidth Monitor Count Current */ 1647 #define DMA6_START_ADDR 0xFFC41304 /* DMA6 Start Address of Current Buffer */ 1653 #define DMA6_CURR_DESC_PTR 0xFFC41324 /* DMA6 Current Descriptor Pointer */ 1655 #define DMA6_CURR_ADDR 0xFFC4132C /* DMA6 Current Address */ 1657 #define DMA6_CURR_X_COUNT 0xFFC41334 /* DMA6 Current Count(1D) or intra-row XCNT (2D) */ 1658 #define DMA6_CURR_Y_COUNT 0xFFC41338 /* DMA6 Current Row Count (2D only) */ 1660 #define DMA6_CURR_BWL_COUNT 0xFFC41344 /* DMA6 Bandwidth Limit Count Current */ 1662 #define DMA6_CURR_BWM_COUNT 0xFFC4134C /* DMA6 Bandwidth Monitor Count Current */ 1668 #define DMA7_START_ADDR 0xFFC41384 /* DMA7 Start Address of Current Buffer */ 1674 #define DMA7_CURR_DESC_PTR 0xFFC413A4 /* DMA7 Current Descriptor Pointer */ 1676 #define DMA7_CURR_ADDR 0xFFC413AC /* DMA7 Current Address */ 1678 #define DMA7_CURR_X_COUNT 0xFFC413B4 /* DMA7 Current Count(1D) or intra-row XCNT (2D) */ 1679 #define DMA7_CURR_Y_COUNT 0xFFC413B8 /* DMA7 Current Row Count (2D only) */ 1681 #define DMA7_CURR_BWL_COUNT 0xFFC413C4 /* DMA7 Bandwidth Limit Count Current */ 1683 #define DMA7_CURR_BWM_COUNT 0xFFC413CC /* DMA7 Bandwidth Monitor Count Current */ 1689 #define DMA8_START_ADDR 0xFFC41404 /* DMA8 Start Address of Current Buffer */ 1695 #define DMA8_CURR_DESC_PTR 0xFFC41424 /* DMA8 Current Descriptor Pointer */ 1697 #define DMA8_CURR_ADDR 0xFFC4142C /* DMA8 Current Address */ 1699 #define DMA8_CURR_X_COUNT 0xFFC41434 /* DMA8 Current Count(1D) or intra-row XCNT (2D) */ 1700 #define DMA8_CURR_Y_COUNT 0xFFC41438 /* DMA8 Current Row Count (2D only) */ 1702 #define DMA8_CURR_BWL_COUNT 0xFFC41444 /* DMA8 Bandwidth Limit Count Current */ 1704 #define DMA8_CURR_BWM_COUNT 0xFFC4144C /* DMA8 Bandwidth Monitor Count Current */ 1710 #define DMA9_START_ADDR 0xFFC41484 /* DMA9 Start Address of Current Buffer */ 1716 #define DMA9_CURR_DESC_PTR 0xFFC414A4 /* DMA9 Current Descriptor Pointer */ 1718 #define DMA9_CURR_ADDR 0xFFC414AC /* DMA9 Current Address */ 1720 #define DMA9_CURR_X_COUNT 0xFFC414B4 /* DMA9 Current Count(1D) or intra-row XCNT (2D) */ 1721 #define DMA9_CURR_Y_COUNT 0xFFC414B8 /* DMA9 Current Row Count (2D only) */ 1723 #define DMA9_CURR_BWL_COUNT 0xFFC414C4 /* DMA9 Bandwidth Limit Count Current */ 1725 #define DMA9_CURR_BWM_COUNT 0xFFC414CC /* DMA9 Bandwidth Monitor Count Current */ 1731 #define DMA10_START_ADDR 0xFFC05004 /* DMA10 Start Address of Current Buffer */ 1737 #define DMA10_CURR_DESC_PTR 0xFFC05024 /* DMA10 Current Descriptor Pointer */ 1739 #define DMA10_CURR_ADDR 0xFFC0502C /* DMA10 Current Address */ 1741 #define DMA10_CURR_X_COUNT 0xFFC05034 /* DMA10 Current Count(1D) or intra-row XCNT (2D) */ 1742 #define DMA10_CURR_Y_COUNT 0xFFC05038 /* DMA10 Current Row Count (2D only) */ 1744 #define DMA10_CURR_BWL_COUNT 0xFFC05044 /* DMA10 Bandwidth Limit Count Current */ 1746 #define DMA10_CURR_BWM_COUNT 0xFFC0504C /* DMA10 Bandwidth Monitor Count Current */ 1752 #define DMA11_START_ADDR 0xFFC05084 /* DMA11 Start Address of Current Buffer */ 1758 #define DMA11_CURR_DESC_PTR 0xFFC050A4 /* DMA11 Current Descriptor Pointer */ 1760 #define DMA11_CURR_ADDR 0xFFC050AC /* DMA11 Current Address */ 1762 #define DMA11_CURR_X_COUNT 0xFFC050B4 /* DMA11 Current Count(1D) or intra-row XCNT (2D) */ 1763 #define DMA11_CURR_Y_COUNT 0xFFC050B8 /* DMA11 Current Row Count (2D only) */ 1765 #define DMA11_CURR_BWL_COUNT 0xFFC050C4 /* DMA11 Bandwidth Limit Count Current */ 1767 #define DMA11_CURR_BWM_COUNT 0xFFC050CC /* DMA11 Bandwidth Monitor Count Current */ 1773 #define DMA12_START_ADDR 0xFFC05104 /* DMA12 Start Address of Current Buffer */ 1779 #define DMA12_CURR_DESC_PTR 0xFFC05124 /* DMA12 Current Descriptor Pointer */ 1781 #define DMA12_CURR_ADDR 0xFFC0512C /* DMA12 Current Address */ 1783 #define DMA12_CURR_X_COUNT 0xFFC05134 /* DMA12 Current Count(1D) or intra-row XCNT (2D) */ 1784 #define DMA12_CURR_Y_COUNT 0xFFC05138 /* DMA12 Current Row Count (2D only) */ 1786 #define DMA12_CURR_BWL_COUNT 0xFFC05144 /* DMA12 Bandwidth Limit Count Current */ 1788 #define DMA12_CURR_BWM_COUNT 0xFFC0514C /* DMA12 Bandwidth Monitor Count Current */ 1794 #define DMA13_START_ADDR 0xFFC07004 /* DMA13 Start Address of Current Buffer */ 1800 #define DMA13_CURR_DESC_PTR 0xFFC07024 /* DMA13 Current Descriptor Pointer */ 1802 #define DMA13_CURR_ADDR 0xFFC0702C /* DMA13 Current Address */ 1804 #define DMA13_CURR_X_COUNT 0xFFC07034 /* DMA13 Current Count(1D) or intra-row XCNT (2D) */ 1805 #define DMA13_CURR_Y_COUNT 0xFFC07038 /* DMA13 Current Row Count (2D only) */ 1807 #define DMA13_CURR_BWL_COUNT 0xFFC07044 /* DMA13 Bandwidth Limit Count Current */ 1809 #define DMA13_CURR_BWM_COUNT 0xFFC0704C /* DMA13 Bandwidth Monitor Count Current */ 1815 #define DMA14_START_ADDR 0xFFC07084 /* DMA14 Start Address of Current Buffer */ 1821 #define DMA14_CURR_DESC_PTR 0xFFC070A4 /* DMA14 Current Descriptor Pointer */ 1823 #define DMA14_CURR_ADDR 0xFFC070AC /* DMA14 Current Address */ 1825 #define DMA14_CURR_X_COUNT 0xFFC070B4 /* DMA14 Current Count(1D) or intra-row XCNT (2D) */ 1826 #define DMA14_CURR_Y_COUNT 0xFFC070B8 /* DMA14 Current Row Count (2D only) */ 1828 #define DMA14_CURR_BWL_COUNT 0xFFC070C4 /* DMA14 Bandwidth Limit Count Current */ 1830 #define DMA14_CURR_BWM_COUNT 0xFFC070CC /* DMA14 Bandwidth Monitor Count Current */ 1836 #define DMA15_START_ADDR 0xFFC07104 /* DMA15 Start Address of Current Buffer */ 1842 #define DMA15_CURR_DESC_PTR 0xFFC07124 /* DMA15 Current Descriptor Pointer */ 1844 #define DMA15_CURR_ADDR 0xFFC0712C /* DMA15 Current Address */ 1846 #define DMA15_CURR_X_COUNT 0xFFC07134 /* DMA15 Current Count(1D) or intra-row XCNT (2D) */ 1847 #define DMA15_CURR_Y_COUNT 0xFFC07138 /* DMA15 Current Row Count (2D only) */ 1849 #define DMA15_CURR_BWL_COUNT 0xFFC07144 /* DMA15 Bandwidth Limit Count Current */ 1851 #define DMA15_CURR_BWM_COUNT 0xFFC0714C /* DMA15 Bandwidth Monitor Count Current */ 1857 #define DMA16_START_ADDR 0xFFC07184 /* DMA16 Start Address of Current Buffer */ 1863 #define DMA16_CURR_DESC_PTR 0xFFC071A4 /* DMA16 Current Descriptor Pointer */ 1865 #define DMA16_CURR_ADDR 0xFFC071AC /* DMA16 Current Address */ 1867 #define DMA16_CURR_X_COUNT 0xFFC071B4 /* DMA16 Current Count(1D) or intra-row XCNT (2D) */ 1868 #define DMA16_CURR_Y_COUNT 0xFFC071B8 /* DMA16 Current Row Count (2D only) */ 1870 #define DMA16_CURR_BWL_COUNT 0xFFC071C4 /* DMA16 Bandwidth Limit Count Current */ 1872 #define DMA16_CURR_BWM_COUNT 0xFFC071CC /* DMA16 Bandwidth Monitor Count Current */ 1878 #define DMA17_START_ADDR 0xFFC07204 /* DMA17 Start Address of Current Buffer */ 1884 #define DMA17_CURR_DESC_PTR 0xFFC07224 /* DMA17 Current Descriptor Pointer */ 1886 #define DMA17_CURR_ADDR 0xFFC0722C /* DMA17 Current Address */ 1888 #define DMA17_CURR_X_COUNT 0xFFC07234 /* DMA17 Current Count(1D) or intra-row XCNT (2D) */ 1889 #define DMA17_CURR_Y_COUNT 0xFFC07238 /* DMA17 Current Row Count (2D only) */ 1891 #define DMA17_CURR_BWL_COUNT 0xFFC07244 /* DMA17 Bandwidth Limit Count Current */ 1893 #define DMA17_CURR_BWM_COUNT 0xFFC0724C /* DMA17 Bandwidth Monitor Count Current */ 1899 #define DMA18_START_ADDR 0xFFC07284 /* DMA18 Start Address of Current Buffer */ 1905 #define DMA18_CURR_DESC_PTR 0xFFC072A4 /* DMA18 Current Descriptor Pointer */ 1907 #define DMA18_CURR_ADDR 0xFFC072AC /* DMA18 Current Address */ 1909 #define DMA18_CURR_X_COUNT 0xFFC072B4 /* DMA18 Current Count(1D) or intra-row XCNT (2D) */ 1910 #define DMA18_CURR_Y_COUNT 0xFFC072B8 /* DMA18 Current Row Count (2D only) */ 1912 #define DMA18_CURR_BWL_COUNT 0xFFC072C4 /* DMA18 Bandwidth Limit Count Current */ 1914 #define DMA18_CURR_BWM_COUNT 0xFFC072CC /* DMA18 Bandwidth Monitor Count Current */ 1920 #define DMA19_START_ADDR 0xFFC07304 /* DMA19 Start Address of Current Buffer */ 1926 #define DMA19_CURR_DESC_PTR 0xFFC07324 /* DMA19 Current Descriptor Pointer */ 1928 #define DMA19_CURR_ADDR 0xFFC0732C /* DMA19 Current Address */ 1930 #define DMA19_CURR_X_COUNT 0xFFC07334 /* DMA19 Current Count(1D) or intra-row XCNT (2D) */ 1931 #define DMA19_CURR_Y_COUNT 0xFFC07338 /* DMA19 Current Row Count (2D only) */ 1933 #define DMA19_CURR_BWL_COUNT 0xFFC07344 /* DMA19 Bandwidth Limit Count Current */ 1935 #define DMA19_CURR_BWM_COUNT 0xFFC0734C /* DMA19 Bandwidth Monitor Count Current */ 1941 #define DMA20_START_ADDR 0xFFC07384 /* DMA20 Start Address of Current Buffer */ 1947 #define DMA20_CURR_DESC_PTR 0xFFC073A4 /* DMA20 Current Descriptor Pointer */ 1949 #define DMA20_CURR_ADDR 0xFFC073AC /* DMA20 Current Address */ 1951 #define DMA20_CURR_X_COUNT 0xFFC073B4 /* DMA20 Current Count(1D) or intra-row XCNT (2D) */ 1952 #define DMA20_CURR_Y_COUNT 0xFFC073B8 /* DMA20 Current Row Count (2D only) */ 1954 #define DMA20_CURR_BWL_COUNT 0xFFC073C4 /* DMA20 Bandwidth Limit Count Current */ 1956 #define DMA20_CURR_BWM_COUNT 0xFFC073CC /* DMA20 Bandwidth Monitor Count Current */ 1962 #define DMA21_START_ADDR 0xFFC09004 /* DMA21 Start Address of Current Buffer */ 1968 #define DMA21_CURR_DESC_PTR 0xFFC09024 /* DMA21 Current Descriptor Pointer */ 1970 #define DMA21_CURR_ADDR 0xFFC0902C /* DMA21 Current Address */ 1972 #define DMA21_CURR_X_COUNT 0xFFC09034 /* DMA21 Current Count(1D) or intra-row XCNT (2D) */ 1973 #define DMA21_CURR_Y_COUNT 0xFFC09038 /* DMA21 Current Row Count (2D only) */ 1975 #define DMA21_CURR_BWL_COUNT 0xFFC09044 /* DMA21 Bandwidth Limit Count Current */ 1977 #define DMA21_CURR_BWM_COUNT 0xFFC0904C /* DMA21 Bandwidth Monitor Count Current */ 1983 #define DMA22_START_ADDR 0xFFC09084 /* DMA22 Start Address of Current Buffer */ 1989 #define DMA22_CURR_DESC_PTR 0xFFC090A4 /* DMA22 Current Descriptor Pointer */ 1991 #define DMA22_CURR_ADDR 0xFFC090AC /* DMA22 Current Address */ 1993 #define DMA22_CURR_X_COUNT 0xFFC090B4 /* DMA22 Current Count(1D) or intra-row XCNT (2D) */ 1994 #define DMA22_CURR_Y_COUNT 0xFFC090B8 /* DMA22 Current Row Count (2D only) */ 1996 #define DMA22_CURR_BWL_COUNT 0xFFC090C4 /* DMA22 Bandwidth Limit Count Current */ 1998 #define DMA22_CURR_BWM_COUNT 0xFFC090CC /* DMA22 Bandwidth Monitor Count Current */ 2004 #define DMA23_START_ADDR 0xFFC09104 /* DMA23 Start Address of Current Buffer */ 2010 #define DMA23_CURR_DESC_PTR 0xFFC09124 /* DMA23 Current Descriptor Pointer */ 2012 #define DMA23_CURR_ADDR 0xFFC0912C /* DMA23 Current Address */ 2014 #define DMA23_CURR_X_COUNT 0xFFC09134 /* DMA23 Current Count(1D) or intra-row XCNT (2D) */ 2015 #define DMA23_CURR_Y_COUNT 0xFFC09138 /* DMA23 Current Row Count (2D only) */ 2017 #define DMA23_CURR_BWL_COUNT 0xFFC09144 /* DMA23 Bandwidth Limit Count Current */ 2019 #define DMA23_CURR_BWM_COUNT 0xFFC0914C /* DMA23 Bandwidth Monitor Count Current */ 2025 #define DMA24_START_ADDR 0xFFC09184 /* DMA24 Start Address of Current Buffer */ 2031 #define DMA24_CURR_DESC_PTR 0xFFC091A4 /* DMA24 Current Descriptor Pointer */ 2033 #define DMA24_CURR_ADDR 0xFFC091AC /* DMA24 Current Address */ 2035 #define DMA24_CURR_X_COUNT 0xFFC091B4 /* DMA24 Current Count(1D) or intra-row XCNT (2D) */ 2036 #define DMA24_CURR_Y_COUNT 0xFFC091B8 /* DMA24 Current Row Count (2D only) */ 2038 #define DMA24_CURR_BWL_COUNT 0xFFC091C4 /* DMA24 Bandwidth Limit Count Current */ 2040 #define DMA24_CURR_BWM_COUNT 0xFFC091CC /* DMA24 Bandwidth Monitor Count Current */ 2046 #define DMA25_START_ADDR 0xFFC09204 /* DMA25 Start Address of Current Buffer */ 2052 #define DMA25_CURR_DESC_PTR 0xFFC09224 /* DMA25 Current Descriptor Pointer */ 2054 #define DMA25_CURR_ADDR 0xFFC0922C /* DMA25 Current Address */ 2056 #define DMA25_CURR_X_COUNT 0xFFC09234 /* DMA25 Current Count(1D) or intra-row XCNT (2D) */ 2057 #define DMA25_CURR_Y_COUNT 0xFFC09238 /* DMA25 Current Row Count (2D only) */ 2059 #define DMA25_CURR_BWL_COUNT 0xFFC09244 /* DMA25 Bandwidth Limit Count Current */ 2061 #define DMA25_CURR_BWM_COUNT 0xFFC0924C /* DMA25 Bandwidth Monitor Count Current */ 2067 #define DMA26_START_ADDR 0xFFC09284 /* DMA26 Start Address of Current Buffer */ 2073 #define DMA26_CURR_DESC_PTR 0xFFC092A4 /* DMA26 Current Descriptor Pointer */ 2075 #define DMA26_CURR_ADDR 0xFFC092AC /* DMA26 Current Address */ 2077 #define DMA26_CURR_X_COUNT 0xFFC092B4 /* DMA26 Current Count(1D) or intra-row XCNT (2D) */ 2078 #define DMA26_CURR_Y_COUNT 0xFFC092B8 /* DMA26 Current Row Count (2D only) */ 2080 #define DMA26_CURR_BWL_COUNT 0xFFC092C4 /* DMA26 Bandwidth Limit Count Current */ 2082 #define DMA26_CURR_BWM_COUNT 0xFFC092CC /* DMA26 Bandwidth Monitor Count Current */ 2088 #define DMA27_START_ADDR 0xFFC09304 /* DMA27 Start Address of Current Buffer */ 2094 #define DMA27_CURR_DESC_PTR 0xFFC09324 /* DMA27 Current Descriptor Pointer */ 2096 #define DMA27_CURR_ADDR 0xFFC0932C /* DMA27 Current Address */ 2098 #define DMA27_CURR_X_COUNT 0xFFC09334 /* DMA27 Current Count(1D) or intra-row XCNT (2D) */ 2099 #define DMA27_CURR_Y_COUNT 0xFFC09338 /* DMA27 Current Row Count (2D only) */ 2101 #define DMA27_CURR_BWL_COUNT 0xFFC09344 /* DMA27 Bandwidth Limit Count Current */ 2103 #define DMA27_CURR_BWM_COUNT 0xFFC0934C /* DMA27 Bandwidth Monitor Count Current */ 2109 #define DMA28_START_ADDR 0xFFC09384 /* DMA28 Start Address of Current Buffer */ 2115 #define DMA28_CURR_DESC_PTR 0xFFC093A4 /* DMA28 Current Descriptor Pointer */ 2117 #define DMA28_CURR_ADDR 0xFFC093AC /* DMA28 Current Address */ 2119 #define DMA28_CURR_X_COUNT 0xFFC093B4 /* DMA28 Current Count(1D) or intra-row XCNT (2D) */ 2120 #define DMA28_CURR_Y_COUNT 0xFFC093B8 /* DMA28 Current Row Count (2D only) */ 2122 #define DMA28_CURR_BWL_COUNT 0xFFC093C4 /* DMA28 Bandwidth Limit Count Current */ 2124 #define DMA28_CURR_BWM_COUNT 0xFFC093CC /* DMA28 Bandwidth Monitor Count Current */ 2130 #define DMA29_START_ADDR 0xFFC0B004 /* DMA29 Start Address of Current Buffer */ 2136 #define DMA29_CURR_DESC_PTR 0xFFC0B024 /* DMA29 Current Descriptor Pointer */ 2138 #define DMA29_CURR_ADDR 0xFFC0B02C /* DMA29 Current Address */ 2140 #define DMA29_CURR_X_COUNT 0xFFC0B034 /* DMA29 Current Count(1D) or intra-row XCNT (2D) */ 2141 #define DMA29_CURR_Y_COUNT 0xFFC0B038 /* DMA29 Current Row Count (2D only) */ 2143 #define DMA29_CURR_BWL_COUNT 0xFFC0B044 /* DMA29 Bandwidth Limit Count Current */ 2145 #define DMA29_CURR_BWM_COUNT 0xFFC0B04C /* DMA29 Bandwidth Monitor Count Current */ 2151 #define DMA30_START_ADDR 0xFFC0B084 /* DMA30 Start Address of Current Buffer */ 2157 #define DMA30_CURR_DESC_PTR 0xFFC0B0A4 /* DMA30 Current Descriptor Pointer */ 2159 #define DMA30_CURR_ADDR 0xFFC0B0AC /* DMA30 Current Address */ 2161 #define DMA30_CURR_X_COUNT 0xFFC0B0B4 /* DMA30 Current Count(1D) or intra-row XCNT (2D) */ 2162 #define DMA30_CURR_Y_COUNT 0xFFC0B0B8 /* DMA30 Current Row Count (2D only) */ 2164 #define DMA30_CURR_BWL_COUNT 0xFFC0B0C4 /* DMA30 Bandwidth Limit Count Current */ 2166 #define DMA30_CURR_BWM_COUNT 0xFFC0B0CC /* DMA30 Bandwidth Monitor Count Current */ 2172 #define DMA31_START_ADDR 0xFFC0B104 /* DMA31 Start Address of Current Buffer */ 2178 #define DMA31_CURR_DESC_PTR 0xFFC0B124 /* DMA31 Current Descriptor Pointer */ 2180 #define DMA31_CURR_ADDR 0xFFC0B12C /* DMA31 Current Address */ 2182 #define DMA31_CURR_X_COUNT 0xFFC0B134 /* DMA31 Current Count(1D) or intra-row XCNT (2D) */ 2183 #define DMA31_CURR_Y_COUNT 0xFFC0B138 /* DMA31 Current Row Count (2D only) */ 2185 #define DMA31_CURR_BWL_COUNT 0xFFC0B144 /* DMA31 Bandwidth Limit Count Current */ 2187 #define DMA31_CURR_BWM_COUNT 0xFFC0B14C /* DMA31 Bandwidth Monitor Count Current */ 2193 #define DMA32_START_ADDR 0xFFC0B184 /* DMA32 Start Address of Current Buffer */ 2199 #define DMA32_CURR_DESC_PTR 0xFFC0B1A4 /* DMA32 Current Descriptor Pointer */ 2201 #define DMA32_CURR_ADDR 0xFFC0B1AC /* DMA32 Current Address */ 2203 #define DMA32_CURR_X_COUNT 0xFFC0B1B4 /* DMA32 Current Count(1D) or intra-row XCNT (2D) */ 2204 #define DMA32_CURR_Y_COUNT 0xFFC0B1B8 /* DMA32 Current Row Count (2D only) */ 2206 #define DMA32_CURR_BWL_COUNT 0xFFC0B1C4 /* DMA32 Bandwidth Limit Count Current */ 2208 #define DMA32_CURR_BWM_COUNT 0xFFC0B1CC /* DMA32 Bandwidth Monitor Count Current */ 2214 #define DMA33_START_ADDR 0xFFC0D004 /* DMA33 Start Address of Current Buffer */ 2220 #define DMA33_CURR_DESC_PTR 0xFFC0D024 /* DMA33 Current Descriptor Pointer */ 2222 #define DMA33_CURR_ADDR 0xFFC0D02C /* DMA33 Current Address */ 2224 #define DMA33_CURR_X_COUNT 0xFFC0D034 /* DMA33 Current Count(1D) or intra-row XCNT (2D) */ 2225 #define DMA33_CURR_Y_COUNT 0xFFC0D038 /* DMA33 Current Row Count (2D only) */ 2227 #define DMA33_CURR_BWL_COUNT 0xFFC0D044 /* DMA33 Bandwidth Limit Count Current */ 2229 #define DMA33_CURR_BWM_COUNT 0xFFC0D04C /* DMA33 Bandwidth Monitor Count Current */ 2235 #define DMA34_START_ADDR 0xFFC0D084 /* DMA34 Start Address of Current Buffer */ 2241 #define DMA34_CURR_DESC_PTR 0xFFC0D0A4 /* DMA34 Current Descriptor Pointer */ 2243 #define DMA34_CURR_ADDR 0xFFC0D0AC /* DMA34 Current Address */ 2245 #define DMA34_CURR_X_COUNT 0xFFC0D0B4 /* DMA34 Current Count(1D) or intra-row XCNT (2D) */ 2246 #define DMA34_CURR_Y_COUNT 0xFFC0D0B8 /* DMA34 Current Row Count (2D only) */ 2248 #define DMA34_CURR_BWL_COUNT 0xFFC0D0C4 /* DMA34 Bandwidth Limit Count Current */ 2250 #define DMA34_CURR_BWM_COUNT 0xFFC0D0CC /* DMA34 Bandwidth Monitor Count Current */ 2256 #define DMA35_START_ADDR 0xFFC10004 /* DMA35 Start Address of Current Buffer */ 2262 #define DMA35_CURR_DESC_PTR 0xFFC10024 /* DMA35 Current Descriptor Pointer */ 2264 #define DMA35_CURR_ADDR 0xFFC1002C /* DMA35 Current Address */ 2266 #define DMA35_CURR_X_COUNT 0xFFC10034 /* DMA35 Current Count(1D) or intra-row XCNT (2D) */ 2267 #define DMA35_CURR_Y_COUNT 0xFFC10038 /* DMA35 Current Row Count (2D only) */ 2269 #define DMA35_CURR_BWL_COUNT 0xFFC10044 /* DMA35 Bandwidth Limit Count Current */ 2271 #define DMA35_CURR_BWM_COUNT 0xFFC1004C /* DMA35 Bandwidth Monitor Count Current */ 2277 #define DMA36_START_ADDR 0xFFC10084 /* DMA36 Start Address of Current Buffer */ 2283 #define DMA36_CURR_DESC_PTR 0xFFC100A4 /* DMA36 Current Descriptor Pointer */ 2285 #define DMA36_CURR_ADDR 0xFFC100AC /* DMA36 Current Address */ 2287 #define DMA36_CURR_X_COUNT 0xFFC100B4 /* DMA36 Current Count(1D) or intra-row XCNT (2D) */ 2288 #define DMA36_CURR_Y_COUNT 0xFFC100B8 /* DMA36 Current Row Count (2D only) */ 2290 #define DMA36_CURR_BWL_COUNT 0xFFC100C4 /* DMA36 Bandwidth Limit Count Current */ 2292 #define DMA36_CURR_BWM_COUNT 0xFFC100CC /* DMA36 Bandwidth Monitor Count Current */ 2298 #define DMA37_START_ADDR 0xFFC10104 /* DMA37 Start Address of Current Buffer */ 2304 #define DMA37_CURR_DESC_PTR 0xFFC10124 /* DMA37 Current Descriptor Pointer */ 2306 #define DMA37_CURR_ADDR 0xFFC1012C /* DMA37 Current Address */ 2308 #define DMA37_CURR_X_COUNT 0xFFC10134 /* DMA37 Current Count(1D) or intra-row XCNT (2D) */ 2309 #define DMA37_CURR_Y_COUNT 0xFFC10138 /* DMA37 Current Row Count (2D only) */ 2311 #define DMA37_CURR_BWL_COUNT 0xFFC10144 /* DMA37 Bandwidth Limit Count Current */ 2313 #define DMA37_CURR_BWM_COUNT 0xFFC1014C /* DMA37 Bandwidth Monitor Count Current */ 2319 #define DMA38_START_ADDR 0xFFC12004 /* DMA38 Start Address of Current Buffer */ 2325 #define DMA38_CURR_DESC_PTR 0xFFC12024 /* DMA38 Current Descriptor Pointer */ 2327 #define DMA38_CURR_ADDR 0xFFC1202C /* DMA38 Current Address */ 2329 #define DMA38_CURR_X_COUNT 0xFFC12034 /* DMA38 Current Count(1D) or intra-row XCNT (2D) */ 2330 #define DMA38_CURR_Y_COUNT 0xFFC12038 /* DMA38 Current Row Count (2D only) */ 2332 #define DMA38_CURR_BWL_COUNT 0xFFC12044 /* DMA38 Bandwidth Limit Count Current */ 2334 #define DMA38_CURR_BWM_COUNT 0xFFC1204C /* DMA38 Bandwidth Monitor Count Current */ 2340 #define DMA39_START_ADDR 0xFFC12084 /* DMA39 Start Address of Current Buffer */ 2346 #define DMA39_CURR_DESC_PTR 0xFFC120A4 /* DMA39 Current Descriptor Pointer */ 2348 #define DMA39_CURR_ADDR 0xFFC120AC /* DMA39 Current Address */ 2350 #define DMA39_CURR_X_COUNT 0xFFC120B4 /* DMA39 Current Count(1D) or intra-row XCNT (2D) */ 2351 #define DMA39_CURR_Y_COUNT 0xFFC120B8 /* DMA39 Current Row Count (2D only) */ 2353 #define DMA39_CURR_BWL_COUNT 0xFFC120C4 /* DMA39 Bandwidth Limit Count Current */ 2355 #define DMA39_CURR_BWM_COUNT 0xFFC120CC /* DMA39 Bandwidth Monitor Count Current */ 2361 #define DMA40_START_ADDR 0xFFC12104 /* DMA40 Start Address of Current Buffer */ 2367 #define DMA40_CURR_DESC_PTR 0xFFC12124 /* DMA40 Current Descriptor Pointer */ 2369 #define DMA40_CURR_ADDR 0xFFC1212C /* DMA40 Current Address */ 2371 #define DMA40_CURR_X_COUNT 0xFFC12134 /* DMA40 Current Count(1D) or intra-row XCNT (2D) */ 2372 #define DMA40_CURR_Y_COUNT 0xFFC12138 /* DMA40 Current Row Count (2D only) */ 2374 #define DMA40_CURR_BWL_COUNT 0xFFC12144 /* DMA40 Bandwidth Limit Count Current */ 2376 #define DMA40_CURR_BWM_COUNT 0xFFC1214C /* DMA40 Bandwidth Monitor Count Current */ 2382 #define DMA41_START_ADDR 0xFFC12184 /* DMA41 Start Address of Current Buffer */ 2388 #define DMA41_CURR_DESC_PTR 0xFFC121A4 /* DMA41 Current Descriptor Pointer */ 2390 #define DMA41_CURR_ADDR 0xFFC121AC /* DMA41 Current Address */ 2392 #define DMA41_CURR_X_COUNT 0xFFC121B4 /* DMA41 Current Count(1D) or intra-row XCNT (2D) */ 2393 #define DMA41_CURR_Y_COUNT 0xFFC121B8 /* DMA41 Current Row Count (2D only) */ 2395 #define DMA41_CURR_BWL_COUNT 0xFFC121C4 /* DMA41 Bandwidth Limit Count Current */ 2397 #define DMA41_CURR_BWM_COUNT 0xFFC121CC /* DMA41 Bandwidth Monitor Count Current */ 2403 #define DMA42_START_ADDR 0xFFC14004 /* DMA42 Start Address of Current Buffer */ 2409 #define DMA42_CURR_DESC_PTR 0xFFC14024 /* DMA42 Current Descriptor Pointer */ 2411 #define DMA42_CURR_ADDR 0xFFC1402C /* DMA42 Current Address */ 2413 #define DMA42_CURR_X_COUNT 0xFFC14034 /* DMA42 Current Count(1D) or intra-row XCNT (2D) */ 2414 #define DMA42_CURR_Y_COUNT 0xFFC14038 /* DMA42 Current Row Count (2D only) */ 2416 #define DMA42_CURR_BWL_COUNT 0xFFC14044 /* DMA42 Bandwidth Limit Count Current */ 2418 #define DMA42_CURR_BWM_COUNT 0xFFC1404C /* DMA42 Bandwidth Monitor Count Current */ 2424 #define DMA43_START_ADDR 0xFFC14084 /* DMA43 Start Address of Current Buffer */ 2430 #define DMA43_CURR_DESC_PTR 0xFFC140A4 /* DMA43 Current Descriptor Pointer */ 2432 #define DMA43_CURR_ADDR 0xFFC140AC /* DMA43 Current Address */ 2434 #define DMA43_CURR_X_COUNT 0xFFC140B4 /* DMA43 Current Count(1D) or intra-row XCNT (2D) */ 2435 #define DMA43_CURR_Y_COUNT 0xFFC140B8 /* DMA43 Current Row Count (2D only) */ 2437 #define DMA43_CURR_BWL_COUNT 0xFFC140C4 /* DMA43 Bandwidth Limit Count Current */ 2439 #define DMA43_CURR_BWM_COUNT 0xFFC140CC /* DMA43 Bandwidth Monitor Count Current */ 2445 #define DMA44_START_ADDR 0xFFC14104 /* DMA44 Start Address of Current Buffer */ 2451 #define DMA44_CURR_DESC_PTR 0xFFC14124 /* DMA44 Current Descriptor Pointer */ 2453 #define DMA44_CURR_ADDR 0xFFC1412C /* DMA44 Current Address */ 2455 #define DMA44_CURR_X_COUNT 0xFFC14134 /* DMA44 Current Count(1D) or intra-row XCNT (2D) */ 2456 #define DMA44_CURR_Y_COUNT 0xFFC14138 /* DMA44 Current Row Count (2D only) */ 2458 #define DMA44_CURR_BWL_COUNT 0xFFC14144 /* DMA44 Bandwidth Limit Count Current */ 2460 #define DMA44_CURR_BWM_COUNT 0xFFC1414C /* DMA44 Bandwidth Monitor Count Current */ 2466 #define DMA45_START_ADDR 0xFFC14184 /* DMA45 Start Address of Current Buffer */ 2472 #define DMA45_CURR_DESC_PTR 0xFFC141A4 /* DMA45 Current Descriptor Pointer */ 2474 #define DMA45_CURR_ADDR 0xFFC141AC /* DMA45 Current Address */ 2476 #define DMA45_CURR_X_COUNT 0xFFC141B4 /* DMA45 Current Count(1D) or intra-row XCNT (2D) */ 2477 #define DMA45_CURR_Y_COUNT 0xFFC141B8 /* DMA45 Current Row Count (2D only) */ 2479 #define DMA45_CURR_BWL_COUNT 0xFFC141C4 /* DMA45 Bandwidth Limit Count Current */ 2481 #define DMA45_CURR_BWM_COUNT 0xFFC141CC /* DMA45 Bandwidth Monitor Count Current */ 2487 #define DMA46_START_ADDR 0xFFC14204 /* DMA46 Start Address of Current Buffer */ 2493 #define DMA46_CURR_DESC_PTR 0xFFC14224 /* DMA46 Current Descriptor Pointer */ 2495 #define DMA46_CURR_ADDR 0xFFC1422C /* DMA46 Current Address */ 2497 #define DMA46_CURR_X_COUNT 0xFFC14234 /* DMA46 Current Count(1D) or intra-row XCNT (2D) */ 2498 #define DMA46_CURR_Y_COUNT 0xFFC14238 /* DMA46 Current Row Count (2D only) */ 2500 #define DMA46_CURR_BWL_COUNT 0xFFC14244 /* DMA46 Bandwidth Limit Count Current */ 2502 #define DMA46_CURR_BWM_COUNT 0xFFC1424C /* DMA46 Bandwidth Monitor Count Current */ 2737 #define SEC_FDLY_CUR 0xFFCA4024 /* SEC Fault Delay Current Register */ 2739 #define SEC_FSRDLY_CUR 0xFFCA402C /* SEC Fault System Reset Delay Current Register */ 2741 #define SEC_FCOPP_CUR 0xFFCA4034 /* SEC Fault COP Period Current Register */
/linux-4.1.27/arch/blackfin/include/asm/
H A D	dma.h	102 void *curr_desc_ptr; /* DMA Current Descriptor Pointer 106 unsigned long curr_addr_ptr; /* DMA Current Address Pointer 110 unsigned long curr_x_count; /* DMA Current x-count register */ 112 unsigned long curr_y_count; /* DMA Current y-count register */ 117 unsigned long curr_bw_limit_count; /* DMA Current band width limit 120 unsigned long curr_bw_monitor_count; /* DMA Current band width limit 140 void *curr_desc_ptr; /* DMA Current Descriptor Pointer 142 unsigned long curr_addr_ptr; /* DMA Current Address Pointer 150 unsigned short curr_x_count; /* DMA Current x-count register */ 155 unsigned short curr_y_count; /* DMA Current y-count register */
H A D	pda.h	22 unsigned long imask; /* Current IMASK value */
H A D	bfin_sport3.h	68 #define SPORT_CNT_CLKCNT 0x0000FFFF /* Current state of clk div counter */ 69 #define SPORT_CNT_FSDIVCNT 0xFFFF0000 /* Current state of frame div counter */
/linux-4.1.27/include/uapi/linux/
H A D	v4l2-common.h	40 /* Current cropping area */ 48 /* Current composing area */ 54 /* Current composing area plus all padding pixels */
H A D	elfcore.h	44 short pr_cursig; /* Current signal */ 60 long pr_instr; /* Current instruction */
H A D	filter.h	13 * Current version of the filter code architecture.
H A D	pci_regs.h	243 #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */ 494 #define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */ 495 #define PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */ 496 #define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */ 497 #define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */ 499 #define PCI_EXP_LNKSTA_NLW_X1 0x0010 /* Current Link Width x1 */ 500 #define PCI_EXP_LNKSTA_NLW_X2 0x0020 /* Current Link Width x2 */ 501 #define PCI_EXP_LNKSTA_NLW_X4 0x0040 /* Current Link Width x4 */ 502 #define PCI_EXP_LNKSTA_NLW_X8 0x0080 /* Current Link Width x8 */
/linux-4.1.27/drivers/ide/
H A D	ide-gd.h	32 /* Current format */
H A D	ide-cd.h	91 u8 current_speed; /* Current speed of the drive. */
/linux-4.1.27/arch/mn10300/include/asm/
H A D	current.h	1 /* MN10300 Current task structure accessor
/linux-4.1.27/arch/m68k/include/asm/
H A D	mcfslt.h	20 #define MCFSLT_SCNT 0x08 /* Current count */
H A D	machines.h	16 /* Current number of machines we know about that has an IDPROM
/linux-4.1.27/tools/perf/util/
H A D	probe-finder.h	72 Dwarf_Die cu_die; /* Current CU */ 81 struct perf_probe_arg *pvar; /* Current target variable */ 82 struct probe_trace_arg *tvar; /* Current result variable */ 109 Dwarf_Die cu_die; /* Current CU */
/linux-4.1.27/drivers/media/radio/wl128x/
H A D	fmdrv.h	138 * Current RX channel Alternate Frequency cache. 151 struct region_info region; /* Current selected band */ 152 u32 freq; /* Current RX frquency */ 153 u8 mute_mode; /* Current mute mode */ 154 u8 deemphasis_mode; /* Current deemphasis mode */ 157 u16 volume; /* Current volume level */ 158 u16 rssi_threshold; /* Current RSSI threshold level */ 231 u8 curr_fmmode; /* Current FM chip mode (TX, RX, OFF) */
/linux-4.1.27/drivers/staging/olpc_dcon/
H A D	olpc_dcon.h	74 /* Current source, initialized at probe time */ 85 /* Current output type; true == mono, false == color */
/linux-4.1.27/include/linux/mfd/syscon/
H A D	atmel-st.h	46 #define AT91_ST_CRTR 0x24 /* Current Real-time Register */ 47 #define AT91_ST_CRTV 0xfffff /* Current Real-Time Value */
/linux-4.1.27/drivers/net/ethernet/amd/
H A D	ariadne.h	78 #define CSR18 0x1200 /* Current Receive Buffer Address */ 79 #define CSR19 0x1300 /* Current Receive Buffer Address */ 80 #define CSR20 0x1400 /* Current Transmit Buffer Address */ 81 #define CSR21 0x1500 /* Current Transmit Buffer Address */ 88 #define CSR28 0x1c00 /* Current Receive Descriptor Address */ 89 #define CSR29 0x1d00 /* Current Receive Descriptor Address */ 94 #define CSR34 0x2200 /* Current Transmit Descriptor Address */ 95 #define CSR35 0x2300 /* Current Transmit Descriptor Address */ 100 #define CSR40 0x2800 /* Current Receive Status and Byte Count */ 101 #define CSR41 0x2900 /* Current Receive Status and Byte Count */ 102 #define CSR42 0x2a00 /* Current Transmit Status and Byte Count */ 103 #define CSR43 0x2b00 /* Current Transmit Status and Byte Count */ 274 #define LEDOUT 0x0080 /* Current LED Status */
/linux-4.1.27/arch/blackfin/mach-bf533/include/mach/
H A D	defBF532.h	133 #define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ 157 #define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ 183 #define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ 193 #define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ 194 #define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ 195 #define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ 196 #define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ 207 #define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ 208 #define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ 209 #define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ 210 #define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ 221 #define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ 222 #define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ 223 #define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ 224 #define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ 235 #define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ 236 #define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ 237 #define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ 238 #define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ 249 #define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ 250 #define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ 251 #define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ 252 #define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ 263 #define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ 264 #define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ 265 #define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ 266 #define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ 277 #define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ 278 #define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ 279 #define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ 280 #define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ 291 #define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ 292 #define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ 293 #define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ 294 #define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ 305 #define MDMA_D1_CURR_DESC_PTR 0xFFC00EA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */ 306 #define MDMA_D1_CURR_ADDR 0xFFC00EA4 /* MemDMA Stream 1 Destination Current Address Register */ 307 #define MDMA_D1_CURR_X_COUNT 0xFFC00EB0 /* MemDMA Stream 1 Destination Current X Count Register */ 308 #define MDMA_D1_CURR_Y_COUNT 0xFFC00EB8 /* MemDMA Stream 1 Destination Current Y Count Register */ 319 #define MDMA_S1_CURR_DESC_PTR 0xFFC00EE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */ 320 #define MDMA_S1_CURR_ADDR 0xFFC00EE4 /* MemDMA Stream 1 Source Current Address Register */ 321 #define MDMA_S1_CURR_X_COUNT 0xFFC00EF0 /* MemDMA Stream 1 Source Current X Count Register */ 322 #define MDMA_S1_CURR_Y_COUNT 0xFFC00EF8 /* MemDMA Stream 1 Source Current Y Count Register */ 333 #define MDMA_D0_CURR_DESC_PTR 0xFFC00E20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */ 334 #define MDMA_D0_CURR_ADDR 0xFFC00E24 /* MemDMA Stream 0 Destination Current Address Register */ 335 #define MDMA_D0_CURR_X_COUNT 0xFFC00E30 /* MemDMA Stream 0 Destination Current X Count Register */ 336 #define MDMA_D0_CURR_Y_COUNT 0xFFC00E38 /* MemDMA Stream 0 Destination Current Y Count Register */ 347 #define MDMA_S0_CURR_DESC_PTR 0xFFC00E60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */ 348 #define MDMA_S0_CURR_ADDR 0xFFC00E64 /* MemDMA Stream 0 Source Current Address Register */ 349 #define MDMA_S0_CURR_X_COUNT 0xFFC00E70 /* MemDMA Stream 0 Source Current X Count Register */ 350 #define MDMA_S0_CURR_Y_COUNT 0xFFC00E78 /* MemDMA Stream 0 Source Current Y Count Register */
/linux-4.1.27/drivers/acpi/acpica/
H A D	psscope.c	55 * PARAMETERS: parser_state - Current parser state object 73 * PARAMETERS: parser_state - Current parser state object 95 * PARAMETERS: parser_state - Current parser state object 133 * PARAMETERS: parser_state - Current parser state object 134 * op - Current op to be pushed 186 * PARAMETERS: parser_state - Current parser state object 238 * PARAMETERS: parser_state - Current parser state object
H A D	dswstate.c	63 * walk_state - Current Walk state 137 * walk_state - Current Walk state 209 * PARAMETERS: walk_state - Current Walk state 254 * PARAMETERS: walk_state - Current Walk state 301 * walk_state - Current Walk state 347 * walk_state - Current Walk state 392 * walk_state - Current Walk state 455 ACPI_DEBUG_PRINT((ACPI_DB_PARSE, "Current WalkState %p\n", acpi_ds_get_current_walk_state() 490 * PARAMETERS: thread - Current thread state 531 * thread - Current thread state 585 * op - Current parse op 660 * search upwards from this Op. Current scope is the first acpi_ds_init_aml_walk()
H A D	dswscope.c	55 * PARAMETERS: walk_state - Current state 90 * walk_state - Current state 169 * PARAMETERS: walk_state - Current state
H A D	dsutils.c	60 * PARAMETERS: walk_state - Current State 102 * walk_state - Current State 160 * PARAMETERS: op - Current Op 161 * walk_state - Current State 325 * PARAMETERS: op - Current parse Op 327 * walk_state - Current state 374 * PARAMETERS: walk_state - Current walk state with operands on stack 412 * PARAMETERS: walk_state - Current walk state with operands on stack 446 * PARAMETERS: walk_state - Current walk state 699 * PARAMETERS: walk_state - Current state 781 * PARAMETERS: walk_state - Current state of the parse tree walk,
H A D	acstruct.h	75 u16 opcode; /* Current AML opcode */ 86 u8 result_count; /* Current number of occupied elements of result stack */ 93 struct acpi_parse_state parser_state; /* Current state of parser */ 111 union acpi_parse_object *op; /* Current parser op */
H A D	excreate.c	57 * PARAMETERS: walk_state - Current state, contains operands 159 * PARAMETERS: walk_state - Current state 209 * PARAMETERS: walk_state - Current state 267 * walk_state - Current state 362 * PARAMETERS: walk_state - Current state 409 * PARAMETERS: walk_state - Current state 458 * walk_state - Current state
H A D	psobject.c	59 * PARAMETERS: walk_state - Current state 158 * PARAMETERS: walk_state - Current state 266 * PARAMETERS: walk_state - Current state 374 * PARAMETERS: walk_state - Current state 547 * PARAMETERS: walk_state - Current state 548 * op - Current Op 549 * status - Current parse status before complete last
H A D	dsmthdat.c	74 * PARAMETERS: walk_state - Current walk state object 128 * PARAMETERS: walk_state - Current walk state object 182 * walk_state - Current walk state object 238 * walk_state - Current walk state object 304 * walk_state - Current walk state object 357 * walk_state - Current walk state object 464 * walk_state - Current walk state object 522 * walk_state - Current walk state 675 * walk_state - Current walk state object
H A D	exmutex.c	104 * thread - Current executing thread object 142 * thread_id - Current thread state 215 * walk_state - Current method execution state 246 * Current sync level must be less than or equal to the sync level of the acpi_ex_acquire_mutex() 347 * walk_state - Current method execution state 446 * PARAMETERS: thread - Current executing thread object
H A D	dsfield.c	79 * ` walk_state - Current method state 133 * PARAMETERS: op - Current parse op (create_XXField) 134 * walk_state - Current state 275 * ` walk_state - Current method state 464 * ` walk_state - Current method state 527 * ` walk_state - Current method state 647 * walk_state - Current method state 737 * ` walk_state - Current method state
H A D	psargs.c	65 * PARAMETERS: parser_state - Current parser state object 118 * PARAMETERS: parser_state - Current parser state object 145 * PARAMETERS: parser_state - Current parser state object 212 * PARAMETERS: parser_state - Current parser state object 380 * PARAMETERS: parser_state - Current parser state object 476 * PARAMETERS: parser_state - Current parser state object 698 * PARAMETERS: walk_state - Current state 699 * parser_state - Current parser state object
H A D	exstoren.c	58 * target_type - Current type of the target 59 * walk_state - Current walk state 161 * walk_state - Current walk state
H A D	dsopcode.c	288 * PARAMETERS: walk_state - Current walk 372 * PARAMETERS: walk_state - Current walk 463 * PARAMETERS: walk_state - Current walk 561 * PARAMETERS: walk_state - Current walk 665 * PARAMETERS: walk_state - Current walk
H A D	exresolv.c	66 * walk_state - Current method state 127 * walk_state - Current method state 322 * PARAMETERS: walk_state - Current state (contains AML opcode)
H A D	exoparg2.c	79 * PARAMETERS: walk_state - Current walk state 147 * PARAMETERS: walk_state - Current walk state 245 * PARAMETERS: walk_state - Current walk state 481 * PARAMETERS: walk_state - Current walk state
H A D	exstore.c	73 * walk_state - Current walk state 218 * walk_state - Current walk state 369 * walk_state - Current walk state 518 * walk_state - Current walk state
H A D	psparse.c	123 * PARAMETERS: walk_state - Current State 312 * PARAMETERS: walk_state - Current state 313 * op - Current parse op 426 * PARAMETERS: walk_state - Current state
H A D	exoparg3.c	78 * PARAMETERS: walk_state - Current walk state 147 * PARAMETERS: walk_state - Current walk state
H A D	dsobject.c	66 * PARAMETERS: walk_state - Current walk state 252 * PARAMETERS: walk_state - Current walk state 356 * PARAMETERS: walk_state - Current walk state 549 * PARAMETERS: walk_state - Current walk state 613 * PARAMETERS: walk_state - Current walk state
H A D	exoparg1.c	80 * PARAMETERS: walk_state - Current state (contains AML opcode) 138 * PARAMETERS: walk_state - Current state (contains AML opcode) 204 * PARAMETERS: walk_state - Current state (contains AML opcode) 246 * PARAMETERS: walk_state - Current state (contains AML opcode) 575 * PARAMETERS: walk_state - Current state (contains AML opcode)
H A D	aclocal.h	458 u8 enable_mask; /* Current mask of enabled GPEs */ 595 union acpi_parse_object *op; /* Current op being parsed */ 596 u8 *arg_end; /* Current argument end */ 597 u8 *pkg_end; /* Current package end */ 807 u8 *pkg_start; /* Current package begin */ 808 u8 *pkg_end; /* Current package end */ 811 union acpi_generic_state *scope; /* Current scope */
H A D	dswload.c	63 * PARAMETERS: walk_state - Current state of the parse tree walk 130 * PARAMETERS: walk_state - Current state of the parse tree walk 413 * PARAMETERS: walk_state - Current state of the parse tree walk
H A D	psloop.c	74 * PARAMETERS: walk_state - Current state 76 * op - Current Op 381 * PARAMETERS: walk_state - Current state
/linux-4.1.27/arch/blackfin/mach-bf518/include/mach/
H A D	defBF512.h	171 #define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ 195 #define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ 218 #define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ 228 #define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ 229 #define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ 232 #define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ 233 #define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ 242 #define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ 243 #define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ 246 #define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ 247 #define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ 256 #define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ 257 #define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ 260 #define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ 261 #define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ 270 #define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ 271 #define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ 274 #define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ 275 #define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ 284 #define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ 285 #define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ 288 #define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ 289 #define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ 298 #define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ 299 #define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ 302 #define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ 303 #define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ 312 #define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ 313 #define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ 316 #define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ 317 #define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ 326 #define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ 327 #define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ 330 #define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ 331 #define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ 340 #define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */ 341 #define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */ 344 #define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */ 345 #define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */ 354 #define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */ 355 #define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */ 358 #define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */ 359 #define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */ 368 #define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */ 369 #define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */ 372 #define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */ 373 #define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */ 382 #define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */ 383 #define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */ 386 #define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */ 387 #define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */ 396 #define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */ 397 #define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */ 400 #define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */ 401 #define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */ 410 #define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */ 411 #define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */ 414 #define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */ 415 #define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */ 424 #define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */ 425 #define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */ 428 #define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */ 429 #define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */ 438 #define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */ 439 #define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */ 442 #define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */ 443 #define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */ 542 #define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */ 543 #define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */ 550 #define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */ 551 #define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
/linux-4.1.27/arch/blackfin/mach-bf527/include/mach/
H A D	defBF522.h	168 #define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ 193 #define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ 218 #define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ 228 #define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ 229 #define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ 232 #define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ 233 #define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ 242 #define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ 243 #define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ 246 #define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ 247 #define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ 256 #define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ 257 #define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ 260 #define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ 261 #define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ 270 #define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ 271 #define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ 274 #define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ 275 #define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ 284 #define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ 285 #define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ 288 #define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ 289 #define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ 298 #define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ 299 #define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ 302 #define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ 303 #define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ 312 #define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ 313 #define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ 316 #define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ 317 #define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ 326 #define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ 327 #define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ 330 #define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ 331 #define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ 340 #define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */ 341 #define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */ 344 #define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */ 345 #define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */ 354 #define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */ 355 #define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */ 358 #define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */ 359 #define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */ 368 #define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */ 369 #define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */ 372 #define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */ 373 #define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */ 382 #define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */ 383 #define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */ 386 #define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */ 387 #define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */ 396 #define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */ 397 #define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */ 400 #define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */ 401 #define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */ 410 #define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */ 411 #define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */ 414 #define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */ 415 #define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */ 424 #define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */ 425 #define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */ 428 #define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */ 429 #define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */ 438 #define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */ 439 #define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */ 442 #define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */ 443 #define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */ 544 #define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */ 545 #define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */ 552 #define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */ 553 #define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
/linux-4.1.27/arch/blackfin/mach-bf537/include/mach/
H A D	defBF534.h	147 #define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ 171 #define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ 194 #define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ 204 #define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ 205 #define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ 208 #define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ 209 #define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ 218 #define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ 219 #define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ 222 #define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ 223 #define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ 232 #define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ 233 #define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ 236 #define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ 237 #define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ 246 #define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ 247 #define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ 250 #define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ 251 #define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ 260 #define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ 261 #define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ 264 #define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ 265 #define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ 274 #define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ 275 #define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ 278 #define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ 279 #define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ 288 #define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ 289 #define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ 292 #define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ 293 #define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ 302 #define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ 303 #define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ 306 #define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ 307 #define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ 316 #define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */ 317 #define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */ 320 #define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */ 321 #define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */ 330 #define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */ 331 #define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */ 334 #define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */ 335 #define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */ 344 #define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */ 345 #define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */ 348 #define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */ 349 #define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */ 358 #define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */ 359 #define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */ 362 #define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */ 363 #define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */ 372 #define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */ 373 #define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */ 376 #define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */ 377 #define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */ 386 #define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */ 387 #define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */ 390 #define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */ 391 #define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */ 400 #define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */ 401 #define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */ 404 #define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */ 405 #define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */ 414 #define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */ 415 #define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */ 418 #define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */ 419 #define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */ 932 #define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */ 933 #define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */ 940 #define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */ 941 #define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
/linux-4.1.27/drivers/media/pci/cx25821/
H A D	cx25821-reg.h	592 #define DMA1_PTR1 0x100000 /* DMA Current Ptr : Ch#1 */ 595 #define DMA2_PTR1 0x100004 /* DMA Current Ptr : Ch#2 */ 598 #define DMA3_PTR1 0x100008 /* DMA Current Ptr : Ch#3 */ 601 #define DMA4_PTR1 0x10000C /* DMA Current Ptr : Ch#4 */ 604 #define DMA5_PTR1 0x100010 /* DMA Current Ptr : Ch#5 */ 607 #define DMA6_PTR1 0x100014 /* DMA Current Ptr : Ch#6 */ 610 #define DMA7_PTR1 0x100018 /* DMA Current Ptr : Ch#7 */ 613 #define DMA8_PTR1 0x10001C /* DMA Current Ptr : Ch#8 */ 616 #define DMA9_PTR1 0x100020 /* DMA Current Ptr : Ch#9 */ 619 #define DMA10_PTR1 0x100024 /* DMA Current Ptr : Ch#10 */ 622 #define DMA11_PTR1 0x100028 /* DMA Current Ptr : Ch#11 */ 625 #define DMA12_PTR1 0x10002C /* DMA Current Ptr : Ch#12 */ 628 #define DMA13_PTR1 0x100030 /* DMA Current Ptr : Ch#13 */ 631 #define DMA14_PTR1 0x100034 /* DMA Current Ptr : Ch#14 */ 634 #define DMA15_PTR1 0x100038 /* DMA Current Ptr : Ch#15 */ 637 #define DMA16_PTR1 0x10003C /* DMA Current Ptr : Ch#16 */ 640 #define DMA17_PTR1 0x100040 /* DMA Current Ptr : Ch#17 */ 643 #define DMA18_PTR1 0x100044 /* DMA Current Ptr : Ch#18 */ 646 #define DMA19_PTR1 0x100048 /* DMA Current Ptr : Ch#19 */ 649 #define DMA20_PTR1 0x10004C /* DMA Current Ptr : Ch#20 */ 652 #define DMA21_PTR1 0x100050 /* DMA Current Ptr : Ch#21 */ 655 #define DMA22_PTR1 0x100054 /* DMA Current Ptr : Ch#22 */ 658 #define DMA23_PTR1 0x100058 /* DMA Current Ptr : Ch#23 */ 661 #define DMA24_PTR1 0x10005C /* DMA Current Ptr : Ch#24 */ 664 #define DMA25_PTR1 0x100060 /* DMA Current Ptr : Ch#25 */ 667 #define DMA26_PTR1 0x100064 /* DMA Current Ptr : Ch#26 */
/linux-4.1.27/drivers/mmc/host/
H A D	wbsd.h	151 struct mmc_request* mrq; /* Current request */ 155 struct scatterlist* cur_sg; /* Current SG entry */ 166 u8 clk; /* Current clock speed */ 167 unsigned char bus_width; /* Current bus width */
H A D	toshsd.h	169 struct mmc_request *mrq;/* Current request */ 170 struct mmc_command *cmd;/* Current command */ 171 struct mmc_data *data; /* Current data request */
H A D	sdhci.h	452 unsigned int clock; /* Current clock (MHz) */ 453 u8 pwr; /* Current voltage */ 459 struct mmc_request *mrq; /* Current request */ 460 struct mmc_command *cmd; /* Current command */ 461 struct mmc_data *data; /* Current data request */ 495 unsigned timing; /* Current timing */
/linux-4.1.27/drivers/regulator/
H A D	internal.h	2 * internal.h -- Voltage/Current Regulator framework internal code
H A D	da9063-regulator.c	41 /* Current limiting */ 138 /* Current limits array (in uA) for BCORE1, BCORE2, BPRO. 145 /* Current limits array (in uA) for BMEM, BIO, BPERI. 152 /* Current limits array (in uA) for merged BCORE1 and BCORE2. 159 /* Current limits array (in uA) for merged BMEM and BIO.
H A D	da9210-regulator.c	63 /* Current limits for buck (uA) indices corresponds with register values */
H A D	wm831x-isink.c	2 * wm831x-isink.c -- Current sink driver for the WM831x series
/linux-4.1.27/arch/tile/include/asm/
H A D	backtrace.h	29 /* Current PC. */ 32 /* Current stack pointer value. */ 35 /* Current frame pointer value (i.e. caller's stack pointer) */ 114 /* Current backtracer state describing where it thinks the caller is. */
/linux-4.1.27/drivers/usb/serial/
H A D	belkin_sa.h	118 #define BELKIN_SA_MSR_CTS 0x10 /* Current CTS */ 119 #define BELKIN_SA_MSR_DSR 0x20 /* Current DSR */ 120 #define BELKIN_SA_MSR_RI 0x40 /* Current RI */ 121 #define BELKIN_SA_MSR_CD 0x80 /* Current CD */
H A D	io_16654.h	149 #define EDGEPORT_MSR_CTS 0x10 // Current state of CTS 150 #define EDGEPORT_MSR_DSR 0x20 // Current state of DSR 151 #define EDGEPORT_MSR_RI 0x40 // Current state of RI 152 #define EDGEPORT_MSR_CD 0x80 // Current state of CD
/linux-4.1.27/arch/arm/include/asm/
H A D	neon.h	26 * (1) Current GCC (4.7) might generate NEON instructions at O3 level if
/linux-4.1.27/sound/soc/fsl/
H A D	fsl_dma.h	17 __be32 eclndar; /* Current link descriptor extended addr reg */ 18 __be32 clndar; /* Current link descriptor address register */ 27 __be32 eclsdar; /* Current list descriptor extended addr reg */ 28 __be32 clsdar; /* Current list descriptor address register */
/linux-4.1.27/drivers/net/wireless/b43/
H A D	lo.h	55 /* Current TX Bias value */ 57 /* Current TX Magnification Value (if used by the device) */
H A D	phy_g.h	142 /* Current idle TSSI */ 146 /* Current TX power level attenuation control values */ 164 /* Current Interference Mitigation mode */
H A D	phy_a.h	111 /* Current idle TSSI */
/linux-4.1.27/drivers/video/fbdev/
H A D	sa1100fb.h	16 #define DCAR1 0x0014 /* LCD DMA Current Address Reg. channel 1 */ 18 #define DCAR2 0x001C /* LCD DMA Current Address Reg. channel 2 */
/linux-4.1.27/net/dccp/ccids/lib/
H A D	loss_interval.h	42 * @counter: Current count of entries (can be more than %LIH_SIZE) 43 * @i_mean: Current Average Loss Interval [RFC 3448, 5.4]
/linux-4.1.27/drivers/staging/vt6655/
H A D	device.h	305 unsigned int uSIFS; /* Current SIFS */ 306 unsigned int uDIFS; /* Current DIFS */ 307 unsigned int uEIFS; /* Current EIFS */ 308 unsigned int uSlot; /* Current SlotTime */ 309 unsigned int uCwMin; /* Current CwMin */
H A D	card.c	30 * CARDbGetCurrentTSF - Read Current NIC TSF counter 915 * qwCurrTSF - Current TSF counter 945 * qwTSF - Current TSF counter 948 * qwCurrTSF - Current TSF counter 1000 * qwTSF - Current TSF counter
/linux-4.1.27/drivers/media/platform/davinci/
H A D	vpif_display.h	109 u32 output_idx; /* Current output index */ 110 struct v4l2_subdev *sd; /* Current output subdev(may be NULL) */
H A D	vpif_capture.h	102 /* Current input */
/linux-4.1.27/drivers/net/fddi/skfp/h/
H A D	sba.h	97 long msg_mib_pl ; /* Current Payload for this Path */ 98 long msg_mib_ov ; /* Current Overhead for this Path*/
H A D	smc.h	171 #define SNMP_PATH_ISOLATED 1 /* Current path is isolated */ 172 #define SNMP_PATH_LOCAL 2 /* Current path is local */ 173 #define SNMP_PATH_SECONDARY 3 /* Current path is secondary */ 174 #define SNMP_PATH_PRIMARY 4 /* Current path is primary */ 175 #define SNMP_PATH_CONCATENATED 5 /* Current path is concatenated */ 176 #define SNMP_PATH_THRU 6 /* Current path is thru */
/linux-4.1.27/include/linux/platform_data/
H A D	ad7793.h	56 * @AD7793_IEXEC1_IOUT1_IEXEC2_IOUT2: Current source IEXC1 connected to pin 58 * @AD7793_IEXEC1_IOUT2_IEXEC2_IOUT1: Current source IEXC2 connected to pin
H A D	mtd-nand-pxa3xx.h	32 * Current pxa3xx_nand controller has two chip select which
/linux-4.1.27/drivers/media/platform/am437x/
H A D	am437x-vpfe.h	154 /* Current Format Bytes Per Pixels */ 156 /* Current Format Bytes per Lines 183 /* Current Format Bytes Per Pixels */ 185 /* Current Format Bytes per Lines
/linux-4.1.27/drivers/net/wan/
H A D	hd64570.h	72 #define CST0 0x1C /* Current Status 0 */ 73 #define CST1 0x1D /* Current Status 1 */ 121 #define CDAL 0x08 /* Current Descriptor Addr L (chained block) */ 122 #define CDAH 0x09 /* Current Descriptor Addr H (chained block) */
H A D	hd64572.h	97 #define CST0 0x108 /* Current Status Register 0 */ 98 #define CST1 0x109 /* Current Status Register 1 */ 99 #define CST2 0x10a /* Current Status Register 2 */ 100 #define CST3 0x10b /* Current Status Register 3 */ 160 #define CDAL 0x84 /* Current Descriptor Addr Register L */ 161 #define CDAH 0x85 /* Current Descriptor Addr Register H */ 162 #define CDAB 0x86 /* Current Descriptor Addr Register B */ 163 #define CDABH 0x87 /* Current Descriptor Addr Register BH */
/linux-4.1.27/drivers/sbus/char/
H A D	bbc_i2c.h	24 /* Current readings, and history. */
/linux-4.1.27/drivers/staging/vt6656/
H A D	device.h	328 u32 sifs; /* Current SIFS */ 329 u32 difs; /* Current DIFS */ 330 u32 eifs; /* Current EIFS */ 331 u32 slot; /* Current SlotTime */
H A D	card.c	28 * vnt_get_current_tsf - Read Current NIC TSF counter 565 * current_tsf - Current TSF counter 605 * tsf - Current TSF counter 608 * tsf - Current TSF counter 674 * tsf - Current TSF counter
/linux-4.1.27/arch/mips/include/asm/mach-rc32434/
H A D	dma.h	24 u32 ca; /* Current Address. */
/linux-4.1.27/drivers/watchdog/
H A D	nv_tco.h	34 #define TCO_RLD(base) ((base) + 0x00) /* TCO Timer Reload and Current Value */
/linux-4.1.27/drivers/media/dvb-frontends/
H A D	stb0899_priv.h	171 u32 tuner_bw; /* Current bandwidth of the tuner (Hz) */ 174 s32 rolloff; /* Current RollOff of the filter (x100) */ 176 s16 derot_freq; /* Current derotator frequency (Hz) */ 179 s16 direction; /* Current derotator search direction */
/linux-4.1.27/include/linux/power/
H A D	max8903_charger.h	38 int dcm; /* Current-Limit Mode input (1: DC, 2: USB) */
/linux-4.1.27/lib/
H A D	average.c	50 * @val: Current value
/linux-4.1.27/include/drm/
H A D	drm_os_linux.h	22 /** Current process ID */
/linux-4.1.27/arch/powerpc/platforms/cell/
H A D	spider-pic.c	40 TIR_CS = 0x144, /* Current Status Register */ 41 TIR_LCSA = 0x150, /* Level Current Status Register A */ 42 TIR_LCSB = 0x154, /* Level Current Status Register B */ 43 TIR_LCSC = 0x158, /* Level Current Status Register C */ 44 TIR_LCSD = 0x15c, /* Level Current Status Register D */
/linux-4.1.27/drivers/video/backlight/
H A D	adp8860_bl.c	42 #define ADP8860_ISCT1 0x11 /* Independent Sink Current Timer Register LED[7:5] */ 43 #define ADP8860_ISCT2 0x12 /* Independent Sink Current Timer Register LED[4:1] */ 45 #define ADP8860_ISC7 0x14 /* Independent Sink Current LED7 */ 46 #define ADP8860_ISC6 0x15 /* Independent Sink Current LED6 */ 47 #define ADP8860_ISC5 0x16 /* Independent Sink Current LED5 */ 48 #define ADP8860_ISC4 0x17 /* Independent Sink Current LED4 */ 49 #define ADP8860_ISC3 0x18 /* Independent Sink Current LED3 */ 50 #define ADP8860_ISC2 0x19 /* Independent Sink Current LED2 */ 51 #define ADP8860_ISC1 0x1A /* Independent Sink Current LED1 */
H A D	adp8870_bl.c	48 #define ADP8870_ISCT1 0x1C /* Independent Sink Current Timer Register LED[7:5] */ 49 #define ADP8870_ISCT2 0x1D /* Independent Sink Current Timer Register LED[4:1] */ 51 #define ADP8870_ISC1 0x1F /* Independent Sink Current LED1 */ 52 #define ADP8870_ISC2 0x20 /* Independent Sink Current LED2 */ 53 #define ADP8870_ISC3 0x21 /* Independent Sink Current LED3 */ 54 #define ADP8870_ISC4 0x22 /* Independent Sink Current LED4 */ 55 #define ADP8870_ISC5 0x23 /* Independent Sink Current LED5 */ 56 #define ADP8870_ISC6 0x24 /* Independent Sink Current LED6 */ 57 #define ADP8870_ISC7 0x25 /* Independent Sink Current LED7 (Brightness Level 1-daylight) */ 58 #define ADP8870_ISC7_L2 0x26 /* Independent Sink Current LED7 (Brightness Level 2-bright) */ 59 #define ADP8870_ISC7_L3 0x27 /* Independent Sink Current LED7 (Brightness Level 3-office) */ 60 #define ADP8870_ISC7_L4 0x28 /* Independent Sink Current LED7 (Brightness Level 4-indoor) */ 61 #define ADP8870_ISC7_L5 0x29 /* Independent Sink Current LED7 (Brightness Level 5-dark) */
/linux-4.1.27/drivers/media/pci/cx88/
H A D	cx88-reg.h	104 #define MO_DMA7_PTR1 0x300018 // {24}RW* DMA Current Ptr : Ch#7 105 #define MO_DMA8_PTR1 0x30001C // {24}RW* DMA Current Ptr : Ch#8 108 #define MO_DMA21_PTR1 0x300080 // {24}R0* DMA Current Ptr : Ch#21 109 #define MO_DMA22_PTR1 0x300084 // {24}R0* DMA Current Ptr : Ch#22 110 #define MO_DMA23_PTR1 0x300088 // {24}R0* DMA Current Ptr : Ch#23 111 #define MO_DMA24_PTR1 0x30008C // {24}R0* DMA Current Ptr : Ch#24 112 #define MO_DMA25_PTR1 0x300090 // {24}R0* DMA Current Ptr : Ch#25 113 #define MO_DMA26_PTR1 0x300094 // {24}R0* DMA Current Ptr : Ch#26 114 #define MO_DMA27_PTR1 0x300098 // {24}R0* DMA Current Ptr : Ch#27 115 #define MO_DMA28_PTR1 0x30009C // {24}R0* DMA Current Ptr : Ch#28 116 #define MO_DMA29_PTR1 0x3000A0 // {24}R0* DMA Current Ptr : Ch#29 117 #define MO_DMA30_PTR1 0x3000A4 // {24}R0* DMA Current Ptr : Ch#30 118 #define MO_DMA31_PTR1 0x3000A8 // {24}R0* DMA Current Ptr : Ch#31 119 #define MO_DMA32_PTR1 0x3000AC // {24}R0* DMA Current Ptr : Ch#32
/linux-4.1.27/drivers/net/ethernet/stmicro/stmmac/
H A D	dwmac_dma.h	42 #define DMA_CUR_TX_BUF_ADDR 0x00001050 /* Current Host Tx Buffer */ 43 #define DMA_CUR_RX_BUF_ADDR 0x00001054 /* Current Host Rx Buffer */
/linux-4.1.27/drivers/staging/comedi/drivers/
H A D	dt2815.c	34 [3] - Current offset configuration 128 options[3] Current offset configuration
/linux-4.1.27/include/linux/usb/
H A D	otg-fsm.h	34 #define MPC_LOC printk("Current Location [%s]:[%d]\n", __FILE__, __LINE__) 119 /* Current usb protocol used: 0:undefine; 1:host; 2:client */
/linux-4.1.27/arch/mips/loongson/lemote-2f/
H A D	ec_kb3310b.h	177 EVENT_USB_OC2, /* USB2 Over Current occurred */ 178 EVENT_USB_OC0, /* USB0 Over Current occurred */
/linux-4.1.27/net/dccp/ccids/
H A D	ccid3.h	79 * @tx_x: Current sending rate in 64 * bytes per second 83 * @tx_p: Current loss event rate (0-1) scaled by 1000000
/linux-4.1.27/include/linux/mfd/wm831x/
H A D	pdata.h	30 int ilim; /** Current limit in microamps */ 80 int isel; /** Current for pen down (uA) */
/linux-4.1.27/drivers/net/wireless/libertas_tf/
H A D	libertas_tf.h	95 * Current version of MAC has a 32x6 multicast address buffer. 210 /** Current command */ 265 /* Current Tx packet status */ 288 /* Current Rx packet status */
/linux-4.1.27/drivers/staging/rtl8188eu/include/
H A D	rtw_led.h	59 enum LED_STATE_871x CurrLedState; /* Current LED state. */
/linux-4.1.27/drivers/cpufreq/
H A D	e_powersaver.c	144 printk(KERN_INFO "eps: Current voltage = %dmV\n", eps_set_state() 147 printk(KERN_INFO "eps: Current multiplier = %d\n", eps_set_state() 246 printk(KERN_INFO "eps: Current voltage = %dmV\n", eps_cpu_init() 249 printk(KERN_INFO "eps: Current multiplier = %d\n", current_multiplier); eps_cpu_init()
/linux-4.1.27/arch/x86/platform/efi/
H A D	efi_32.c	64 /* Current pgd is swapper_pg_dir, we'll restore it later: */ efi_call_phys_prolog()
/linux-4.1.27/arch/x86/boot/
H A D	video-bios.c	40 ireg.ah = 0x0f; /* Get Current Video Mode */ set_bios_mode()
/linux-4.1.27/drivers/usb/storage/
H A D	protocol.h	4 * Current development and maintenance by:
H A D	scsiglue.h	4 * Current development and maintenance by:
H A D	debug.h	4 * Current development and maintenance by:
/linux-4.1.27/drivers/video/fbdev/omap/
H A D	lcd_palmte.c	5 * Current version : Laurent Gonzalez <palmte.linux@free.fr>
H A D	lcd_palmtt.c	3 * Current version : Marek Vasut <marek.vasut@gmail.com>
H A D	lcd_palmz71.c	5 * Current version : Laurent Gonzalez
/linux-4.1.27/include/net/irda/
H A D	irlap.h	112 int s; /* Current slot */ 127 volatile IRLAP_STATE state; /* Current state */ 179 int window_size; /* Current negotiated window size */ 193 __u8 s; /* Current slot */
/linux-4.1.27/arch/m68k/amiga/
H A D	amisound.c	40 * Current period (set by dmasound.c)
/linux-4.1.27/arch/m68k/ifpsp060/
H A D	iskeleton.S	100 | * Current PC * * Current PC * 140 | * Current PC * * Current PC *
/linux-4.1.27/arch/metag/include/asm/mach/
H A D	arch.h	54 * Current machine - only accessible during boot.
/linux-4.1.27/arch/arm/include/asm/mach/
H A D	arch.h	69 * Current machine - only accessible during boot.
/linux-4.1.27/sound/pci/ctxfi/
H A D	ctresource.h	38 u32 conj:12; /* Current conjugate index */
/linux-4.1.27/drivers/media/rc/img-ir/
H A D	img-ir-hw.h	224 * @decoder: Current decoder settings. 226 * @clk_hz: Current core clock rate in Hz. 230 * @mode: Current decode mode.
/linux-4.1.27/fs/ntfs/
H A D	volume.h	89 LCN mft_zone_pos; /* Current position in the mft zone. */ 90 LCN data1_zone_pos; /* Current position in the first data 92 LCN data2_zone_pos; /* Current position in the second data
/linux-4.1.27/include/uapi/linux/usb/
H A D	ch11.h	18 * Current Wireless USB host hardware (Intel i1480 for example) allows 186 #define HUB_CHAR_OCPM 0x0018 /* Over-Current Protection Mode mask */ 187 #define HUB_CHAR_COMMON_OCPM 0x0000 /* All ports Over-Current reporting */
/linux-4.1.27/drivers/media/usb/pvrusb2/
H A D	pvrusb2-hdw-internal.h	301 unsigned int freqValTelevision; /* Current freq for tv mode */ 302 unsigned int freqValRadio; /* Current freq for radio mode */ 303 unsigned int freqSlotTelevision; /* Current slot for tv mode */ 304 unsigned int freqSlotRadio; /* Current slot for radio mode */ 308 /* Current tuner info - this information is polled from the I2C bus */
/linux-4.1.27/include/linux/mfd/
H A D	db8500-prcmu.h	118 * @NO_PWRST: Current power state init 119 * @AP_BOOT: Current power state is apBoot 120 * @AP_EXECUTE: Current power state is apExecute 121 * @AP_DEEP_SLEEP: Current power state is apDeepSleep 122 * @AP_SLEEP: Current power state is apSleep 123 * @AP_IDLE: Current power state is apIdle 124 * @AP_RESET: Current power state is apReset
H A D	si476x-core.h	112 * @state: Current power state of the device. 327 * @tp: Current channel's TP flag. 328 * @pty: Current channel's PTY code. 329 * @pi: Current channel's PI code.
/linux-4.1.27/drivers/scsi/
H A D	nsp32.h	497 struct scsi_cmnd *SCpnt; /* Current Handling struct scsi_cmnd */ 501 int cur_entry; /* Current SG entry number */ 582 nsp32_lunt *cur_lunt; /* Current connected LUN table */ 585 nsp32_target *cur_target; /* Current connected SCSI ID */ 587 int cur_id; /* Current connected target ID */ 588 int cur_lun; /* Current connected target LUN */
/linux-4.1.27/drivers/net/wireless/b43legacy/
H A D	b43legacy.h	449 /* Current idle TSSI */ 471 /* Current Radio Attenuation for TXpower recalculation. */ 473 /* Current Baseband Attenuation for TXpower recalculation. */ 475 /* Current TXpower control value for TXpower recalculation. */ 484 /* Current Interference Mitigation mode */ 595 /* Current BSSID (can be NULL). */
/linux-4.1.27/include/target/iscsi/
H A D	iscsi_target_core.h	416 /* Current struct iscsi_pdu in struct iscsi_cmd->pdu_list */ 422 /* Current struct iscsi_seq in struct iscsi_cmd->seq_list */ 470 /* Current struct iscsi_pdu used for DataPDUInOrder=No */ 474 /* Current struct iscsi_seq used for DataSequenceInOrder=No */ 535 /* IFMarkInt's Current Value */ 537 /* OFMarkInt's Current Value */
/linux-4.1.27/drivers/staging/lustre/lustre/include/
H A D	lustre_import.h	219 /** Current import state */ 226 /** Current import generation. Incremented on every reconnect */ 259 * Current connection. \a imp_connection is imp_conn_current->oic_conn
H A D	lustre_fld.h	110 * Current hash to be used to chose an export. */
/linux-4.1.27/drivers/isdn/isdnloop/
H A D	isdnloop.h	83 int l2_proto[ISDNLOOP_BCH]; /* Current layer-2-protocol */
/linux-4.1.27/drivers/hwmon/
H A D	ina2xx.c	5 * Zero Drift Bi-Directional Current/Power Monitor with I2C Interface 9 * Bi-Directional Current/Power Monitor with I2C Interface 13 * Bi-Directional Current/Power Monitor with I2C Interface 17 * Bi-directional Current/Power Monitor with I2C Interface
H A D	ltc4151.c	2 * Driver for Linear Technology LTC4151 High Voltage I2C Current
H A D	ltc4260.c	131 /* Current (via sense resistor) */
/linux-4.1.27/drivers/net/ethernet/qualcomm/
H A D	qca_framing.h	102 /* Current decoding state */
/linux-4.1.27/drivers/message/fusion/lsi/
H A D	mpi_lan.h	200 /* LAN Current Device State defines */
/linux-4.1.27/drivers/mfd/
H A D	wm8350-regmap.c	56 { 0x8000, 0x0000, 0xFFFF }, /* R29 - Over Current Interrupt status */ 64 { 0x8000, 0x8000, 0x0000 }, /* R37 - Over Current Int status Mask */ 199 { 0x903F, 0x903F, 0xFFFF }, /* R172 - Current Sink Driver A */ 201 { 0x903F, 0x903F, 0xFFFF }, /* R174 - Current Sink Driver B */
/linux-4.1.27/drivers/net/wireless/rt2x00/
H A D	rt2x00firmware.c	81 rt2x00_err(rt2x00dev, "Current firmware does not support detected chipset\n"); rt2x00lib_request_firmware()
/linux-4.1.27/drivers/staging/ft1000/ft1000-usb/
H A D	ft1000_ioctl.h	75 unsigned long ConTm; /* Current session connection time
/linux-4.1.27/drivers/staging/rtl8712/
H A D	rtl871x_led.h	88 u32 CurrLedState; /* Current LED state. */
/linux-4.1.27/drivers/net/ethernet/broadcom/
H A D	b44.h	76 #define B44_DMATX_STAT 0x020CUL /* DMA TX Current Active Desc. + Status */ 77 #define DMATX_STAT_CDMASK 0x00000fff /* Current Descriptor Mask */ 97 #define B44_DMARX_STAT 0x021CUL /* DMA RX Current Active Desc. + Status */ 98 #define DMARX_STAT_CDMASK 0x00000fff /* Current Descriptor Mask */
/linux-4.1.27/drivers/clocksource/
H A D	timer-u300.c	59 /* OS Timer Current Count Register 32bit (R/-) */ 95 /* DD Timer Current Count Register 32bit (R/-) */ 131 /* GP1 Timer Current Count Register 32bit (R/-) */ 167 /* GP2 Timer Current Count Register 32bit (R/-) */
/linux-4.1.27/drivers/char/
H A D	nsc_gpio.c	86 /* View Current pin settings */ nsc_gpio_write()
/linux-4.1.27/drivers/usb/host/
H A D	ohci-pxa27x.c	55 #define UHCPCED (0x001C) /* UHC Period Current Endpt Descr */ 57 #define UHCCCED (0x0024) /* UHC Control Current Endpt Descr */ 59 #define UHCBCED (0x002C) /* UHC Bulk Current Endpt Descr */ 69 #define UHCRHDA_OCPM (1 << 11) /* Over Current Protection Mode */
/linux-4.1.27/include/trace/events/
H A D	signal.h	44 * Current process sends a 'sig' signal to 'task' process with
/linux-4.1.27/include/uapi/linux/nfsd/
H A D	nfsfh.h	48 * Current values:
/linux-4.1.27/arch/powerpc/platforms/powernv/
H A D	opal-flash.c	56 #define VALIDATE_CUR_UNKNOWN 3 /* Current fixpack level is unknown */ 58 * Current T side will be committed to P side before being replace with new 63 * Current T side will be committed to P side before being replaced with new 169 /* Current and candidate image version details */ validate_show()
/linux-4.1.27/arch/mips/include/asm/sn/
H A D	gda.h	31 #define GDA_VERSION 2 /* Current GDA version # */
/linux-4.1.27/arch/mips/kernel/
H A D	binfmt_elfn32.c	63 short pr_cursig; /* Current signal */
H A D	binfmt_elfo32.c	84 short pr_cursig; /* Current signal */
/linux-4.1.27/arch/parisc/kernel/
H A D	binfmt_elf32.c	47 short pr_cursig; /* Current signal */
/linux-4.1.27/arch/arm64/kernel/
H A D	efi-entry.S	41 * x0 and x1 are already set up by firmware. Current runtime
/linux-4.1.27/arch/hexagon/mm/
H A D	vm_tlb.c	70 /* Current Virtual Machine has only one map active at a time */ flush_tlb_mm()
/linux-4.1.27/arch/arm/mach-omap2/
H A D	sdrc2xxx.c	151 fast_dll |= dll_cnt; /* Current lock mode */ omap2xxx_sdrc_init_params()
/linux-4.1.27/mm/
H A D	vmacache.c	26 * to worry about other threads' seqnum. Current's vmacache_flush_all()
/linux-4.1.27/include/linux/i2c/
H A D	adp8860.h	124 * Independent Current Sinks / LEDS
H A D	adp8870.h	140 * Independent Current Sinks / LEDS
/linux-4.1.27/drivers/isdn/icn/
H A D	icn.h	153 int l2_proto[ICN_BCH]; /* Current layer-2-protocol */ 163 struct sk_buff *xskb[ICN_BCH]; /* Current transmitted skb */
/linux-4.1.27/drivers/net/ethernet/xilinx/
H A D	ll_temac.h	312 * 3 completed Current descriptor completed 358 u32 options; /* Current options word */
/linux-4.1.27/drivers/net/irda/
H A D	irda-usb.h	164 __u16 xbofs; /* Current xbofs setting */ 166 __u32 speed; /* Current speed */
H A D	girbil-sir.c	44 /* LED Current Register (0x2) */
H A D	mcs7780.h	108 unsigned int speed; /* Current speed */
/linux-4.1.27/drivers/power/
H A D	max8903_charger.c	95 /* Set Current-Limit-Mode 1:DC 0:USB */ max8903_dcin() 136 /* Do not touch Current-Limit-Mode */ max8903_usbin()
/linux-4.1.27/include/sound/
H A D	seq_midi_emul.h	49 unsigned char control[128]; /* Current value of all controls */ 50 unsigned char note[128]; /* Current status for all notes */
/linux-4.1.27/sound/pci/emu10k1/
H A D	p17v.h	28 #define P17V_PLAYBACK_FIFO_PTR 0x08 /* Current playback fifo pointer 32 #define P17V_CAPTURE_FIFO_PTR 0x13 /* Current capture fifo pointer
/linux-4.1.27/drivers/iio/adc/
H A D	ad7793.c	82 #define AD7793_CONF_BO_EN (1 << 13) /* Burnout Current Enable */ 115 /* IO (Excitation Current Sources) Register Bit Designations (AD7793_REG_IO) */ 125 #define AD7793_IO_IXCEN_10uA (1 << 0) /* Excitation Current 10uA */ 126 #define AD7793_IO_IXCEN_210uA (2 << 0) /* Excitation Current 210uA */ 127 #define AD7793_IO_IXCEN_1mA (3 << 0) /* Excitation Current 1mA */
/linux-4.1.27/drivers/video/fbdev/sis/
H A D	sis.h	335 #define Q_WRITE_PTR 0x85C4 /* Current write pointer */ 336 #define Q_READ_PTR 0x85C8 /* Current read pointer */ 508 int cmdqueuelength; /* Current (for accel) */
/linux-4.1.27/drivers/isdn/act2000/
H A D	act2000.h	120 unsigned short fsm_state; /* Current D-Channel state */
/linux-4.1.27/drivers/leds/
H A D	leds-lp55xx-common.h	165 * @led_current : Current setting at each led channel
/linux-4.1.27/drivers/net/caif/
H A D	caif_spi.c	152 "Current CMD: 0x%x\n", cfspi->cmd); dbgfs_state() 158 "Current TX len: %d\n", cfspi->tx_cpck_len); dbgfs_state() 160 "Current RX len: %d\n", cfspi->rx_cpck_len); dbgfs_state() 216 "Current frame:\n"); dbgfs_frame()
/linux-4.1.27/drivers/media/platform/omap3isp/
H A D	isppreview.h	119 * @state: Current preview pipeline state
/linux-4.1.27/drivers/net/wireless/ath/ath9k/
H A D	htc_hst.h	148 /* Current service IDs */
/linux-4.1.27/drivers/media/platform/
H A D	via-camera.h	14 #define VCR_IC_VBIBUF 0x0400 /* Current VBI buffer */
/linux-4.1.27/drivers/media/radio/
H A D	radio-isa.h	52 /* Current frequency */
/linux-4.1.27/drivers/net/wireless/orinoco/
H A D	cfg.c	251 * Current implementation uses 2347 as the default and orinoco_set_wiphy_params()
/linux-4.1.27/drivers/scsi/csiostor/
H A D	csio_rnode.h	103 uint8_t cur_evt; /* Current event */
/linux-4.1.27/drivers/spi/
H A D	spi-pxa2xx.h	70 /* Current message transfer state info */
/linux-4.1.27/drivers/staging/speakup/
H A D	spk_types.h	61 /* Current index into highbuf */
/linux-4.1.27/drivers/staging/lustre/lustre/fld/
H A D	fld_internal.h	97 * Current number of cached entries. Protected by \a fci_lock */
/linux-4.1.27/arch/x86/include/asm/xen/
H A D	interface_64.h	57 * Never returns if successful. Current kernel context is lost.
/linux-4.1.27/arch/sparc/include/uapi/asm/
H A D	pstate.h	15 #define PSTATE_CLE _AC(0x0000000000000200,UL) /* Current Little Endian.*/

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