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Searched refs:CCR (Results 1 – 25 of 25) sorted by relevance

/linux-4.1.27/arch/arm/plat-omap/
Ddma.c208 ccr = p->dma_read(CCR, lch); in omap_set_dma_priority()
213 p->dma_write(ccr, CCR, lch); in omap_set_dma_priority()
232 ccr = p->dma_read(CCR, lch); in omap_set_dma_transfer_params()
236 p->dma_write(ccr, CCR, lch); in omap_set_dma_transfer_params()
248 val = p->dma_read(CCR, lch); in omap_set_dma_transfer_params()
273 p->dma_write(val, CCR, lch); in omap_set_dma_transfer_params()
323 l = p->dma_read(CCR, lch); in omap_set_dma_src_params()
326 p->dma_write(l, CCR, lch); in omap_set_dma_src_params()
425 l = p->dma_read(CCR, lch); in omap_set_dma_dest_params()
428 p->dma_write(l, CCR, lch); in omap_set_dma_dest_params()
[all …]
/linux-4.1.27/drivers/dma/
Dtxx9dmac.h80 TXX9_DMA_REG32(CCR); /* Channel Control Register */
90 u32 CCR; member
281 desc->hwdesc.CCR |= TXX9_DMA_CCR_INTENT; in txx9dmac_desc_set_INTENT()
283 desc->hwdesc32.CCR |= TXX9_DMA_CCR_INTENT; in txx9dmac_desc_set_INTENT()
297 desc->hwdesc.CCR = ccr; in txx9dmac_desc_set_nosimple()
301 desc->hwdesc32.CCR = ccr; in txx9dmac_desc_set_nosimple()
Dtxx9dmac.c298 channel64_readl(dc, CCR), in txx9dmac_dump_regs()
310 channel32_readl(dc, CCR), in txx9dmac_dump_regs()
316 channel_writel(dc, CCR, TXX9_DMA_CCR_CHRST); in txx9dmac_reset_chan()
329 channel_writel(dc, CCR, 0); in txx9dmac_reset_chan()
369 channel64_writel(dc, CCR, dc->ccr); in txx9dmac_dostart()
390 channel32_writel(dc, CCR, dc->ccr); in txx9dmac_dostart()
395 channel32_writel(dc, CCR, dc->ccr); in txx9dmac_dostart()
487 desc->SAIR, desc->DAIR, desc->CCR, desc->CSR); in txx9dmac_dump_desc()
500 d->SAIR, d->DAIR, d->CCR, d->CSR); in txx9dmac_dump_desc()
Domap-dma.c295 omap_dma_chan_write(c, CCR, d->ccr | CCR_ENABLE); in omap_dma_start()
308 val = omap_dma_chan_read(c, CCR); in omap_dma_stop()
318 val = omap_dma_chan_read(c, CCR); in omap_dma_stop()
320 omap_dma_chan_write(c, CCR, val); in omap_dma_stop()
324 val = omap_dma_chan_read(c, CCR); in omap_dma_stop()
342 omap_dma_chan_write(c, CCR, val); in omap_dma_stop()
407 omap_dma_chan_write(c, CCR, d->ccr); in omap_dma_start_desc()
Dpl330.c338 CCR, enumerator
1321 off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr); in _setup_req()
/linux-4.1.27/drivers/clocksource/
Dtcb_clksrc.c102 __raw_writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR)); in tc_mode()
125 regs + ATMEL_TC_REG(2, CCR)); in tc_mode()
151 tcaddr + ATMEL_TC_REG(2, CCR)); in tc_next_event()
233 __raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR)); in tcb_setup_dual_chan()
241 __raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR)); in tcb_setup_dual_chan()
257 __raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR)); in tcb_setup_single_chan()
/linux-4.1.27/arch/arm/mach-imx/
Dpm-imx6.c34 #define CCR 0x0 macro
219 val = readl_relaxed(ccm_base + CCR); in imx6_enable_rbc()
222 writel_relaxed(val, ccm_base + CCR); in imx6_enable_rbc()
225 val = readl_relaxed(ccm_base + CCR); in imx6_enable_rbc()
228 writel(val, ccm_base + CCR); in imx6_enable_rbc()
252 val = readl_relaxed(ccm_base + CCR); in imx6q_enable_wb()
255 writel_relaxed(val, ccm_base + CCR); in imx6q_enable_wb()
/linux-4.1.27/arch/cris/arch-v10/kernel/
Dkgdb.c307 P4, CCR, P6, MOF, enumerator
618 else if (regno == CCR) { in write_register()
621 hex2mem ((unsigned char *)&(current_reg->ccr) + (regno-CCR) * sizeof(unsigned short), in write_register()
656 else if (regno == P4 || regno == CCR) { in read_register()
/linux-4.1.27/arch/arm/mach-omap1/
Ddma.c60 [CCR] = { 0x0002, 0x40, OMAP_DMA_REG_16BIT },
217 l = dma_read(CCR, lch); in omap1_clear_dma()
219 dma_write(l, CCR, lch); in omap1_clear_dma()
/linux-4.1.27/drivers/pwm/
Dpwm-atmel-tcb.c180 regs + ATMEL_TC_REG(group, CCR)); in atmel_tcb_pwm_disable()
183 ATMEL_TC_REG(group, CCR)); in atmel_tcb_pwm_disable()
265 regs + ATMEL_TC_REG(group, CCR)); in atmel_tcb_pwm_enable()
/linux-4.1.27/Documentation/frv/
Dkernel-ABI.txt101 CCR.ICC2 Virtual interrupt disablement tracking
132 CCR/CCCR - Mostly Clobbered
181 (*) CCR.ICC2.Z [Zero flag]
187 (*) CCR.ICC2.C [Carry flag]
/linux-4.1.27/drivers/net/can/
Dbfin_can.c120 #define CCR 0x0080 /* CAN Configuration Mode Request */ macro
210 writew(SRS | CCR, &reg->control); in bfin_can_set_reset_mode()
211 writew(CCR, &reg->control); in bfin_can_set_reset_mode()
265 writew(readw(&reg->control) & ~CCR, &reg->control); in bfin_can_set_normal_mode()
/linux-4.1.27/arch/arm/mach-omap2/
Ddma.c59 [CCR] = { 0x0080, 0x60, OMAP_DMA_REG_32BIT },
/linux-4.1.27/arch/frv/mm/
Dtlb-miss.S46 # SCR2 - saved CCR
91 # SCR2 - saved CCR
/linux-4.1.27/sound/pci/emu10k1/
Demu10k1_callback.c434 snd_emu10k1_ptr_write(hw, CCR, ch, 0x1c << 16); in start_voice()
447 snd_emu10k1_ptr_write(hw, CCR, ch, val); in start_voice()
Demu10k1_main.c81 snd_emu10k1_ptr_write(emu, CCR, ch, 0); in snd_emu10k1_voice_init()
2080 CPF, PTRX, CVCF, VTFT, Z1, Z2, PSST, DSL, CCCA, CCR, CLP,
/linux-4.1.27/include/linux/
Domap-dma.h155 CSDP, CCR, CICR, CSR, enumerator
/linux-4.1.27/sound/soc/dwc/
Ddesignware_i2s.c32 #define CCR 0x010 macro
272 i2s_write_reg(dev->i2s_base, CCR, ccr); in dw_i2s_hw_params()
/linux-4.1.27/Documentation/parisc/
Dregisters13 CR10 (CCR) lazy FPU saving*
/linux-4.1.27/arch/blackfin/include/asm/
Dbfin_can.h117 #define CCR 0x0080 /* CAN Configuration Mode Request */ macro
/linux-4.1.27/Documentation/powerpc/
Dtransactional_memory.txt62 Checkpointed registers include all GPRs, FPRs, VRs/VSRs, LR, CCR/CR, CTR, FPCSR
/linux-4.1.27/include/sound/
Demu10k1.h439 #define CCR 0x09 /* Cache control register */ macro
/linux-4.1.27/drivers/tty/
Dsynclink_gt.c400 #define CCR 0x89 /* clock control */ macro
3947 wr_reg8(info, CCR, 0x49); in enable_loopback()
4230 wr_reg8(info, CCR, 0x69); in async_mode()
4443 wr_reg8(info, CCR, (unsigned char)val); in sync_mode()
Dsynclink.c342 #define CCR 0x06 /* Channel Control Register */ macro
5184 usc_OutReg( info, CCR, RegValue ); in usc_set_sdlc_mode()
6106 usc_OutReg( info, CCR, 0x0100 ); in usc_loopback_frame()
/linux-4.1.27/drivers/video/fbdev/
Dimsttfb.c95 CCR = 0x00000008L,