| /linux-4.1.27/drivers/staging/rtl8188eu/hal/ |
| D | rtl8188eu_led.c | 39 usb_write8(padapter, REG_LEDCFG2, (LedCfg&0xf0)|BIT5|BIT6); /* SW control led0 on. */ in SwLedOn()
63 usb_write8(padapter, REG_LEDCFG2, (LedCfg|BIT3|BIT5|BIT6)); in SwLedOff()
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| D | odm_RTL8188E.c | 170 phy_set_bb_reg(adapter, 0x864, BIT8|BIT7|BIT6, 1); in dm_fast_training_init()
210 BIT8|BIT7|BIT6, optional_ant); in rtl88eu_dm_update_rx_idle_ant()
214 BIT6|BIT7, default_ant); in rtl88eu_dm_update_rx_idle_ant()
219 BIT8|BIT7|BIT6, optional_ant); in rtl88eu_dm_update_rx_idle_ant()
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| D | rtl8188e_cmd.c | 610 if (haldata->RegFwHwTxQCtrl&BIT6) { in rtl8188e_set_FwJoinBssReport_cmd()
616 usb_write8(adapt, REG_FWHW_TXQ_CTRL+2, (haldata->RegFwHwTxQCtrl&(~BIT6))); in rtl8188e_set_FwJoinBssReport_cmd()
617 haldata->RegFwHwTxQCtrl &= (~BIT6); in rtl8188e_set_FwJoinBssReport_cmd()
659 usb_write8(adapt, REG_FWHW_TXQ_CTRL+2, (haldata->RegFwHwTxQCtrl|BIT6)); in rtl8188e_set_FwJoinBssReport_cmd()
660 haldata->RegFwHwTxQCtrl |= BIT6; in rtl8188e_set_FwJoinBssReport_cmd()
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| D | usb_halinit.c | 1177 usb_write8(adapt, REG_FWHW_TXQ_CTRL+2, (haldata->RegFwHwTxQCtrl) | BIT6); in ResumeTxBeacon()
1178 haldata->RegFwHwTxQCtrl |= BIT6; in ResumeTxBeacon()
1191 usb_write8(adapt, REG_FWHW_TXQ_CTRL+2, (haldata->RegFwHwTxQCtrl) & (~BIT6)); in StopTxBeacon()
1192 haldata->RegFwHwTxQCtrl &= (~BIT6); in StopTxBeacon()
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| /linux-4.1.27/drivers/staging/rtl8188eu/include/ |
| D | rtl8188e_spec.h | 32 #define BIT6 0x00000040 macro
506 #define HSIMR_RON_INT_EN BIT6
513 #define HSISR_RON_INT_EN BIT6
546 #define CMD_EFUSE_PATCH_ERR BIT6
557 #define RRSR_12M BIT6
636 #define IMR_MGNTDOK_88E BIT6 /* Management Queue DMA OK */
699 #define StopBecon BIT6
725 #define RCR_CBSSID_DATA BIT6 /* Accept BSSID match (Data)*/
1206 #define SDIO_HIMR_TXBCNOK_MSK BIT6
1232 #define SDIO_HISR_TXBCNOK BIT6
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| D | rtw_sreset.h | 39 #define WIFI_IF_NOT_EXIST BIT6
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| D | odm_debug.h | 66 #define ODM_COMP_ANT_DIV BIT6
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| D | odm.h | 423 ODM_BB_ANT_DIV = BIT6,
469 ODM_RF_RX_C = BIT6,
507 ODM_AD_HOC = BIT6,
521 ODM_WM_AC = BIT6,
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| D | Hal8188EPhyCfg.h | 96 WIRELESS_MODE_AC = BIT6
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| D | osdep_service.h | 94 #define BIT6 0x00000040 macro
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| D | pwrseq.h | 289 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0}, \
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| /linux-4.1.27/drivers/staging/rtl8192e/rtl8192e/ |
| D | r8192E_hw.h | 236 #define IMR_MGNTDOK BIT6
251 #define TPPoll_MQ BIT6
291 #define AcmHw_VoqStatus BIT6
381 #define RRSR_12M BIT6
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| /linux-4.1.27/drivers/video/fbdev/via/ |
| D | lcd.c | 390 viafb_write_reg_mask(CRA2, VIACR, 0xC0, BIT7 + BIT6); in load_lcd_scaling()
625 viafb_write_reg_mask(CRD3, VIACR, 0xC0, BIT6 + BIT7); in integrated_lvds_disable()
634 viafb_write_reg_mask(CR91, VIACR, 0xC0, BIT6 + BIT7); in integrated_lvds_disable()
647 viafb_write_reg_mask(CRD2, VIACR, 0x40, BIT6); in integrated_lvds_disable()
653 viafb_write_reg_mask(CRD2, VIACR, 0xC0, BIT6 + BIT7); in integrated_lvds_disable()
677 viafb_write_reg_mask(CR91, VIACR, 0, BIT6 + BIT7); in integrated_lvds_enable()
686 viafb_write_reg_mask(CRD3, VIACR, 0, BIT6 + BIT7); in integrated_lvds_enable()
702 viafb_write_reg_mask(CRD2, VIACR, 0, BIT6); in integrated_lvds_enable()
708 viafb_write_reg_mask(CRD2, VIACR, 0, BIT6 + BIT7); in integrated_lvds_enable()
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| D | dvi.c | 69 viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT6 + BIT7); in viafb_tmds_trasmitter_identify()
76 BIT5 + BIT6 + BIT7); in viafb_tmds_trasmitter_identify()
435 viafb_write_reg_mask(CR88, VIACR, 0x00, BIT6 + BIT0); in viafb_dvi_enable()
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| D | hw.c | 1684 viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6); in viafb_init_dac()
1691 viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6); in viafb_init_dac()
1695 viafb_write_reg_mask(CR6A, VIACR, 0x40, BIT6); in viafb_init_dac()
2048 viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6); in enable_second_display_channel()
2050 viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6); in enable_second_display_channel()
2056 viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6); in disable_second_display_channel()
2058 viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6); in disable_second_display_channel()
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| D | share.h | 34 #define BIT6 0x40 macro
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| /linux-4.1.27/drivers/scsi/ |
| D | dc395x.h | 69 #define BIT6 0x00000040 macro
137 #define DATAIN BIT6
179 #define EN_ATN_STOP BIT6
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| /linux-4.1.27/drivers/net/wireless/rtlwifi/btcoexist/ |
| D | halbt_precomp.h | 54 #define BIT6 0x00000040 macro
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| D | halbtc8821a2ant.h | 31 #define BT_INFO_8821A_2ANT_B_A2DP BIT6
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| D | halbtc8723b2ant.h | 34 #define BT_INFO_8723B_2ANT_B_A2DP BIT6
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| D | halbtc8723b1ant.h | 31 #define BT_INFO_8723B_1ANT_B_A2DP BIT6
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| D | halbtc8192e2ant.h | 31 #define BT_INFO_8192E_2ANT_B_A2DP BIT6
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| D | halbtc8821a1ant.h | 33 #define BT_INFO_8821A_1ANT_B_A2DP BIT6
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| D | halbtcoutsrc.h | 107 #define ALGO_TRACE_FW_EXEC BIT6
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| D | halbtc8723b1ant.c | 891 real_byte5 &= ~BIT6; in halbtc8723b1ant_set_fw_ps_tdma()
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| /linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8821ae/ |
| D | pwrseq.h | 307 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0 \
442 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0 \
466 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 , BIT6 \
664 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0 \
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| /linux-4.1.27/drivers/staging/rtl8192u/ |
| D | r8192U_hw.h | 235 #define AcmHw_VoqStatus BIT6
313 #define RRSR_12M BIT6
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| D | r8192U.h | 52 #define BIT6 0x00000040 macro
99 #define COMP_POWER BIT6
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| D | r8192U_dm.c | 2381 if (tmp1byte&BIT6 || tmp1byte&BIT0) { in dm_check_pbc_gpio()
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| /linux-4.1.27/drivers/char/pcmcia/ |
| D | synclink_cs.c | 299 #define IRQ_EXITHUNT BIT6 // receive frame start
300 #define IRQ_RXTIME BIT6 // rx char timeout
307 #define XFW BIT6 // transmit FIFO write enable
679 #define CMD_RXRESET BIT6 // receiver reset
927 if (status & (BIT7 + BIT6)) { in rx_ready_async()
941 else if (status & BIT6) in rx_ready_async()
1483 info->read_status_mask |= BIT7 | BIT6; in mgslpc_change_params()
1485 info->ignore_status_mask |= BIT7 | BIT6; in mgslpc_change_params()
2191 set_reg_bits(info, CHA+DAFO, BIT6); in mgslpc_break()
2193 clear_reg_bits(info, CHA+DAFO, BIT6); in mgslpc_break()
[all …]
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| /linux-4.1.27/drivers/net/hamradio/ |
| D | z8530.h | 117 #define BIT6 1 /* 6 bit/8bit sync */ macro
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| /linux-4.1.27/drivers/tty/serial/ |
| D | zs.h | 172 #define BIT6 1 /* 6 bit/8bit sync */ macro
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| D | ip22zilog.h | 153 #define BIT6 1 /* 6 bit/8bit sync */ macro
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| D | sunzilog.h | 155 #define BIT6 1 /* 6 bit/8bit sync */ macro
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| D | pmac_zilog.h | 246 #define BIT6 1 /* 6 bit/8bit sync */ macro
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| /linux-4.1.27/include/uapi/linux/ |
| D | synclink.h | 24 #define BIT6 0x0040 macro
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| /linux-4.1.27/drivers/tty/ |
| D | synclinkmp.c | 416 #define RXINTE BIT6
422 #define IDLE BIT6
435 #define PMP BIT6
436 #define SHRT BIT6
2606 if (timerstatus0 & (BIT7 | BIT6)) in synclinkmp_interrupt()
2610 if (timerstatus1 & (BIT7 | BIT6)) in synclinkmp_interrupt()
4445 RegValue=BIT6; in async_mode()
4454 RegValue=BIT6; in async_mode()
4582 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */ in hdlc_mode()
4610 RegValue |= BIT6; in hdlc_mode()
[all …]
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| D | synclink_gt.c | 421 #define IRQ_CTS BIT6
1424 value |= BIT6; in set_break()
1426 value &= ~BIT6; in set_break()
4022 wr_reg32(info, RDCSR, BIT6); in rx_start()
4035 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0)); in rx_start()
4332 val |= BIT6; in sync_mode()
4424 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */ in sync_mode()
4426 val |= BIT6; /* 010, txclk = BRG */ in sync_mode()
4455 val = BIT7 + BIT6; break; in sync_mode()
4456 default: val = BIT6; // NRZ encodings in sync_mode()
[all …]
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| D | synclink.c | 506 #define RXSTATUS_IDLE_RECEIVED BIT6
546 #define TXSTATUS_IDLE_SENT BIT6
567 #define MISCSTATUS_DCD BIT6
591 #define SICR_DCD_INACTIVE BIT6
592 #define SICR_DCD (BIT7|BIT6)
627 #define TXSTATUS_IDLE_SENT BIT6
5220 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) | (BIT7 | BIT6)); in usc_enable_loopback()
5259 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) & ~(BIT7 | BIT6)); in usc_enable_loopback()
5929 RegValue |= BIT6; in usc_set_async_mode()
5986 RegValue |= BIT6; in usc_set_async_mode()
[all …]
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| /linux-4.1.27/drivers/net/wan/ |
| D | z85230.h | 138 #define BIT6 1 /* 6 bit/8bit sync */ macro
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| /linux-4.1.27/drivers/staging/rtl8192e/ |
| D | rtl819x_Qos.h | 28 #define BIT6 0x00000040 macro
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| D | rtllib.h | 131 #define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT6
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| /linux-4.1.27/drivers/staging/rtl8192u/ieee80211/ |
| D | rtl819x_Qos.h | 10 #define BIT6 0x00000040 macro
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| /linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8192de/ |
| D | reg.h | 390 #define RRSR_12M BIT6
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| /linux-4.1.27/drivers/scsi/lpfc/ |
| D | lpfc_hw4.h | 680 #define LPFC_SLI4_INTR6 BIT6
|