Lines Matching refs:BIT6
299 #define IRQ_EXITHUNT BIT6 // receive frame start
300 #define IRQ_RXTIME BIT6 // rx char timeout
307 #define XFW BIT6 // transmit FIFO write enable
679 #define CMD_RXRESET BIT6 // receiver reset
927 if (status & (BIT7 + BIT6)) { in rx_ready_async()
941 else if (status & BIT6) in rx_ready_async()
1483 info->read_status_mask |= BIT7 | BIT6; in mgslpc_change_params()
1485 info->ignore_status_mask |= BIT7 | BIT6; in mgslpc_change_params()
2191 set_reg_bits(info, CHA+DAFO, BIT6); in mgslpc_break()
2193 clear_reg_bits(info, CHA+DAFO, BIT6); in mgslpc_break()
3192 val |= BIT6; in hdlc_mode()
3195 val |= BIT6; in hdlc_mode()
3198 val |= BIT7 | BIT6; in hdlc_mode()
3282 clear_reg_bits(info, CHA + CCR0, BIT6); in hdlc_mode()
3449 val |= BIT6; in async_mode()
3632 val &= ~BIT6; in set_signals()
3634 val |= BIT6; in set_signals()
3691 else if (status & BIT6) in rx_get_frame()